Central PROCESS TM CP707 Small Signal Transistors Semiconductor Corp. PNP - Darlington Transistor Chip PROCESS DETAILS EPITAXIAL PLANAR 27 x 27 MILS PROCESS DIE SIZE 9.0 MILS 6.0 x 4.7 MILS DIE THICKNESS BASE BONDING PAD AREA TOP SIDE METALIZATION 7.0 x 6.3 MILS Al - 30,000Å BACK SIDE METALIZATION Au - 3,500Å EMITTER BONDING PAD AREA GEOMETRY B PRINCIPAL DEVICE TYPES CMPTA63 CMPTA64 CXTA64 CZTA64 MPSA63 MPSA64 E BACKSIDE COLLECTOR Please refer to selection guide on page 19 . 67 145 Adams Avenue Hauppauge, NY 11788 USA Phone (631) 435-1110 Fax (631) 435-1824 www.centralsemi.com