PROCESS Central CP307 TM Small Signal Transistors Semiconductor Corp. NPN - Silicon Darlington Transistor Chip PROCESS DETAILS PROCESS EPITAXIAL PLANAR DIE SIZE 27 x 27 MILS DIE THICKNESS 9.0 MILS BASE BONDING PAD AREA 6.0 x 4.7 MILS EMITTER BONDING PAD AREA 7.0 x 6.3 MILS TOP SIDE METALIZATION Al - 30,000Å BACK SIDE METALIZATION Au - 3,500Å GEOMETRY B PRINCIPAL DEVICE TYPES 2N6426 2N6427 CMPT6427 CMPTA13 CMPTA14 CXTA14 E CZTA14 MPSA13 MPSA14 Please refer to selection guide on page 19. BACKSIDE COLLECTOR 44 145 Adams Avenue Hauppauge, NY 11788 USA Phone (631) 435-1110 Fax (631) 435-1824 www.centralsemi.com