PROCESS Central CP14 47 TM Power Transistors Semiconductor Corp. NPN - Darlington Chip PROCESS DETAILS PROCESS EPITAXIAL BASE DIE SIZE 195 X 195 MILS DIE THICKNESS 12 MILS BASE BONDING PAD AREA 20 X 20 MILS EMITTER BONDING PAD AREA 40 X 40 MILS TOP SIDE METALIZATION Al - 30,000Å BACK SIDE METALIZATION Ti/Ni/Au - Ni-6,000Å; Au-6,000Å GEOMETRY B PRINCIPAL DEVICE TYPES MJ11012 MJ11014 MJ11016 2N6282 2N6283 2N6284 E BACKSIDE COLLECTOR Please refer to selection guide on page 20. 26 145 Adams Avenue Hauppauge, NY 11788 USA Phone (631) 435-1110 Fax (631) 435-1824 www.centralsemi.com