CXP921F064A
CMOS 16-bit Single Chip Microcomputer
Description
The CXP921F064A is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, clock prescaler,
remote control receive circuit, and as well as basic
configurations like a 16-bit CPU, ROM, RAM, and I/O
port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
104 pin LFLGA (Plastic)
Features
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, generalpurpose register of 16-bit × 8-pin × 16-bank
configuration
• Minimum instruction cycle
100ns at 20MHz operation (2.7 to 3.3V)
61µs at 32kHz operation (2.2 to 3.3V)
• Incorporated Flash ROM capacity
256K bytes
• Incorporated RAM capacity
10K bytes
• Peripheral functions
— A/D converter
8-bit 12 analog input, 2 channels, successive approximation system,
automatic scanning function, (Conversion time: 3.4µs at 20MHz)
— Serial interface
128-byte buffer RAM, 3 channels
8-stage FIFO, 1 channel (supports special mode master/slave)
— I2C bus interface
64-byte buffer RAM , 2 channels
(supports master/slave and automatic transfer mode)
— Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit timer, 3 channels
— Real-time pulse generator
5-bit output, 1 channel (2-stage FIFO)
— Clock prescaler
— Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO
• Interruption
30 factors, 30 vectors, multi-interruption and priority selection possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP/LQFP
104-pin plastic LFLGA
• Mask ROM
CXP921064A
• Piggy/evaluation chip
CXP921000A
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00250A18-PS
BUFFER
RAM
FIFO
SERIAL
INTERFACE
UNIT (CH2)
SERIAL
INTERFACE
UNIT (CH3)
CS2
SI2
SO2
SCK2
SI3
SO3
SCK3
RMC
TMO
TO
REMOCON
FIFO
16-BIT TIMER (CH2)
16-BIT TIMER (CH1)
16-BIT TIMER (CH0)
8-BIT TIMER (CH1)
8-BIT TIMER/COUNTER (CH0)
BUFFER
RAM
I2C BUS
INTERFACE
UNIT (CH1)
SCL1
SDA1
EC
BUFFER
RAM
I2C BUS
INTERFACE
UNIT (CH0)
SCL0
SDA0
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH1)
CS1
SI1
SO1
SCK1
BUFFER
RAM
3
2
2
2
NMI
12
AVREF0
SERIAL
INTERFACE
UNIT (CH0)
12
RAM
10K BYTES
CLOCK GENERATOR/
SYSTEM CONTROLLER
FIFO
TOKEI PRESCALER
PRESCALER/
TIME-BASE TIMER
BOOT ROM
FLASH
ROM
256K BYTES
SPC950
CPU CORE
5
XOUT
CS0
SI0
SO0
SCK0
16
SIMPLE UART
RxD
INTERRUPT CONTROLLER
8
FLASH CONTROLLER
INT0
to INT7
KS0
to KS15
A/D
CONVERTER
(CH0)
AN0
to AN11
REALTIME PULSE
GENERATOR
RTO0
to RTO4
A/D
CONVERTER
(CH1)
AVSS
AVREF1
AVDD
AN12
to AN23
TEX
TX
EXTAL
XTAL
RST
VDD
VSS
TxD
PB0 to PB7
PC0 to PC7
PD0 to PD7
8
8
8
8
PF4 to PF7
PG0 to PG7
PH0 to PH5
PH6, PH7
PI0 to PI7
4
8
6
2
8
8
PJ0 to PJ7
PF0 to PF3
4
PE0 to PE7
PA0 to PA7
8
PORT B
PORT C
PORT G
PORT H
–2–
TETA
TETB
TETC
PWE
PORT A
PORT D
PORT E
PORT F
PORT I
PORT J
Block Diagram
CXP921F064A
CXP921F064A
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
PWE
VDD
VSS
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
Pin Assignment 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB2/AN22
1
80
PJ0/AN4/KS8
PB3/AN23
2
79
AVDD
PB4/SI3
3
78
AVREF1
PB5/SO3
4
77
AVREF0
PB6/SCK3
5
76
AVss
PB7/RMC
6
75
AN3
PC0/SDA0
7
74
AN2
PC1/SCL0
8
73
AN1
PC2/SDA1
9
72
PI7/AN0
PC3/SCL1
10
71
PI6/NMI
PC4
11
70
PI5/INT7
PC5
12
69
PI4/INT6
PC6
13
68
PI3/INT5
PC7
14
67
PI2/INT4
VSS
15
66
PI1/INT3
PD0/KS0
16
65
PI0/INT2
PD1/KS1
17
64
PH7/INT1/TETC
PD2/KS2
18
63
PH6/INT0
PD3/KS3
19
62
PH5/XOUT
PD4/KS4
20
61
PH4/RTO4
PD5/KS5
21
60
PH3/RTO3
PD6/KS6
22
59
PH2/RTO2
PD7/KS7
23
58
PH1/RTO1
PE0/TxD
24
57
PH0/RTO0
PE1/RxD
25
56
Vss
PE2
26
55
TX
PE3
27
54
TEX
PE4
28
53
VDD
PE5
29
52
PG7/SCK2
PE6
30
51
PG6/SO2
PG5/SI2
PG4/CS2
PG3/SCK1
PG2/SO1
PG1/SI1
PG0/CS1
VDD
XTAL
EXTAL
VSS
RST
PF7/TMO/TETA
PF5/SCK0
PF6/TO/TETB
PF4/SO0
PF3/SI0
PF2/CS0
PF1/EC
PF0
PE7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. Vss (Pins 15, 41, 56 and 90) must be connected to GND.
2. VDD (Pins 44, 53 and 89) must be connected to VDD.
–3–
CXP921F064A
AVREF1
AVDD
PJ0/AN4/KS8
PJ1/AN5/KS9
PJ2/AN6/KS10
PJ3/AN7/KS11
PJ4/AN8/KS12
PJ5/AN9/KS13
PJ6/AN10/KS14
PJ7/AN11/KS15
PWE
VDD
VSS
PA0/AN12
PA1/AN13
PA2/AN14
PA3/AN15
PA4/AN16
PA5/AN17
PA6/AN18
PA7/AN19
PB0/AN20
PB1/AN21
PB2/AN22
PB3/AN23
Pin Assignment 2 (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB4/SI3
1
75
AVREF0
PB5/SO3
2
74
AVss
PB6/SCK3
3
73
AN3
PB7/RMC
4
72
AN2
PC0/SDA0
5
71
AN1
PC1/SCL0
6
70
PI7/AN0
PC2/SDA1
7
69
PI6/NMI
PC3/SCL1
8
68
PI5/INT7
PC4
9
67
PI4/INT6
PC5
10
66
PI3/INT5
PC6
11
65
PI2/INT4
PC7
12
64
PI1/INT3
VSS
13
63
PI0/INT2
PD0/KS0
14
62
PH7/INT1/TETC
PD1/KS1
15
61
PH6/INT0
PD2/KS2
16
60
PH5/XOUT
PD3/KS3
17
59
PH4/RTO4
PD4/KS4
18
58
PH3/RTO3
PD5/KS5
19
57
PH2/RTO2
PD6/KS6
20
56
PH1/RTO1
PD7/KS7
21
55
PH0/RTO0
PE0/TxD
22
54
Vss
PE1/RxD
23
53
TX
PE2
24
52
TEX
PE3
25
51
VDD
Note) 1. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
2. VDD (Pins 42, 51 and 87) must be connected to VDD.
–4–
PG6/SO2
PG7/SCK2
PG5/SI2
PG4/CS2
PG3/SCK1
PG2/SO1
PG1/SI1
PG0/CS1
VDD
EXTAL
XTAL
VSS
RST
PF7/TMO/TETB
PF6/TO/TETA
PF5/SCK0
PF4/SO0
PF3/SI0
PF2/CS0
PF1/EC
PF0
PE7
PE6
PE5
PE4
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP921F064A
Pin Assignment 3 (Top View) 104-pin LFLGA package
1
2
3
4
5
6
7
8
9
10
11
A
98
PB1
96
PA7
93
PA4
90
PA1
88
VSS
86
NC
83
PJ5
80
PJ2
78
PJ0
A
B
99
PB2
97
PB0
94
PA5
91
PA2
87
VDD
85
PJ7
82
PJ4
79
PJ1
77
AVDD
B
100
PB3
95
PA6
92
PA3
89
PA0
84
PJ6
81
76
PJ3 AVREF1
C
3
PB6
2
PB5
D
5
PC0
4
PB7
1
PB4
8
PC3
F 11
PC6
G 13
VSS
H 15
PD1
J 18
PD4
K 21
PD7
L 23
PE1
M
7
PC2
10
PC5
6
PC1
9
PC4
70
PI7
67
PI4
12
PC7
14
PD0
16
PD2
19
PD5
22
PE0
E
1
2
13
74
AVSS
73
AN3
C
75
72
AVREF0 AN2
71
AN1
D
69
PI6
66
PI3
68
PI5
65
PI2
E
64
PI1
62
PH7
63
PI0
G
17
PD3
59
PH4
60
PH5
61
PH6
H
20
PD6
25
PE3
56
PH1
51
VDD
57
PH2
54
VSS
58
PH3
55
PH0
J
52
TEX
53
TX
F
K
L
26
PE4
31
PF1
34
PF4
39
VSS
45
PG2
50
PG7
27
PE5
29
PE7
32
PF2
35
PF5
37
41
44
PF7 EXTAL PG1
47
PG4
49
PG6
M
28
PE6
3
30
PF0
4
33
PF3
5
36
PF6
6
38
40
43
RST XTAL PG0
7
8
9
46
PG3
10
48
PG5
11
N
24
PE2
N
12
42
VDD
12
13
Note) 1. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
2. VDD (Pins 42, 51 and 87) must be connected to VDD.
3. Pin Nos. 1 to 100 are the same Pin Nos. of LQFP. For details, see page 4.
–5–
CXP921F064A
Pin Functions
Symbol
I/O
PA0/AN12
to PA7/AN19
Output / Input
PB0/AN20
to PB3/AN23
Output / Input
PB4/SI3
Output / Input
Functions
(Port A)
8-bit output port.
(8 pins)
Analog input for A/D converter.
(12 pins)
Serial data (CH3) input.
PB6/SCK3
(Port B)
8-bit output port.
Output / Output
(8 pins)
Output / I/O
PB7/RMC
Output / Input
Remote control receive circuit input.
PC0/SDA0
I/O / I/O
PC1/SCL0
I/O / I/O
PC2/SDA1
I/O / I/O
PC3/SCL1
I/O / I/O
PC4 to PC7
I/O
PB5/SO3
PD0/KS0
to PD7/KS7
I/O / Input
PE0/TxD
I/O / Output
PE1/RxD
I/O / Input
PE2 to PE7
I/O
PF0
Input
PF1/EC
Input / Input
PF2/CS0
Input / Input
PF3/SI0
PF4/SO0
PF5/SCK0
Serial data (CH3) output.
Serial clock (CH3) I/O.
Data I/O of I2C bus interface (CH0).
(Port C)
Clock I/O of I2C bus interface (CH0).
8-bit I/O port.
I/O can be specified in 1-bit units.
Data I/O of I2C bus interface (CH1).
Pull-up resistor is present or not
Clock I/O of I2C bus interface (CH1).
through program in 1-bit units.
(8 pins)
(Port D)
8-bit I/O port.
I/O can be specified in 1-bit units.
Can drive 5mA sink current
(VDD = 2.7 to 3.3V).
(8 pins)
(Port E)
Serial (asynchronous communication)
8-bit I/O port.
during flash on-board write.
I/O can be specified in 1-bit units.
(8 pins)
External event input for 8-bit
timer/counter.
(Port F)
8-bit port.
Input / Input
Lower 4 bits are for input;
Output / Output upper 4 bits are for output.
(8 pins)
Output / I/O
PF6/TO/TETB Output / Output
PF7/TMO/TETA Output / Output
Standby release input function can be
specified in 1-bit units.
(8 pins)
Flash mode
setting pins
–6–
Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
8-bit timer/counter output.
16-bit timer (CH0) output.
CXP921F064A
Symbol
I/O
Functions
PG0/CS1
I/O / Input
Serial chip select (CH1) input.
PG1/SI1
I/O / Input
Serial data (CH1) input.
PG2/SO1
I/O / Output
PG3/SCK1
I/O / I/O
PG4/CS2
I/O / Input
PG5/SI2
I/O / Input
PG6/SO2
I/O / Output
Serial data (CH2) output.
PG7/SCK2
I/O / Output
Serial clock (CH2) output.
PH0/RTO0
to PH4/RTO4
PH5/XOUT
PH6/INT0
PH7/INT1/
TETC
Serial data (CH1) output.
(Port G)
Serial clock (CH1) I/O.
8-bit I/O port.
I/O can be specified in 1-bit units. Serial chip select (CH2) input.
(8 pins)
Serial data (CH2) input.
Output / Output (Port H)
8-bit port.
Output / Output Lower 6 bits are for output;
upper 2 bits are for input.
Input / Input
(8 pins)
Flash mode
Input / Input /
setting pins
Input
Real-time pulse generator output.
(5 pins)
Clock output for clock prescaler buzzer.
External interrupt input.
(8 pins)
PI0/INT2
to PI5/INT7
Input / Input
PI6/NMI
Input / Input
PI7/AN0
Input / Input
AN1 to AN3
Input
Analog input for A/D converter.
(12 pins)
PJ0/AN4/
KS8
to PJ7/AN11/
KS15
I/O / Input /
Input
(Port J)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
EXTAL
Input
Connects a crystal for main clock oscillation.
(When the clock is supplied externally, input it to EXTAL and input an
opposite phase clock to XTAL.)
Input
Connects a crystal for sub clock oscillation.
(When the clock is supplied externally, input it to TEX and input an
opposite phase clock to TX.)
Input
System reset. Active at "L" level.
XTAL
TEX
TX
RST
(Port I)
8-bit input port.
(8 pins)
Non-maskable external interrupt input.
Standby release input
function can be specified in
1-bit units.
(8 pins)
Positive power supply for A/D converter.
AVDD
AVREF0
Input
Reference voltage input for A/D converter (CH0).
AVREF1
Input
Reference voltage input for A/D converter (CH1).
AVSS
GND for A/D converter.
VDD
Positive power supply.
(Connect all three VDD pins to positive power supply.)
VSS
GND
(Connect all four Vss pins to GND.)
PWE
Input
Permits erasure and write of incorporated Flash EEPROM.
–7–
CXP921F064A
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
PA register
"0" after a reset
PA0/AN12
to PA7/AN19
PASL register
Input protection
circuit
IP
Hi-Z
"0" after a reset
Internal data bus
A/D converter
RD
Input multiplexer
PB register
"0" after a reset
PB0/AN20
to PB3/AN23
PBSL register
IP
Hi-Z
IP
Hi-Z
"0" after a reset
Internal data bus
A/D converter
RD
Input multiplexer
PB register
"0" after a reset
PB4/SI3
PB7/RMC
PBSL register
"0" after a reset
Internal data bus
RD
SI3, RMC
CMOS Schmitt input
–8–
CXP921F064A
Pin
Circuit format
SO3
0
MPX
1
PB register
PB5/SO3
After a reset
"0" after a reset
Hi-Z
Internal data bus
RD
PBSL register
"0" after a reset
SO3 output enable
0
SCK3
MPX
1
PB register
"0" after a reset
Internal data bus
PB6/SCK3
Hi-Z
RD
PBSL register
IP
"0" after a reset
SCK3 output enable
SCK3
CMOS Schmitt input
PULC register
"0" after a reset
SDA0, SCL0, SDA1, SCL1
PC register
∗
1
MPX
0
Undefined after a reset
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PCSL register
Hi-Z
"0" after a reset
IP
PCD register
"0" after a reset
Internal data bus
RD
SDA0, SCL0
SDA1, SCL1
CMOS Schmitt input
∗ Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
–9–
CXP921F064A
Pin
Circuit format
After a reset
PULC register
∗
"0" after a reset
PC register
Undefined after a reset
PC4 to PC7
Hi-Z
PCD register
IP
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
PD register
Undefined after a reset
∗
PDD register
PD0/KS0
to PD7/KS7
IP
Hi-Z
"0" after a reset
Internal data bus
RD
Standby release
TxD
PE register
∗ Large current drive
5mA (VDD = 2.7 to 3.3V)
1
MPX
0
Undefined after a reset
PE0/TxD
PED register
IP
"0" after a reset
TxD output enable
Internal data bus
RD
– 10 –
Hi-Z
CXP921F064A
Pin
Circuit format
After a reset
PE register
Undefined after a reset
PED register
PE1/RxD
IP
Hi-Z
"0" after a reset
Internal data bus
RD
RxD
PE register
Undefined after a reset
PE2 to PE7
PED register
IP
Hi-Z
"0" after a reset
Internal data bus
RD
PF0
IP
Internal data bus
Hi-Z
RD
Internal data bus
PF1/EC
IP
RD
EC
Hi-Z
CMOS Schmitt input
IP
Internal data bus
PF2/CS0
PF3/SI0
RD
PFSL register
CMOS Schmitt input
"0" after a reset
CS0, SI0
– 11 –
Hi-Z
CXP921F064A
Pin
Circuit format
SO0
PF register
Internal
data bus
After a reset
1
MPX
0
"0" after a reset
RD
PF4/SO0
Hi-Z
PFSL register
"0" after a reset
SO0 output enable
PF register write
S
Reset
R
SCK0
PF register
Internal
data bus
Q
1
MPX
0
"0" after a reset
RD
PF5/SCK0
Hi-Z
PFSL register
"0" after a reset
IP
SCK0 output enable
PF register write
S
Reset
R
Q
SCK0
CMOS Schmitt input
PF6/TO/
TETB
PF7/TMO/
TETA
PF register write
S
Reset
R
TO, TMO
PF register
Internal
data bus
∗
Q
"H" level
("H" level at ON
resistance of
pull-up transistor
during a reset.)
1
MPX
0
"0" after a reset
RD
PFSL register
"0" after a reset
TETA,
TETB
∗ Pull-up transistor
approximately 150kΩ (VDD = 2.7 to 3.3V)
– 12 –
CXP921F064A
Pin
Circuit format
After a reset
PG register
Undefined after a reset
PGD register
PG0/CS1
PG1/SI1
PG4/CS2
PG5/SI2
IP
"0" after a reset
Hi-Z
Internal
data bus
RD
CMOS Schmitt input
PGSL register
"0" after a reset
CS1, SI1
CS2, SI2
SO1, SCK1
SO2, SCK2
PG register
1
MPX
0
Undefined after a reset
PGSL register
PG2/SO1
PG3/SCK1
PG6/SO2
PG7/SCK2
"0" after a reset
Hi-Z
PGD register
IP
"0" after a reset
SO1, SCK1
output enable
SO2, SCK2
Internal
data bus
RD
SCK1
CMOS Schmitt input
(PG3 only)
RTO0 to RTO4
PH register
PH0/RTO0
to PH4/RTO4
Hi-Z
Undefined after a reset
Internal
data bus
RD
PH register write
S
Reset
R
Q
– 13 –
CXP921F064A
Pin
Circuit format
XOUT
PH register
After a reset
1
MPX
0
Undefined after a reset
Internal
data bus
PH5/XOUT
Hi-Z
RD
PHSL register
"0" after a reset
PH register write
S
Reset
R
Q
Internal data bus
PH6/INT0
to PH7/INT1/
TETC
IP
RD
CMOS Schmitt input
Interrupt circuit
Hi-Z
TETC
PI0/INT2
to PI5/INT7
Internal data bus
IP
Hi-Z
RD
CMOS Schmitt input
Interrupt circuit
PISL register
"0" after a reset
PI6/NMI
Interrupt circuit (NMI)
IP
Hi-Z
CMOS Schmitt input
Internal data bus
RD
PISL register
"0" after a reset
PI7/AN0
Internal data bus
IP
Hi-Z
RD
A/D converter
Input multiplexer
AN1 to AN3
A/D converter
IP
Input multiplexer
– 14 –
Hi-Z
CXP921F064A
Pin
Circuit format
After a reset
PJ register
Undefined after a reset
PJD register
"0" after a reset
PJ0/AN4/
KS8
to PJ7/AN11/
KS15
Hi-Z
Internal data bus
RD
Standby release
IP
PJSL register
"0" after a reset
A/D converter
Input multiplexer
IP
EXTAL
Timing generator
• Diagram shows circuit
configuration during
oscillation.
• Feedback resistor is
removed during stop
mode, and XTAL is
driven at "H" level.
EXTAL
XTAL
Oscillation stop control
Oscillation
XTAL
Oscillation stop control
TEX
Timing generator,
clock prescaler
IP
TEX
TX
Oscillation
• TX is driven at Hi-Z
during stop mode.
TX
IP
– 15 –
CXP921F064A
Pin
Circuit format
Mask option
After a reset
∗
OP
RST
Internal
reset circuit
IP
"L" level
(during a reset)
CMOS Schmitt input
∗ Pull-up transistor
approximately 30kΩ (VDD = 2.7 to 3.3V)
∗
PWE
IP
Flash EEPROM circuit
∗ Input protection only to negative voltage
– 16 –
Hi-Z
CXP921F064A
(VSS = 0V reference)
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
V
AVDD
–0.3 to +4.6
AVSS to +4.6∗1
AVREF
AVSS to +4.6∗1
VDD
Supply voltage
Remarks
V
V
VIN
–0.3 to +0.3
–0.3 to +4.6∗2
Output voltage
VOUT
–0.3 to +4.6∗2
V
High level output current
IOH
–5
mA
Output (value per pin)
High level total output current
∑IOH
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
∑IOL
130
mA
Operating temperature
Topr
–20 to +75∗4
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
QFP-100P-L01
380
mW
LQFP-100P-L01
500
mW
LFLGA-104P-02
AVSS
Input voltage
V
V
Low level output current
Low level total output current
Allowable power dissipation
PD
All pins excluding large current output
pins (value per pin)
Large current output pins∗3
(value per pin)
Total for all output pins
∗1 AVDD and AVREF must be the same voltage with VDD.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
∗3 The large current drive transistor is N-ch transistor of PD.
∗4 Operating temperature range during write/erasure of flash memory is Ta = 0 to 50°C.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 17 –
CXP921F064A
(Vss = 0V reference)
Recommended Operating Conditions
Item
Symbol
Min.
Max.
Unit
2.7
3.3
V
2.2
3.3
V
Guaranteed operation range with TEX clock
2.2
3.3
V
Guaranteed operation range for clock mode
2.0
3.3
V
AVDD
2.7
3.3
V
Guaranteed data hold range during stop mode
∗1
AVREF
2.7
3.3
V
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
CMOS Schmitt input∗3
VIHEX
0.7VDD VDD + 0.3
VDD
Supply voltage
High level input
voltage
Low level input
voltage
Operating temperature
V
Remarks
VIL
0
0.2VDD
V
EXTAL, TEX
∗2
VILS
0
0.2VDD
V
CMOS Schmitt input∗3
VILEX
–0.3
0.3VDD
V
EXTAL, TEX
Topr
–20
+75
°C
∗1 AVDD and AVREF must be the same voltage with VDD.
∗2 PC4 to PC7, PD, PE, PF0, PG2, PG6, PI7, PJ for normal input port.
∗3 PB4, PB6, PB7, PC0 to PC3, PF1 to PF3, PF5, PG0, PG1, PG3 to PG5, PH6, PH7, PI0 to PI6, RST.
– 18 –
CXP921F064A
Electrical Characteristics
DC Characteristics
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
(Topr = –20 to +75°C, Vss = 0V reference)
Pins
IILE
Typ.
Max.
Unit
VDD = 2.7V, IOH = –0.15mA
2.4
V
VDD = 2.7V, IOH = –0.5mA
2.0
V
PC
VDD = 2.7V, IOH = –0.05mA
1.3
V
VDD = 2.7V, IOL = 1.2mA
0.3
V
VDD = 2.7V, IOL = 1.6mA
0.5
V
PC0 to PC3
(SCL0, SCL1,
SDA0, SDA1)
VDD = 2.7V, IOL = 2.0mA
0.3
V
VDD = 2.7V, IOL = 3.0mA
0.5
V
PD
VDD = 2.7V, IOL = 5.0mA
1.0
V
IIHE
Input
current
Min.
PA, PB, PD, PE,
PF4 to PF7, PG,
PH0 to PH5, PJ
PA, PB ,
PC4 to PC7, PE ,
PF4 to PF7, PG,
PH0 to PH5, PJ
VOL
Conditions
EXTAL
IILR
RST∗1
IIL
PC∗2
VDD = 3.3V, VIH = 3.3V
0.3
20
µA
VDD = 3.3V, VIL = 0.3V
–0.3
–20
µA
–0.9
–250
µA
–250
µA
VDD = 3.3V, VIL = 0.3V
VDD = 2.7V, VIH = 2.4V
–1.0
µA
I/O leakage
IIZ
current
PA, PB,
PD to PG,
PH6, PH7,
PI, PJ,
AN1 to AN3,
TEX
VDD = 3.3V, VI = 0, 3.3V
±10
µA
Open drain
output
leakage
ILOH
current (N-ch
Tr. off state)
PC∗2
VDD = 3.3V, VIH = 3.3V
10
µA
IDD1∗4
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
(C1 = C2 = 10pF)
20
26
mA
IDD2
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF)
70
150
µA
IDDS1
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
(C1 = C2 = 10pF), sleep mode
7
12
mA
IDDS2
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF),
sleep mode
12
70
µA
IDDS3
VDD = 3.0V, 32kHz crystal
oscillation, 20MHz oscillation stop
(C1 = C2 = 47pF), clock mode
7
50
µA
IDDS4
VDD = 3.0V, stop mode
40
µA
Supply
current∗3
VDD, VSS
– 19 –
CXP921F064A
Item
Symbol
Input
CIN
capacitance
Pins
Conditions
PA, PB0 to PB4,
PB6, PB7,
PC to PE,
PF0 to PF3,
PF5, PG, PH6,
PH7, PI, PJ,
AN1 to AN3,
EXTAL, TEX,
RST
Clock 1MHz
0V for all pins excluding measured
pins
Min.
Typ.
Max.
Unit
10
20
pF
∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗2 PC specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗3 When all output pins are open.
∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and
the LSI is operated in high-speed mode (2 frequency dividing clock).
– 20 –
CXP921F064A
AC Characteristics
(1) Clock timing
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol
Main clock base oscillation
frequency
Main clock base oscillation
input pulse width
Main clock base oscillation
input rise time, fall time
Sub clock base oscillation
frequency
Sub clock base oscillation
input pulse width
Sub clock base oscillation
input rise time, fall time
fEX
tXH
tXL
tXR
tXF
fTEX
tTH
tTL
tTR
tTF
Pins
Conditions
EXTAL,
XTAL
EXTAL
EXTAL
TEX,
TX
TEX
TEX
Fig.1
Fig.1, Fig.2
External clock
drive
Fig.1, Fig.2
External clock
drive
Min.
Typ.
Max.
Unit
VDD = 3.0 ± 0.3V
15
20
20.5
MHz
VDD = 3.0 ± 0.3V
20
VDD = 3.0 ± 0.3V
ns
14
ns
Fig.1
VDD = 2.2 to 3.3V 32.735 32.768 33.096 kHz
Fig.1, Fig.2
External clock
drive
Fig.1, Fig.2
External clock
drive
VDD = 3.3V
15.3
µs
VDD = 2.2V
15.3
µs
VDD = 3.3V
200
ns
VDD = 2.2V
200
ns
Note) tsys indicates the four values below according to the upper two bits (PCK1, PCK0) of the clock control
register (CLC: 0002FEh) during main mode and tsys = 2/fTEX = 61.04µs during sub mode.
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10),
16/fEX (PCK1, PCK0 = 11)
1/fEX
0.7VDD
EXTAL
0.3VDD
tXH
tXF
tXL
tXR
1/fTEX
0.7VDD
TEX
0.3VDD
tTH
tTF
tTL
tTR
Fig.1. Clock timing
Oscillator connection
example of
main oscillation circuit
EXTAL
XTAL
Oscillator connection
example of
sub oscillation circuit
TEX
TX
Connection example of
external clock
(TEX)
EXTAL
(TX)
XTAL
74HC04
Fig.2. Oscillator connection and clock applied conditions
– 21 –
CXP921F064A
(2) Event count input
Item
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Symbol
tEH,
tEL
Event count input clock
pulse width
Pins
Conditions
EC
Min.
Max.
tsys + 100
Fig.3
Unit
ns
0.8VDD
EC
0.2VDD
tEH
tEL
Fig.3. Event count input timing
(3) Interruption and reset input
Item
External interruption
high, low level width
Symbol
tIH,
tIL
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Pins
Conditions
Min.
Main mode
Sub mode
NMI
INT0 to INT7 Sleep mode
KS0 to KS15 Clock mode
Stop mode
Noise filter
INT4 to INT7
selected
Reset input low level
width
tRST RST
ns
1
µs
2tsys + 100
PS4
32/fEX + 100
PS6
128/fEX + 100
50/fEX
tIH
tIL
0.8VDD
NMI
INT0 to INT7
KS0 to KS15
0.2VDD
Fig.4. Interruption input timing
tRST
RST
0.2VDD
Fig.5. Reset input timing
– 22 –
Unit
tsys + 100
φ
Fig.5
Max.
ns
ns
CXP921F064A
(4) A/D converter characteristics
(Topr = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 3.3V, Vss = AVss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Resolution
Linearity error
VDD = AVDD = AVREF = 3.0V
Absolute error
Conversion time
Sampling time
tCONV
tSAMP
Reference input
voltage
VREF
AVREF
Analog input
voltage
VIAN
AN0 to AN23
IREF
AVREF current
IREFS
AVREF0
AVREF1
Max.
Unit
8
Bits
±1
LSB
±3
LSB
34tsys
µs
9tsys
µs
VDD = AVDD = AVREF
Main mode
Sub mode
2.7
3.3
V
0
AVREF
V
1.5
mA
10
µA
1.1
Clock mode
Stop mode
during ADC off state∗
∗ When Bit 14 (ADOFF) of A/D control status register (ADCS0: 00013Ch, ADCS1: 00014Ch) is specified to "1".
Note) AVDD and AVREF must be the same voltage with VDD.
(100h)
FFh
FEh
Digital conversion value
Digital conversion value
FFh
FEh
Linearity error
01h
00h
VZT∗1
Analog input
Absolute error
01h
00h
VFT∗2
Absolute error
Analog input
∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa
Fig.6. Definition of A/D converter terms
– 23 –
AVREF
CXP921F064A
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
(5) Serial transfer (CH0, CH1, CH2)
Item
Symbol
Pins
Conditions
Min.
SCK0
External start transfer mode
SCK1
(SCK = output mode)
SCK2
CS ↓ → SCK
delay time
tDCSK
CS ↑ → SCK
float delay time
tDCSKF SCK1 External start transfer mode
CS ↓ → SO
delay time
tDCSO
CS ↑ → SO
float delay time
tDCSOF CS1
CS high level width
tWHCS
CS0
CS1
CS2
SCK cycle time
tKCY
Max.
Unit
1.5tsys + 200
ns
1.5tsys + 200
ns
SCK0
SCK2
(SCK = output mode)
SO0
SO1
SO2
External start transfer mode
1.5tsys + 200
ns
External start transfer mode
1.5tsys + 200
ns
CS0
CS2
tsys + 100
ns
SCK0 Input mode
SCK1
SCK2 Output mode
2tsys + 200
ns
16/fEX
ns
tsys + 100
ns
8/fEX – 100
ns
100
ns
External start transfer mode
SCK
high, low pulse width
tKH
tKL
SCK0 Input mode
SCK1
SCK2 Output mode
SI input data setup time
(for SCK ↑)
tSIK
SI0
SI1
SI2
SCK input mode
SCK output mode
200 – tsys
ns
SI input data hold time
(for SCK ↑)
tKSI
SI0
SI1
SI2
SCK input mode
tsys + 100
ns
SCK output mode
tsys + 100
ns
SCK ↓ → SO
delay time
tKSO
SO0
SO1
SO2
SCK input mode
Minimum interval time
tINT
SCK output mode
SCK0 SCK input mode
SCK1
SCK2 SCK output mode
ns
100
ns
3tsys + 100
ns
8/fEX – 100
ns
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
– 24 –
tsys + 150
CXP921F064A
tWHCS
0.8VDD
CS0
CS1
CS2
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
SCK0
SCK1
SCK2
0.2VDD
tSIK
tKSI
0.8VDD
SI0
SI1
SI2
Input data
0.2VDD
tDCSO
tDCSOF
tKSO
0.8VDD
SO0
SO1
SO2
Output data
0.2VDD
tINT
0.8VDD
SCK0
SCK1
SCK2
Fig.7. Serial transfer CH0, CH1, CH2 timing
– 25 –
CXP921F064A
(6) Serial transfer (CH3) [SIO mode]
Item
SCK cycle time
Symbol
SI input data setup
time (for SCK ↑)
tSIK
SI3
SI input data hold
time (for SCK ↑)
tKSI
SCK ↓ → SO delay
time
tKSO
Min.
16/fEX
ns
Input mode
tsys + 100
ns
Output mode
8/fEX – 100
ns
SCK input mode
100
ns
SCK output mode
200
ns
tsys + 100
ns
200
ns
Output mode
SCK input mode
SCK input mode
SCK output mode
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
tKCY
tKL
tKH
SCK3
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI3
Unit
ns
SCK output mode
SO3
Max.
2tsys + 200
Input mode
SCK3
tKH
tKL
Conditions
Pins
tKCY
SCK high, low pulse
width
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
0.2VDD
tKSO
0.8VDD
Output data
SO3
0.2VDD
Fig.8. Serial transfer CH3 timing (SIO mode)
– 26 –
tsys + 150
ns
100
ns
CXP921F064A
(7) Serial transfer (CH3) [Special mode]
Item
Symbol
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Conditions
Pins
SO cycle time∗
tLCY
SO3
SI3
SI input setup time
tLSU
SI3
SI input hold time
tLHD
SI3
Input start bit high level
width
tLSBH
SI3
SI → SO
delay time
tLIO
Min.
Typ. Max. Unit
104
fEX = 20MHZ
2
1
Communication slave mode
SO3
1
∗ When lower 2 bits (SCK1, SCK0) of serial mode register (SIOM3: 0001A4h) is specified to "00".
Note) The load condition for the SO output delay time is 100pF.
SO3
tLCY
tLCY
Start bit
Output data bit
0.5VDD
tLCY/2
tLSU
tLHD
0.8VDD
Input data
bit
SI3
0.2VDD
Fig.9. Serial transfer CH3 timing (Special mode)
tLSBH
0.8VDD
Input data bit
SI3
0.2VDD
tLHD
tLSU
tLCY/2
tLCY
tLIO
tLCY
SO3
µs
2
0.5VDD
tLSU
tLHD
tLCY
Output data bit
Fig.10. Serial transfer CH3 timing (Special mode)
– 27 –
CXP921F064A
(8) I2C bus (CH0, CH1)
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol
Pins
Standard mode
High-speed mode
Min.
Max.
Min.
Max.
100
0
400
Unit
SCK clock frequency
tSCL
SCL0
SCL1
0
Bus free time between
stop and start conditions
tBUF
SDA0
SDA1
4.7
1.3
µs
Hold time under (resend)
start condition
tHD;STA
SDA0, SDA1
SCL0, SCL1
4.0
0.6
µs
Hold time in SCL clock
low state
tLow
SCL0
SCL1
4.7
1.3
µs
Hold time in SCL clock
high state
tHigh
SCL0
SCL1
4.0
0.6
µs
Setup time under (resend)
start condition
tSU;STA
SDA0, SDA1
SCL0, SCL1
4.7
0.6
µs
Data hold time
tHD;DAT
SDA0, SDA1
SCL0, SCL1
0
0
Data setup time
tSU;DAT
SDA0, SDA1
SCL0, SCL1
250
100
SCL, SDA signal output
rise time
tRd
tRc
tFd
tFc
SDA0, SDA1
SCL0, SCL1
1000
20 + α∗
300
ns
SDA0, SDA1
SCL0, SCL1
300
20 + α∗
300
ns
tSU;STO
SDA0, SDA1
SCL0, SCL1
SCL, SDA signal output
fall time
Setup time under stop
condition
4.0
0.9
kHz
µs
ns
µs
0.6
∗ Due to the total capacitance of the bus.
tSU;DAT
tBUF
SDA0
SDA1
tHD;STA
tRd
tFd
tSCL
tRc
tFc
tLow
SCL0
SCL1
tHD;STA
tHD;DAT
tHigh
Fig.11. I2C bus timing
– 28 –
tSU;STA
tSU;STO
CXP921F064A
(9) Remote control reception
Item
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Symbol
Pins
Conditions
Min.
Max.
Unit
PS5 selected 128/fEX + 100
PS7 selected
Remote control receive
high, low level width
tRMC
RMC
Main mode
512/fEX + 100
PS9 selected 2048/fEX + 100
4/fTEX + 100
32k selected
8/fTEX + 100
Sub mode
0.8VDD
RMC
0.2VDD
tRMC
tRMC
Fig.12. Remote control signal input timing
– 29 –
ns
CXP921F064A
Appendix
(i) Main oscillation circuit
EXTAL
(ii) Main oscillation circuit
XTAL
EXTAL
XTAL
Rd
C1
(iii) Sub oscillation circuit
TEX
Rd
TX
Rf
Rd
C2
C2
C1
C1 C2
Fig.13. Recommended oscillation circuit
Manufacturer
MURATA MFG
CO., LTD.
Model
fEX (MHz)
C1 (pF)
C2 (pF)
CSA12.0MTZ
12.0
30
30
0
CSA16.00MXZ040
16.0
15
15
0
CSA20.00MXZ040
CST12.0MTW∗
20.00
10
10
0
12.0
30
30
0
16.0
15
15
0
12.00
10
10
220
12.0
12
12
1.0k
16.0
12
12
470
20.0
12
12
390
CST16.00MXW0C3∗
RIVER ELETEC
HC-49/U03
CO., LTD.
KINSEKI LTD.
HC-49/U-S
CCR12.0MSC5∗
CCR16.0MSC6∗
TDK
Corporation
CCR20.0MSC6∗
Seiko
Instruments Inc.
VTC-200
SP-T
12.0
20 (±20%) 20 (±20%)
16.0
10 (±20%) 10 (±20%)
20.0
10 (±20%) 10 (±20%)
32.768kHZ
18
20
∗ Indicates types with on-chip grounding capacitor (C1, C2).
Reset pin pull-up resistor
Content
Non-existent
Existent
– 30 –
Remarks
(i)
(ii)
(i)
CL = 10pF
(i)
CL = 12pF
0
(ii)
150k
(iii)
Rf = 10MΩ
CL = 12.5pF
CCR∗∗∗: Surface mounted type ceramic oscillator.
CL
: Load capacitor
Mask option table
Item
Rd (Ω) Circuit example
CXP921F064A
Notes on Using the PF7 Pin
The PF7 pin of the Flash EEPROM incorporated version provides a flash mode setting function. Note the
following points when using this pin.
1. Although the PF7 pin output is made at high level during a reset, the pin is driven at a relatively high
impedance of about 150kΩ. Note that VOH does not fall below 0.7VDD due to partial pressure with the load
impedance of the external circuit.
2. When the software reset function is used, the PF7 pin may not rise enough during a reset. Switching the
PF7 pin to high output or connecting pull-up resistor is recommended before software reset is executed.
RST
Normal operation
PF7
Flash mode
Be sure to set the PF7 pin to 0.7VDD
or more during this interval.
Fig.14. Status of the PF7 pin during a reset
Description of Flash Memory Performance
Item
Performance
Operational mode
Off-board parallel, on-board serial
Programming method
Page units (512-bit units)
Erase method
All erase
10 years∗1
Data hold
∗1 when data is used and stored under recommended operating conditions.
(Ta = 0 to +50°C, VDD = 2.7 to 3.3V, VSS = 0V reference)
Item
Typ.
Max.
Unit
8
12
ms/512 bits
Erase time
50
ms
Program/erase count
100
Count
Write time∗2
Min.
∗2 When write clock fFCK = 10MHz is used in off-board parallel mode.
– 31 –
CXP921F064A
On-board Write
By performing steps 1) through 3) below on the user's hardware, the microcontroller can be reset/started and
the Flash EEPROM overwritten,
1) Fix the mode control pin using external hardware
PF7/TETA pin → Fix to “L” level
PF6/TETB pin → Fix to “H” level or leave open
PH7/TETC pin → Fix to “H” level
PWE pin
→ Fix to “H” level
2) Connect the microcontroller and SFP-2 using the specified connection method.
3) Overwrite the Flash EEPROM from the SFP-2.
SFP-2 asynchronous communications connector (ASYNC: Pin 7)
SFP-2
User hardware
VIN
5
VDD
PWE
VDD
RxD
2
TxD
TxD
3
RxD
TxD/PE0
CXP921F064A
RxD/PE1
TETC
ON only while
Flash EEPROM overwrite
TETB
TETA
RES
4
RES
GND
1, 6
VSS
VPP
7
RST
VSS
Reset
circuit
(Not used)
Fig.15. Example of Connection between the SFP-2 and User Hardware
1. The PWE pin provides a function for writing/erasing the Flash EEPROM. Fix this pin to “H” level to overwrite
or erase the Flash EEPROM. Fix this pin to “L” level to forcibly prohibit overwriting.
2. Since an AMP-CT receptal 173977-7 is used as the connector for the flash programmer (SFP-2), an AMPCT connector 175489-7 is recommended for the user hardware.
∗ The SFP-2 is manufactured and sold by MITEC SYSTEMS, INC.
– 32 –
CXP921F064A
Off-board Write
The SFP-2 is used to write data. The setting is as follows.
Device type
ROM area
SPC970FLSH#0 ADAPTER
START : FC0000
END : FFFFFF
For details on how to write data using the SFP-2, refer to the SFP-2 User's Manual.
– 33 –
CXP921F064A
Characteristics Curve
IDD vs. VDD
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
(fEX = 20MHz, Topr = 25°C, Typical)
20
20
18
18
2 frequency dividing mode
16
IDD – Supply current [mA]
IDD – Supply current [mA]
16
14
12
4 frequency dividing mode
10
8
8 frequency dividing mode
6
16 frequency dividing mode
14
12
10
8
Sleep mode (2 frequency division)
6
4
4
2
2
Sleep mode (4 frequency division)
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
0
2.1
2.4
2.7
3
3.3
3.6
2.1
3.9
2.4
VDD – Supply voltage [V]
2.7
3
3.3
3.6
VDD – Supply voltage [V]
IDD vs. VDD
IDD vs. fEX
(fTEX = 32kHz, Topr = 25°C, Typical)
(VDD = 3V, Topr = 25°C, Typical)
3.9
20
30
2 frequency dividing mode
18
32kHz mode
(instruction execution)
16
IDD – Supply current [mA]
IDD – Supply current [µA]
25
20
15
10
32kHz
sleep mode
32kHz
clock mode
5
0
2.1
2.4
3
3.3
3.6
2.7
VDD – Supply voltage [V]
3.9
14
4 frequency dividing mode
12
10
8 frequency dividing mode
8
6
16 frequency dividing mode
4
2
0
0
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
20
18
IDD – Supply current [mA]
16
14
12
10
8
Sleep mode (2 frequency division)
6
Sleep mode (4 frequency division)
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
4
2
0
0
5
10
15
20
fEX– System clock [MHz]
25
– 34 –
5
10
15
20
fEX – System clock [MHz]
25
CXP921F064A
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
(16.3)
0.15
0° to 10°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 35 –
CXP921F064A
Unit: mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
76
50
(15.0)
B
26
100
1
0.5 ± 0.2
A
(0.22)
25
b
0.13 M
0.1 ± 0.1
+ 0.2
1.5 – 0.1
0.1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
b = 0.18 – 0.03
0.5 ± 0.2
0˚ to 10˚
(0.127)
( 0.18 )
DETAIL B
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
LQFP-100P-L01
SONY CODE
P-LQFP100-14x14-0.5
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE MASS
0.7g
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
76
50
(15.0)
B
26
100
1
0.5 ± 0.2
A
(0.22)
25
b
0.13 M
0.1 ± 0.1
+ 0.2
1.5 – 0.1
0.1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
b = 0.18 – 0.03
0˚ to 10˚
(0.127)
( 0.18 )
0.5 ± 0.2
Package Outline
DETAIL B
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
LQFP-100P-L01
SONY CODE
P-LQFP100-14x14-0.5
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE MASS
0.7g
LEAD SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
ALLOY 42
LEAD TREATMENT
Sn-Bi 2.5%
LEAD TREATMENT THICKNESS
5-18µm
– 36 –
CXP921F064A
Unit: mm
104PIN LFLGA
0.15 S A
1.4MAX
X
PIN 1 INDEX
0.10 S
12.0
0.15 S B
0.20 S
12.0
0.01
x4
0.20
S
0.8
DETAIL X
A
103 – φ0.40 ± 0.05
1.6
N
M
L
K
J
H
G
F
E
D
C
B
A
φ0.08 M S A B
0.8
B
0.4
1 2 3 4 5 6 7 8 9 10111213
0.4
1.2
1.6
1.2
Package Outline
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
EIAJ CODE
JEDEC CODE
LFLGA-104P-02
LFLGA104-P-1212
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
– 37 –
ORGANIC SUBSTRATE
GOLD PLATING
NICKEL PLATING
0.4g
Sony Corporation