MAXIM MAX1917

19-2335; Rev 1; 6/02
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Applications
DDR Memory Power
Supply
Processor or DSP Core
Supply
AGTL Bus Termination
Supply
Notebook Computers
Desktop Computers
Storage
Networking Systems
Features
♦ 25A Sourcing and Sinking Current
♦ Automatically Sets VTT to 1/2VDDR
♦ VTT and VTTR Within 1% of 1/2VDDR
♦ Smallest Output Capacitors
♦ 4.5V to 14V (or 28V with Resistor-Divider) Input
Voltage Range
♦ 1.5V to 3.6V Input DDR Range
♦ 200kHz/300kHz/400kHz/550kHz Preset Switching
Frequencies
♦ Variable Switching Frequency of Up to 1MHz
♦ Overcurrent Protection Without Current-Sense
Resistor
♦ Internal Soft-Start
♦ VTTR Reference Sources and Sinks Up to 25mA
♦ Quick-PWM Control for Fastest Loop Response
♦ Up to 96% Efficiency
♦ 16-Pin QSOP Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1917EEE
-40°C to +85°C
16 QSOP
Typical Operating Circuit
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
VIN (2.5V TO 15V)
Pin Configuration
EN/HSD
DH
POK
VL
POK
TOP VIEW
VOUT
VDDR
DDR
MAX1917
BST
EN/HSD 1
16 LX
DDR 2
15 DH
V+
LX
POK 3
14 BST
REF
DL
ILIM
PGND
(4.5V TO 14V)
VTT 4
MAX1917EEE
13 PGND
VL
ILIM 5
12 DL
FSEL 6
11 VL
FSEL
VTT
REF 7
10 V+
GND
VTTR
GND 8
9
VTTR
VTTR
QSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1917
General Description
The MAX1917 provides a complete power-management solution for DDR memory. It contains a synchronous buck controller and an amplifier to generate
1/2VDDR voltage for VTT and VTTR. The VTT and VTTR
voltages are maintained within 1% of 1/2VDDR. The
controller operates in synchronous rectification mode to
ensure balanced current sourcing and sinking capability of up to 25A. With a shutdown current of less than
5µA, the MAX1917 is the best choice for low-power
notebook applications, as well as servers and desktop
computers. An all N-FET design optimizes efficiency.
The MAX1917 can also be used for generating VDDR
and as a general-purpose step-down controller with
variable switching frequency as high as 1MHz with few
additional components.
The MAX1917 uses Maxim’s proprietary Quick-PWM™
architecture for fast transient response up to 96% efficiency, and the smallest external components. Output
current monitoring is achieved without sense resistors
by monitoring the bottom FET’s drain-to-source voltage.
The current-limit threshold is programmable through an
external resistor. The MAX1917 comes in a space-saving 16-pin QSOP package.
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +15V
EN/HSD to GND .....................................................-0.3V to +16V
VL to GND ................................................................-0.3V to +6V
PGND to GND .......................................................-0.3V to +0.3V
VTT, DDR, POK to GND ...........................................-0.3V to +6V
REF, VTTR, DL, ILIM, FSEL to GND ................-0.3V to VL + 0.3V
LX to PGND ............................................................-0.3V to +30V
BST to GND ............................................................-0.3V to +36V
DH to LX ......................................................-0.3V to VBST + 0.3V
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate up to +70°C)..............................667mW
16-Pin QSOP (derating above +70°C) .....................8.3mW/°C
Operating Temperature Range
Extended .........................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s.) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
V+ Input Voltage Range
EN/HSD Input Voltage Range
CONDITIONS
TYP
MAX
UNITS
5.5
14.0
VL = V+
4.5
5.5
Enabled
1.5
15.0
V
0
3.6
V
mA
DDR Input Voltage Range
V+ Supply Current
MIN
VTT = 2.0V
DDR Supply Current
EN/HSD Supply Current
V
0.8
1.2
115
250
µA
5
10
µA
0.8
1.2
mA
3
5
µA
1
µA
3
5
µA
4.25
4.40
V
VL Supply Current
VL = V+ = 5.5V, VTT = 2.0V
V+ Shutdown Supply Current
EN/HSD = 0V
DDR Shutdown Supply Current
EN/HSD = 0V
VL Shutdown Supply Current
VL = V+ = 5.5V
VL Undervoltage Lockout
Threshold
Rising edge, hysteresis = 40mV
4.05
VVTT = 2.5V
-0.1
0
µA
0
1.8
V
VTT
VTT Input Bias Current
VTT Feedback Voltage Range
Overload range, VDDR = 1.8V
49.5
50
50.5
Overload range, VDDR = 3.6V
49.5
50
50.5
Reference Output Voltage
V+ = VL = 4.5V to 5.5V, IREF = 0
1.98
2.00
2.02
V
Reference Load Regulation
V+ = VL = 5V, IREF = 0 to 50µA
10
mV
Reference UVLO
V+ = VL = 5V
1.7
V
1.8
V
VTT Feedback Voltage
Accuracy
%VDDR
REFERENCE
1.5
1.6
VTTR
VTTR Output Voltage Range
0
IVTTR = -5mA to +5mA
VTTR Output Accuracy
2
49.5
50
IVTTR = -25mA to +25mA, VDDR = 1.8V
49
50
51
IVTTR = -25mA to +25mA, VDDR = 3.6V
49.5
50
50.5
_______________________________________________________________________________________
50.5
%VDDR
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
Thermal Shutdown
CONDITIONS
MIN
Rising temperature, typical hysteresis = 15°C
TYP
MAX
UNITS
+160
°C
1.7
ms
SOFT-START
Ramps the ILIM trip threshold from 20% to 100%
in 20% increments
ILIM Ramp Period
OSCILLATOR
Oscillator Frequency
FSEL = VL
200
FSEL = unconnected
300
FSEL = REF
400
FSEL = GND
On Time (Note 1)
kHz
550
FSEL = VL
2.18
2.5
2.83
FSEL not connected
1.45
1.67
1.89
FSEL = REF
1.09
1.25
1.41
FSEL = GND
0.82
0.91
1.00
350
400
Minimum Off Time (Note 1)
µs
ns
CURRENT LIMIT
Current-Limit Threshold
(Positive Direction)
Current-Limit Threshold
(Negative Direction)
LX to PGND, ILIM = VL
90
100
110
LX to PGND, RILIM = 100kΩ
40
50
60
LX to PGND, RILIM = 400kΩ
170
200
230
LX to PGND, ILIM = VL, with percentage of positive
current-limit threshold
-90
-110
-130
ILIM Input Current
5
mV
%
µA
VL REGULATOR
Output Voltage
5.5V < V+ < 14V
1mA < IVL < 35mA
Line Regulation
5.5V < V+ < 14V, IVL = 10mA
4.8
5.0
0.2
RMS Output Current
Bypass Capacitor
5.2
%
35
ESR < 100mΩ
V
2.2
mA
µF
DRIVER
DH Gate-Driver On-Resistance
VBST - VLX = 5V
1.4
2.5
Ω
DL Gate-Driver On-Resistance
(Source)
DL high state
1.6
3
Ω
DL Gate-Driver On-Resistance
(Sink)
DL low state
0.75
1.25
Ω
Dead Time
DL rising
32
DL falling
30
ns
FSEL LOGIC
Logic Input Current
-3
Logic GND Level
3
µA
0.5
V
Logic REF Level
FSEL = VREF
1.65
2.35
V
Logic Float Level
FSEL floating
3.15
3.85
V
_______________________________________________________________________________________
3
MAX1917
ELECTRICAL CHARACTERISTICS (continued)
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise specified.)
PARAMETER
Logic VL Level
CONDITIONS
FSEL = VL
MIN
TYP
MAX
VL - 0.4
UNITS
V
EN/HSD LOGIC
EN/HSD Shutdown Current
Max IEN/HSD for VEN/HSD = 0.8V
0.5
Logic High
VL = V+ = 4.5V to 5.5V, 100mV hysteresis
1.45
Logic Low
VL = V+ = 4.5V to 5.5V
3.0
µA
V
0.8
V
POWER-OK OUTPUT
POK Output Low Level
ISINK = 2mA
0.4
%VDDR/
2
%VDDR/
2
%VDDR/
2
%VDDR/
2
V
POK Output High Leakage
VPOK = 5.5V
5
µA
Upper VTT Threshold
110
112
114
Lower VTT Threshold
86
88
90
Upper VTTR Threshold
110
112
114
Lower VTTR Threshold
86
88
90
ELECTRICAL CHARACTERISTICS
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = -40°C to +85°C, unless otherwise specified.) (Note 2)
PARAMETER
V+ Input Voltage Range
EN/HSD Input Voltage Range
CONDITIONS
MAX
UNITS
5.5
14.0
V
VL = V+
4.5
5.5
V
Enabled
1.5
15.0
V
0
3.6
V
1.2
mA
250
µA
DDR Input Voltage Range
V+ Supply Current
MIN
TYP
VTT = 2.0V
DDR Supply Current
EN/HSD Supply Current
VEN/HSD = 2.5V
10
µA
VL Supply Current
VL = V+ = 5.5V
1.2
mA
V+ Shutdown Supply Current
EN/HSD = 0V
5
µA
DDR Shutdown Supply Current
EN/HSD = 0V
1
µA
VL Shutdown Supply Current
VL = V+ = 5.5V
5
µA
VL Undervoltage Lockout
Threshold
Rising edge, hysteresis = 40mV
4.05
4.40
V
VVTT = 2.5V
-0.15
0
µA
0
1.8
V
Overload range, VDDR = 1.8V
49.5
50.5
Overload range, VDDR = 3.6V
49.5
50.5
Reference Output Voltage
V+ = VL = 4.5V to 5.5V, IREF = 0
1.98
2.02
V
Reference Load Regulation
V+ = VL = 5V, IREF = 0 to 50µA
10
mV
VTT
VTT Input Bias Current
VTT Feedback Voltage Range
VTT Feedback Voltage
Accuracy
%VDDR
REFERENCE
4
_______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = -40°C to +85°C, unless otherwise specified.) (Note 2)
PARAMETER
Reference UVLO
CONDITIONS
V+ = VL = 5V
MIN
TYP
MAX
UNITS
1.5
1.7
V
0
1.8
V
49.5
50.5
VTTR
VTTR Output Voltage Range
IVTTR = -5mA to +5mA
VTTR Output Accuracy
IVTTR = -25mA to +25mA, VDDR = 1.8V
49
51
IVTTR = -25mA to +25mA, VDDR = 3.6V
49.5
50.5
%VDDR
OSCILLATOR
On Time (Note 1)
FSEL = VL
2.18
2.83
FSEL not connected
1.45
1.89
FSEL = REF
1.09
1.41
FSEL = GND
0.82
1.00
Minimum Off Time (Note 1)
400
µs
ns
CURRENT LIMIT
Current-Limit Threshold
(Positive Direction)
Current-Limit Threshold
(Negative Direction)
LX to PGND, ILIM = VL
85
110
LX to PGND, RILIM = 100kΩ
35
60
LX to PGND, RILIM = 400kΩ
160
230
LX to PGND, ILIM = VL, with percentage of positive
current-limit threshold
-90
-130
%
5.5V < V+ < 14V; 1mA < IVL < 35mA
4.8
5.2
V
35
mA
ESR < 100mΩ
2.2
mV
VL REGULATOR
Output Voltage
RMS Output Current
Bypass Capacitor
µF
FSEL LOGIC
Logic Input Current
3
µA
0.5
V
1.65
2.35
V
3.15
3.85
V
Logic GND Level
Logic REF Level
FSEL = VREF
Logic Float Level
FSEL floating
Logic VL Level
FSEL = VL
VL - 0.4
V
EN/HSD LOGIC
EN/HSD Shutdown Current
IEN/HSD for VEN/HSD = 0.8V
0.5
Logic High
VL = V+ = 4.5V to 5.5V, 100mV hysteresis
1.45
Logic Low
VL = V+ = 4.5V to 5.5V
3.0
µA
0.8
V
V
POWER-OK OUTPUT
Upper VTT Threshold
110
114
Lower VTT Threshold
86
90
%VDDR
/2
%VDDR
/2
_______________________________________________________________________________________
5
MAX1917
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, VEN/HSD = VDDR = 2.5V, CVL = 4.7µF, CVTTR = 1µF, CREF = 0.22µF, VFSEL = 0, ILIM = VL, PGND = LX = POK = GND,
BST = VL. Specifications are for TA = -40°C to +85°C, unless otherwise specified.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POK Output Low Level
ISINK = 2mA
0.4
%VDDR
/2
%VDDR
/2
V
POK Output High Leakage
VPOK = 5.5V
5
µA
Upper VTTR Threshold
110
114
Lower VTTR Threshold
86
90
Note 1: On Time and Off Time specifications are measured from 50% point to 50% point at the DH pin with LX forced to 0V, BST
forced to 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching
speeds.
Note 2: Specifications to -40°C are guaranteed by design and are not production tested.
Typical Operating Characteristics
(V+ = 12V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.)
VIN = 5V
80
VIN = 2V
70
92
90
88
86
84
VIN = 5V
80
60
40
30
80
20
78
10
CIRCUIT OF FIGURE 3
1.0
0.1
10.0
1.0
10.0
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
AT 0.9V OUTPUT
FREQUENCY vs. LOAD CURRENT
AT 1.25V OUTPUT
FREQUENCY vs. LOAD CURRENT
AT 0.9V OUTPUT
80
VIN = 5V
70
65
550
VIN = 5V
500
VIN = 12V
450
MAX1917 toc06
VIN = 2.5V
600
FREQUENCY (kHz)
FREQUENCY (kHz)
600
650
MAX1917 toc05
650
MAX1917 toc04
VIN = 2.5V
85
75
1.0
LOAD CURRENT (A)
95
90
0.1
10.0
CIRCUIT OF FIGURE 4
0
76
0.1
VIN = 12V
50
60
CIRCUIT OF FIGURE 3
VIN = 5V
70
82
50
VIN = 2.5V
90
65
55
MAX1917 toc03
VIN = 2.5V
EFFICIENCY (%)
85
EFFICIENCY (%)
EFFICIENCY (%)
90
94
100
MAX1917 toc02
VIN = 2.5V
75
96
MAX1917 toc01
100
95
EFFICIENCY vs. LOAD CURRENT
AT 1.25V OUTPUT
EFFICIENCY vs. LOAD CURRENT
AT 0.9V OUTPUT
EFFICIENCY vs. LOAD CURRENT
AT 1.25V OUTPUT
EFFICIENCY (%)
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
550
VIN = 2.5V
500
VIN = 5V
450
400
400
60
CIRCUIT OF FIGURE 4
50
CIRCUIT OF FIGURE 3
CIRCUIT OF FIGURE 3
300
0.1
1.0
LOAD CURRENT (A)
6
350
350
55
10.0
300
-8
-6
-4
-2
0
2
LOAD CURRENT (A)
4
6
8
-8
-6
-4
-2
0
2
LOAD CURRENT (A)
_______________________________________________________________________________________
4
6
8
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
FREQUENCY vs. INPUT VOLTAGE
500
IOUT = 0.1A
450
534
532
530
528
526
400
524
350
CIRCUIT OF FIGURE 3
5
7
9
11
13
15
-40
-20
40
60
80
LOAD REGULATION WITHOUT
DROOP RESISTOR
MAX1917 toc10
1.32
1.7
1.5
1.3
1.1
0.9
1.29
VIN = 5V
VIN = 12V
1.28
1.27
1.26
1.25
5
7
9
11
13
9
11
13
15
1.29
VIN = 5V
1.27
1.25
1.23
VIN = 2.5V
1.21
1.19
1.17
1.22
15
7
VIN = 12V
1.31
1.23
CIRCUIT OF FIGURE 3
5
VDDR = 2.5V
1.33
VIN = 2.5V
1.24
0.5
1.35
OUTPUT VOLTAGE (V)
1.9
3
LOAD REGULATION WITH
DROOP RESISTOR
1.30
OUTPUT VOLTAGE (V)
2.1
1
100
VDDR = 2.5V
1.31
CIRCUIT OF FIGURE 6
INPUT VOLTAGE (V)
SHUTDOWN CURRENT
vs. INPUT VOLTAGE
2.3
3
20
TEMPERATURE (°C)
2.5
1
0
INPUT VOLTAGE (V)
0.7
2.0
1.0
MAX1917 toc11
3
2.5
1.5
520
1
3.0
522
CIRCUIT OF FIGURE 3
300
MAX1917 toc09
3.5
MAX1917 toc12
FREQUENCY (kHz)
550
536
SHUTDOWN CURRENT (µA)
IOUT = 7A
ILOAD = 3.5A
538
4.0
MAX1917 toc08
600
FREQUENCY (kHz)
540
MAX1917 toc07
650
SHUTDOWN CURRENT (mA)
SHUTDOWN CURRENT
vs. INPUT VOLTAGE
FREQUENCY vs. TEMPERATURE
MAX1917
Typical Operating Characteristics (continued)
(V+ = 12V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.)
1.15
-7
-5
-3
-1
1
3
5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
TRANSIENT LOAD RESPONSE
WITHOUT DROOP RESISTOR
TRANSIENT LOAD RESPONSE
WITH DROOP RESISTOR
MAX1917 toc13
7
-8
-6
-4
-2
0
2
4
6
8
LOAD CURRENT (A)
POWER-UP WITH VDDR TRACKING
MAX1917 toc14
MAX1917 toc15
VOUT
1V/div
VVTT
50mV/div
VVTT
50mV/div
VPOK
5V/div
VDDR
2.5V
VEN/HSD
10V/div
0A
OA
CIRCUIT OF FIGURE 3
20µs/div
IOUT
5A/div
CIRCUIT OF FIGURE 3
20µs/div
IOUT
5A/div
400µs/div
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(V+ = 12V, VOUT = 1.25V, TA = +25°C, unless otherwise noted.)
INDUCTOR PEAK AND VALLEY CURRENT
vs. INPUT VOLTAGE AT CURRENT LIMIT
CURRENT LIMIT vs. TEMPERATURE
16
12
RILIM = 402kΩ
10
8
6
RILIM = 200kΩ
4
RILIM = 400kΩ
16
INDUCTOR CURRENT (A)
14
MAX1917 toc17
18
MAX1917 toc16
18
CURRENT LIMIT (A)
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
14
IPEAK
12
IVALLEY
10
2
CIRCUIT OF FIGURE 3
8
0
-40
-20
0
20
40
60
80
100
1
3
5
7
9
11
13
15
VIN (V)
TEMPERATURE (°C)
Pin Description
PIN
8
NAME
FUNCTION
1
EN/HSD
Enable/High-Side Drain. Connect to the high-side N-FET drain for normal operation. Leave unconnected or
connect to GND for low-power shutdown.
2
DDR
DDR Reference Input. An applied voltage at DDR sets VVTT and VVTTR to 1/2VDDR. DDR voltage range is
from 0 to 3.6V.
3
POK
Power-OK Output. POK is an open-drain output and is logic high when both VTT and VTTR are within 12%
of regulation. POK is pulled low in shutdown.
4
VTT
VTT Feedback Input. Connect to VTT output.
5
ILIM
Current-Limit Threshold Adjustment. Connect a resistor from ILIM to GND to set the current-limit threshold,
or connect ILIM to VL for default setting. See the Setting the Current Limit section.
6
FSEL
Frequency Select. Selects the switching frequency of the MAX1917. See Table 1 for configuration of FSEL.
7
REF
Reference Bypass. Connect a 0.22µF or larger capacitor from REF to GND.
8
GND
Ground
9
VTTR
VTTR Reference Output. Connect a 1µF or larger capacitor from VTTR to GND. VTTR is capable of
sourcing and sinking up to 25mA.
10
V+
Input Supply Voltage. Supply input for the VL regulator and the VTTR regulator. Bypass with a 0.22µF or
larger capacitor.
11
VL
Internal Regulator Output. Connect a 2.2µF or larger capacitor from VL to GND. VL can be connected to
V+ if the operating range is 4.5V to 5.5V.
12
DL
Low-Side MOSFET Gate Drive. Connect to the gate of the low-side N-channel MOSFET.
13
PGND
Power Ground
14
BST
Bootstrapped Supply to Drive High-Side N-Channel MOSFET. Connect a 0.47µF or larger capacitor from
BST to LX.
15
DH
High-Side MOSFET Gate Drive. Connect to the high-side N-channel MOSFET gate.
16
LX
Inductor Switching Node
_______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
ILIM
1-SHOT
FSEL
VTT
ON TIME
COMPUTE
Q
TRIG
5µA
BST
S
TON
TRIG
POK
DH
Q
Q
R
1-SHOT
Σ
LX
DDR
VL
DL
EN/HSD
PGND
VTT
V+
VL
5V
REF
2V
REF
REF
GND
MAX1917
VTTR
_______________________________________________________________________________________
9
MAX1917
Functional Diagram
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Detailed Description
fS =
Internal Linear Regulator (VL)
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, MOSFET driver, logic, reference, and other blocks within the IC. This 5V lowdropout (LDO) linear regulator supplies up to 35mA for
MOSFET gate-drive and external loads. For supply voltages between 4.5V and 5.5V, connect VL to V+. This
bypasses the VL regulator, which improves efficiency,
and allows the IC to function at lower input voltages.
0.5 × VDDR + IO (RDSONL + RDC )
× 103 kHz
t ON × VIN + IO (RDSONL − RDSONH )
(
)
where IO is the output current, RDSONH is the on-resistance of the high-side MOSFET, R DSONL is the onresistance of the low-side MOSFET, and RDC is the DC
resistance of the output inductor. The above equation is
valid only when FSEL is connected to ground. The ideal
switching frequency for VDDR = 2.5V is about 550kHz.
The switching frequency, which is almost constant,
results in relatively constant inductor ripple current
regardless of input voltage and predictable output voltage ripple. This feature eases design methodology.
Switching frequency increases for positive (sourcing)
load current and decreases for negative (sinking) load
current, due to the changing voltage drop across the
low-side MOSFET, which changes the inductor-current
discharge ramp rate. The on times guaranteed in the
Electrical Characteristics tables are also influenced by
switching delays caused by the loading effect of the
external power MOSFETs.
On-Time One-Shot and
Switching Frequency
The heart of the PWM is the one-shot that sets the highside switch on time. This fast, low-jitter, adjustable oneshot includes circuitry that varies the on time in response
to both input and output voltages. The high-side switch
on time is inversely proportional to the input voltage as
measured by the EN/HSD input, and is directly proportional to the VTT output voltage. This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. The switching frequency can be selected to avoid noise-sensitive regions
such as the 455kHz IF band. Also, with a constant
switching frequency, the inductor ripple-current operating point remains relatively constant, resulting in easy
design methodology and predictable output voltage ripple. The general formula for on time (tON) is:
VTTR Reference
The MAX1917 VTTR output is capable of sourcing or
sinking up to 25mA of current. The VTTR output voltage
is one half of the voltage applied to the DDR input.
Bypass VTTR with at least a 1.0µF capacitor.
EN/HSD Function
t ON = K × N ×
V
× DDR µs
VHSD
2
1
In order to reduce pin count and package size, the
MAX1917 features a dual-function input pin, EN/HSD.
When EN/HSD is connected to ground, the internal circuitry powers off, reducing current consumption to less
than 5µA typical (circuit of Figure 6). To enable normal
operation, connect EN/HSD to the drain of the high-side
MOSFET. If EN/HSD is not grounded, it becomes an
input that monitors the high-side MOSFET drain voltage
(converter input voltage) and uses that measurement to
calculate the appropriate on time for the converter.
Therefore, EN/HSD must be connected to this node in
order for the controller to operate properly.
where VHSD and VDDR are the voltages measured at
EN/HSD and DDR, respectively, and K = 1.7µs. The
value of N depends on the configuration of FSEL and is
listed in Table 1.
The actual switching frequency, which is given by the
following equation, varies slightly due to voltage drop
across the on-resistance of the MOSFETs and the DC
resistance of the output inductor:
Table 1. Configuration of FSEL
FSEL CONNECTED
TO
N
tON (µs)
FREQUENCY (kHz)
CONDITION
Ground
1.00
0.91
550
0.5VDDR / VHSD = 0.5
REF
1.33
1.25
400
0.5VDDR / VHSD = 0.5
Floating
2.00
1.66
300
0.5VDDR / VHSD = 0.5
VL
3.00
2.50
200
0.5VDDR / VHSD = 0.5
10
______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Overcurrent Protection
The current-limit circuit employs a unique “valley” current-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is greater than the currentlimit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of
the MOSFET on-resistance, inductor value, and input
voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. There is also a negative current limit that prevents excessive reverse inductor
currents when VOUT is sinking current. The negative
current-limit threshold is set to approximately 110% of
the positive current limit, and tracks the positive current
limit when ILIM is adjusted. The current-limit threshold
can be adjusted with an external resistor (RILIM) at ILIM.
A precision 5µA pullup current source at ILIM sets a
voltage drop on this resistor, adjusting the current-limit
threshold from <50mV to >200mV. In the adjustable
mode, the current-limit threshold voltage is precisely
1/10th the voltage seen at ILIM.
Therefore, choose RILIM equal to 2kΩ/mV of the current-limit threshold. The threshold defaults to 100mV
when ILIM is connected to VL. The logic threshold for
switchover to the 100mV default value is approximately
VL - 1V. The adjustable current limit can accommodate
VIN
POK
various MOSFETs. A capacitor in parallel with RILIM can
provide a variable soft-start function.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signals seen by LX and PGND. The IC must
be mounted close to the low-side MOSFET with short,
direct traces making a Kelvin-sense connection to the
source and drain terminals. See the PC Board Layout
section.
Voltage Positioning
The quick-PWM control architecture responds virtually
instantaneously to transient load changes and eliminates the control loop delay of conventional PWM controllers. As a result, a large portion of the voltage
deviation during a step load change is from the equivalent series resistance (ESR) of the output capacitors.
For DDR termination applications, the maximum
allowed voltage deviation is ±40mV for any output load
transition from sourcing current to sinking current.
Passive voltage positioning adjusts the converter’s output voltage based on its load current to optimize transient response and minimize the required output
capacitance. Voltage positioning is implemented by
connecting a 2mΩ resistor as shown in Figure 1.
MOSFET Drivers
The DH and DL drivers are optimized for driving moderate-size, high-side and larger, low-side power
MOSFETs and are optimized for 2.5V and 5V input voltages. The drivers are sized to drive MOSFETs that can
deliver up to 25A output current. An adaptive deadtime circuit monitors the DL output and prevents the
VL
POK
RBST
VL
BST
V+
V+
DDR
BST
MAX1917
DDR
DH
EN/HSD
LX
REF
DL
RDRP
2mΩ
VOUT
MAX1917
DH
EN/HSD
LX
REF
DL
4 x 270µF
2V
ILIM
PGND
ILIM
PGND
FSEL
VTT
FSEL
VTT
GND
VTTR
GND
VTTR
VTTR
Figure 1. Using a Resistor for Voltage Positioning
Figure 2. Increasing the On Time of the High-Side MOSFET
______________________________________________________________________________________
11
MAX1917
Voltage Reference
The voltage at REF is nominally 2.00V. Connect a 0.22µF
ceramic bypass capacitor between REF and GND.
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
high-side FET from turning on until DL is fully off. There
must be a low-resistance, low-inductance path from the
DL driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the
sense circuitry in the MAX1917 interprets the MOSFET
gate as off while there is actually still charge left on the
gate. Use very short, wide traces measuring 10
squares to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the MAX1917). The dead time at
the other edge (DH turning off) is determined by a fixed
35ns (typ) internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.5Ω (typ) on-
resistance. This helps prevent DL from being pulled up
during the fast rise time of the inductor node, due to
capacitive coupling from the drain to the gate of the
massive low-side synchronous-rectifier MOSFET. Some
combinations of high- and low-side FETs may be
encountered that cause excessive gate-drain coupling,
which can lead to efficiency-killing, EMI-producing
shoot-through currents. This can often be remedied by
adding a resistor (R BST ) in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 2).
Typical Application Circuits
VL
R2
5.1kΩ
VL
R3
20kΩ
2.5V
3
POK
5.5V TO 14V
10
V+
VDDR
SHDN
Q3
2N7002K
2
C9
0.47µF/25V
C8
0.47µF/10V
VL
1
7
5
11
BST
V+
DDR
MAX1917
DH
EN/HSD
LX
REF
DL
ILIM
D1
CMPSH-3
VL
POK
PGND
14
15
C3
4.7µF
10V
C4
0.47µF
10V
C2
2 x 330µF
6V
C1
1µF
6.3V
Q1
IRF7463
1.25V AT 7A
16
2.5V
12
L1
0.68µH/9A
Q2
IRF7463
C6
6 x 270µF
2V
13
VIN
VOUT
C5
2 x 10µF
6.3V
PGND
6
8
FSEL
VTT
GND
VTTR
4
9
C7
1µF/6.3V
VTTR
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
Figure 3. Typical Application Circuit for 1.25V at 7A Output
12
______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
VL
R2
5.1kΩ
VL
R3
20kΩ
2.5V
3
POK
5.5V TO 14V
10
V+
2
VDDR
C9
0.47µF/25V
C8
0.47µF/10V
SHDN
Q3
2N7002K
VL
1
7
5
POK
VL
V+
DDR
BST
MAX1917
DH
EN/HSD
LX
REF
DL
ILIM
PGND
FSEL
VTT
GND
VTTR
11
D1
CMPSH-3
14
C3
4.7µF
10V
C4
0.47µF
10V
15
C2
2 x 330µF
6V
C1
1µF
6.3V
VIN
Q1
IRF7463
2mΩ
16
2.5V
12
1.25V AT 7A
VOUT
L1
0.68µH/9A
Q2
IRF7463
C6
4 x 270µF
2V
13
PGND
6
8
4
9
C7
1µF/6.3V
VTTR
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS
Figure 4. Typical Application Circuit for 1.25V at 7A Output Using Voltage Positioning
VL
R2
5.1kΩ
VL
R3
20kΩ
2.5V
3
POK
5.5V TO 14V
10
V+
VDDR
SHDN
Q3
2N7002K
2
C9
0.47µF/25V
C8
0.47µF/10V
VL
1
7
5
POK
VL
V+
DDR
EN/HSD
REF
ILIM
BST
MAX1917
DH
LX
DL
PGND
11
14
15
D1
CMPSH-3
C3
2.2µF
10V
C4
0.22µF
10V
C2
330µF
6V
C1
1µF
6.3V
VIN
Q1
IRF7811W
1.25V AT 3.5A
16
2.5V
12
Q2
IRF7811W C6
3 x 270µF
2V
13
VOUT
L1
1.0µH/5A
C5
10µF
6.3V
PGND
6
8
FSEL
VTT
GND
VTTR
4
9
C7
1µF/6.3V
VTTR
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
Figure 5. Typical Application Circuit for 1.25V at 3.5A Output
______________________________________________________________________________________
13
MAX1917
Typical Application Circuits (continued)
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
MAX1917
Typical Application Circuits (continued)
R2
10kΩ
VL
Q3
Si1029X
SHDN
VL
R3
20kΩ`
2.5V
3
POK
5.5V TO 14V
V+
10
2
VDDR
C9
0.47µF/25V
1
7
VL
C8
0.47µF/10V
5
POK
VL
V+
BST
MAX1917
DDR
EN/HSD
REF
DH
LX
DL
ILIM
PGND
6 FSEL
VTT
11
14
15
D1
CMPSH-3
C3
2.2µF
10V
C4
0.22µF
10V
C1
1µF
6.3V
C2
330µF
6V
Q1
IRF7811W
1.25V AT 3.5A
16
2.5V
12
L1
1.0µH/5A
Q2
IRF7811W C6
3 x 270µF
2V
13
VIN
VOUT
C5
10µF
6.3V
PGND
8
GND
VTTR
4
9
C7
1µF/10V
VTTR
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
Figure 6. Typical Application Circuit Using P/N-Channel MOSFETs for EN to Minimize the Supply Current from VIN in Shutdown Mode
5V
R2
5.1kΩ
R3
20kΩ
3
POK
10
2
C9
0.22µF
25V
SHDN
Q3
2N7002K
R6
1
C8
0.47µF/10V
VL
7
5
6
8
POK
VL
V+
DDR
EN/HSD
BST
MAX1917
DH
LX
11
14
15
16
12
REF
ILIM
DL
PGND
FSEL
VTT
GND
VTTR
D1
CMPSH-3
C3
4.7µF
10V
C4
0.47µF
10V
C2
4 x 330µF
6V
4.5V TO 15V
VIN
C1
1µF
25V
Q1
IRF7822
2.5V AT 12A
VOUT
2.5V
L1
0.75µH/24A
Q2
IRF7822
R4
15kΩ
0.1%
13
C6
3 x 560µF
4V
C5
1µF
6.3V
R5
10kΩ
0.1%
4
PGND
9
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS
Figure 7. Circuit to Generate a Fixed 2.5V at 12A Output with a Wide Input Voltage Range
14
______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple current ratio). The
primary design trade-off is in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
input voltage. The minimum value (VIN(MIN)) must
account for the lowest input voltage after drops due
to connectors, fuses, and battery selector switches.
If there is a choice at all, lower input voltages result
in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (I LOAD(MAX) )
determines the instantaneous component stresses
and filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-contributing components.
3) Switching Frequency. This determines the basic
trade-off between size and efficiency. The optimal
frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
proportional to frequency and VIN2. The optimum
frequency is also a moving target, due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
4) Inductor Operating Point. This provides trade-offs
between size and efficiency. Low inductor values
cause large ripple currents, resulting in the smallest
size but poor efficiency and high output noise. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit.
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on
time and minimum off time:
(∆ILOAD(MAX) ) × L
VSAG =
kHz
2 × Cf × DUTY × (VIN(MIN) − VOUT )
2
Output Inductor Selection
The switching frequency (on time) and operating point
(% ripple or LIR) determine the inductor value as follows:
VOUT
L=
f × LIR × ILOAD(MAX )
Example: ILOAD(MAX) = 7A, VOUT = 1.25V, f = 550kHz,
50% ripple current or LIR = 0.5:
L=
1.25V
= 0.65µH(0.68µH)
550kHz × 0.5 × 7A
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current:
(IPEAK): IPEAK = ILOAD(MAX) + (LIR / 2) (ILOAD(MAX))
Output Capacitor Selection
The output filter capacitor must have low enough ESR
to meet output ripple and load-transient requirements,
yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high
enough to absorb the inductor energy going from a
positive full-load to negative full-load condition or vice
versa without incurring significant over/undershoot. In
DDR termination applications where the output is subject to violent load transients, the output capacitor’s
size depends on how much ESR is needed to prevent
the output from dipping too low under a load transient.
Ignoring the sag due to finite capacitance:
RESR ≤
VDIP
ILOAD(MAX )
=
40mV
= 2.85mΩ
14A
In DDR applications, VDIP = 40mV, the output capacitor’s size depends on how much ESR is needed to
maintain an acceptable level of output voltage ripple:
RESR ≤
VP−P
9mV
=
= 2.57mΩ
LIR × ILOAD(MAX )
0.5 × 7A
______________________________________________________________________________________
15
MAX1917
Design Procedure
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
As a result, the capacitor is usually selected by ESR
and voltage rating rather than by capacitance value
(this is true of tantalums, OS-CONs, POSCAPs, and
other electrolytics).
R DRP introduces some power dissipation, which is
given by:
PD(DRP) = RDRP ✕ IOUT(MAX)2
Input Capacitor Selection
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage:
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their superior surge current
capacity:

 V
OUT × (VIN − VOUT )

IRMS = ILOAD × 


VIN


Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current. For example:
ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) ✕ ILOAD(MAX)
where ILIMIT(LOW) = minimum current-limit threshold
voltage divided by the R DS(ON) of Q2. For the
MAX1917, the minimum current-limit threshold (100mV
default setting) is 50mV. Use the worst-case maximum
value for RDS(ON) from the MOSFET Q2 data sheet, and
add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional
resistance for each °C of temperature rise.
When adjusting the current limit, use a 1% tolerance
RILIM resistor to prevent a significant increase of errors
in the current-limit tolerance.
RDRP should be chosen to handle this power dissipation.
MOSFET Power Dissipation
PD(Q1) = (VOUT / VIN(MIN)) ✕ (ILOAD2) ✕ (RDS(ON))
Generally, a small high-side MOSFET is desired in order
to reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (RDS(ON))
losses. Calculating the power dissipation in Q1 due to
switching losses is challenging because it must allow for
difficult-to-quantify factors that influence the turn-on and
turn-off times. These factors include the internal gate
resistance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The following switching loss calculation provides only a very
rough estimate and is no substitute for breadboard evaluation, preferably including a check using a thermocouple mounted on Q1:
PD(SWITCHING) =
CRSS × VIN(MAX )2 × f × ILOAD
IGATE
where CRSS is the reverse transfer capacitance of Q1
and IGATE is the peak gate-drive source/sink current.
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum input voltage:
Setting the Voltage Positioning
The droop resistor, R DRP , in series with the output
inductor before the output capacitor, sets the droop
voltage, VDRP. Choose RDRP such that the output voltage at the maximum load current, including ripple, is
just above the lower limit of the output tolerance:
RDRP <
16
PD(Q2) = (1 - VOUT / VIN(MAX)) ✕ ILOAD2 ✕ RDS(ON)
VOUT(TYP) − VOUT(MIN) − VRIPPLE /2
IOUT(MAX )
______________________________________________________________________________________
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
ILOAD = ILIMIT(HIGH) + (LIR / 2) (ILOAD(MAX))
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses.
Control IC Power Dissipation
MAX1917 has on-chip MOSFETs drivers (DH and DL)
that dissipate the power loss due to driving the external
MOSFETs. Power dissipation due to a MOSFET driver is
given by:
(
PDR = (V + ) × fS × (QGH + QGL ) + IVTTR
)
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. The
use of thick copper PC boards (2oz vs. 1oz) can
enhance full-load efficiency by 1% or more.
Correctly routing PC board traces is a difficult task
that must be approached in terms of fractions of
centimeters, where a single mΩ of excess trace
resistance causes a measurable efficiency penalty.
4) LX and PGND connections to Q2 for current limiting
must be made using Kelvin-sense connections in
order to guarantee the current-limit accuracy. With
8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
copper layer, while tying in PGND and LX inside
(underneath) the 8-pin SO package.
5) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
where QGH and QGL are the total gate charge of the
high-side and low-side MOSFETs, respectively. Select
the switching frequency and V+ correctly to ensure the
power dissipation does not exceed the package power
dissipation requirement.
6) Ensure that the VTT feedback connection to COUT
is short and direct. In some cases, it may be desirable to deliberately introduce some trace length
(droop resistance) between the FB inductor node
and the output filter capacitor.
Applications Information
7) VTT feedback sense point should also be as close
as possible to the load connection.
PC Board Layout
8) Route high-speed switching nodes away from sensitive analog nodes (DDR, EN/HSD, REF, ILIM).
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
9) Make all pin-strap control input connections (ILIM,
etc.) to GND or VL close to the chip, and do not
connect to PGND.
Chip Information
TRANSISTOR COUNT: 2708
PROCESS: BiCMOS
2) Connect GND and PGND together as close to the
IC as possible.
______________________________________________________________________________________
17
MAX1917
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than or
equal to ILOAD(MAX). To protect against this condition,
design the circuit to tolerate:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.