ETC DEM-ADS7833

®
DEM-ADS7833
EVALUATION FIXTURE
OVERVIEW
OPERATING THE DEM-ADS7833
The DEM-ADS7833 is operated via a series of menus
which are displayed on the LCD display. The five
buttons PREVIOUS DISPLAY, NEXT DISPLAY,
DOWN, UP, and CLEAR are used to step through the
various menus and to change options within the menus.
The PREVIOUS DISPLAY and NEXT DISPLAY
buttons are used to step through the different menus.
These buttons have no other function. Both buttons
will auto-repeat if held down. Figure 1 shows all of the
available menus and the sequence in which they are
displayed.
The DEM-ADS7833 allows for quick evaluation of
the ADS7833. The evaluation fixture is completely
stand-alone and includes the ADS7833, a DSP
(Motorola DSP56004), RAM, ROM, an LCD display,
a simple “keyboard,” a 16-bit DAC, the necessary
input/output connectors, and a breadboard area.
The LCD display and keyboard allow the user to
completely exercise the ADS7833—its input channels, sample/holds, programmable gain amplifiers, and
8-bit DAC. Results from the three internal analog-todigital (A/D) converters can be displayed on the LCD
panel. In addition, any A/D converter result can be
reconstructed on either an 8-bit DAC (internal to the
ADS7833) or a 16-bit DAC (DAC56), or both. For
this converter’s results, the minimum and maximum
output code is maintained as well as a running average.
The UP and DOWN buttons are used to change options within each menu. The change which occurs and
the number of options which are possible vary from
menu to menu. Figure 1 contains some information as
to the purpose of each menu and the available options.
The portion of each menu which will change when the
UP or DOWN button is pressed is highlighted in gray.
Figure 1 can be used as a “quickstart” guide—but the
best way to learn about the DEM-ADS7833 is to
simply to play with it.
InternationalAirportIndustrialPark • MailingAddress:POBox11400,Tucson,AZ85734 • StreetAddress:6730S.TucsonBlvd.,Tucson,AZ 85706 • Tel:(520)746-1111 • Twx:910-952-1111
Internet:http://www.burr-brown.com/ • FAXLine:(800)548-6133(US/CanadaOnly) • Cable:BBRCORP • Telex:066-6491 • FAX:(520)889-1510 • ImmediateProductInfo:(800)548-6132
©
1996 Burr-Brown Corporation
LI-485
Printed in U.S.A. December, 1996
Menu 1
Channel Select Mode:
V1-1/S1 V2-1/S3 V3-1/S5
There are six different configurations that can be
selected. Note that in mode 4 (V1-3/S2 V2-3/S4
V3-3/S5), every other conversion result must be
thrown away.
V1-1/S1
001
The header in this menu changes depending on
the mode selected in menu 1. The UP/DOWN
buttons control the DAC56 code (and voltage).
Menu 5 will change accordingly.
Menu 2
V2-1/S3
002
V3-1/S5
FFF
Menu 3
There are four selections: 1.00, 1.25, 2.50, and
5.00 V/V. Note that for channels V3-2, V3-3, and
V3-4, the gain is fixed at 1.00V/V (but the display
will change as the gain is valid for V1-X and V2-X ).
Gain Setting:
1.00 V/V
Menu 4
ADS7833 DAC Code:
with reconstruction
80
off
Menu 5
DAC56 Code:
2AAA
with reconstruction off
Menu 6
The ADS7833 8-bit DAC range is 00h (0V) to FFh
(2.5V).
The 16-bit DAC56 range is 8000h (–3V) to 7FFFh
(3V).
Three possible selections: ADC1, ADC2, or ADC3.
This determines the ADC result which will be used
ADC1 to P2-PARALLEL,
DAC Reconstruct, & Stats in combination with the next four menus and that
will appear on the PARALLEL I/O Connector.
Menu 7
The 8 most significant bits of the ADC result
7833 DAC Reconstruct OFF selected in menu 6 (or 10) will be sent to the
ADS7833 8-bit DAC when reconstruction is on.
ADC1 result on P1-AOUT
Menu 8
DAC56 Reconstruct OFF
ADC1 result on P1-DAC56
Menu 9
ADC1 Results Used to
Compute Average: 512
Menu 10
The ADC result selected in menu 6 (or 10) will be
padded with zeros and sent to the 16-bit DAC56
when reconstruction is on.
N conversion results from the ADC selected in
menu 6 (or 10) will be continuously averaged for
use in menu 10. N can be 2, 4, 8, 16, 32, 64,
128, 256, or 512.
This is the minimum and maximum code and most
Stats
ADC1:
Min
019
Avg
019
Max recent N average from the ADC selected in menu
01B 6 (or here). The min/max are cleared by pressing
CLEAR or changing menu 1, 3, 6 (or here).
Menu 11
ADS7833 Cycle Time:
=(32*(1+09h))/fOSC
Menu 12
LCD
Update
SLOW
Rate:
Menu 13
Applications Hotline
1-800-548-6132
The cycle time of the ADS7833 can be changed
from 5.3µs (188kHz) to 171µs (5.9kHz). This is
also the update rate of the DACs when reconstruction is on (except in mode 4 where it is 1/2 this rate).
This menu controls the speed of the LCD update
for some numeric results. When SLOW is selected,
the update rate is about every 1/2 second; when
FAST is selected, 20 or more times per second.
Outside the United States, contact your local
Burr-Brown sales office.
The grey area of each menu shows the selection which will change when either the UP or DOWN button is pressed. The
default for each selection is shown. The selection reverts to its default when the power is cycled or the RESET button is
pressed.
FIGURE 1. Summary of Menu Structure.
®
DEM-ADS7833
2
V1-1
SH1
PGA
ADC1
SOUT1
V1-3
SH2
PGA
ADC1
SOUT1
V2-1
SH3
PGA
ADC2
SOUT2
V2-3
SH4
PGA
ADC2
SOUT2
V3-1
SH5
PGA
ADC3
SOUT3
V3-3
SH5
ADC3
SOUT3
Mode 1: V1-1/S1 V2-1/S3 V3-1/S5
Mode 4: V1-3/S2 V2-3/S4 V3-3/S5
V1-2
SH1
PGA
ADC1
SOUT1
V1-2
SH6
PGA
ADC1
SOUT1
V2-2
SH3
PGA
ADC2
SOUT2
V2-2
SH7
PGA
ADC2
SOUT2
V3-2
SH5
ADC3
SOUT3
V3-4
SH5
ADC3
SOUT3
Mode 2: V1-2/S1 V2-2/S3 V3-2/S5
Mode 5: V1-2/S6 V2-2/S7 V3-4/S5
V1-3
SH1
PGA
ADC1
SOUT1
V1-3
SH6
PGA
ADC1
SOUT1
V2-3
SH3
PGA
ADC2
SOUT2
V2-3
SH7
PGA
ADC2
SOUT2
V3-3
SH5
ADC3
SOUT3
V3-4
SH5
ADC3
SOUT3
Mode 3: V1-3/S1 V2-3/S3 V3-3/S5
Mode 6: V1-3/S6 V2-3/S7 V3-4/S5
FIGURE 2. Channel Select Modes.
The UP and DOWN buttons may or may not auto-repeat. In
addition, options may or may not “roll-over” back to the
beginning or ending option. These actions depend on the
particular menu and the purpose of the option. Several
menus contain hexadecimal values which will change in
larger and larger proportions while the UP or DOWN button
is held down.
some cases, the ADS7833 can only be operated in certain
modes and the limitation resides in the ADS7833 itself.
However, in the majority of cases, the limitation resides in
the software running on the DSP56004. Basically, at the
highest operating speed of the ADS7833, the DSP56004
spends over 80% of its time in its main interrupt routine.
This routine must fetch each A/D result from the ADS7833,
calculate running statistics, format data for the ADS7833
(including the 8-bit DAC), format data for the 16-bit DAC,
place parallel data out on the parallel connector, and do all
the miscellaneous housekeeping chores.
The CLEAR button has only one function in the current
revision of the software: to reset the statistics in the “Stats
ADCX” display.
LIMITATIONS OF THE DEM-ADS7833
In some cases, it may seem that the DEM-ADS7833 is being
overly restrictive on how the ADS7833 can be operated.
There are two things to keep in mind in regards to this. In
One example of a hardware limitation of the ADS7833 is the
programmable gain amplifier on A/D converter number
three. The PGA function of the ADS7833 is only valid for
input channel V3-1 and no other channel (V3-2, V3-3, or
V3-4). This is simply a hardware limitation of the ADS7833.
®
3
DEM-ADS7833
On the other hand, it could be very useful to follow more
than three input channels at one time. For example, by using
the asynchronous sample/holds, five input channels could be
monitored at 1/2 the overall conversion rate of the ADS7833.
The ADS7833 can certainly do this. Here, the limitation is
in the software: it is simply not possible to handle all of the
different software options in a reasonable period of computational time and a reasonable amount of software complexity.
A/D result. Note that this is the only menu in which the
UP/DOWN buttons are active but do not actually change the
menu itself.
Menu 3: This menu controls the gain of the internal ADS7833
PGAs. The UP/DOWN buttons are used to select one of four
gains: 1.00 V/V, 1.25 V/V, 2.50 V/V, or 5.00 V/V.
Gain Setting:
1.00 V/V
In several places throughout this manual, a limitation of the
DEM-ADS7833 is mentioned. In these cases, an attempt has
been made to make the user aware of why this limitation
exists: either due to the ADS7833 itself or due to the design
(software and hardware) of the DEM-ADS7833.
As mentioned previously, be careful of A/D converter three.
For this converter, the PGA setting is only valid for input
channel V3-1 and no other (channels V3-2, V3-3, and
V3-4 always remain at 1.00 V/V).
BASIC OPERATION
Menu 4: The next menu controls the value sent to the 8-bit
DAC on the ADS7833. The value ranges from 00 to FF
(hexadecimal, straight binary coding). This corresponds to
an output range of 0 to 2.5V.
Menu 1: The ADS7833 can be used in six basic modes of
operation as shown in Figure 2. These are really the only
modes in which the ADS7833 can be operated. While the
ADS7833 has more actual mode numbers than this, several
of these map to the same mode of operation. (However, the
exact number is important when configuring the ADS7833
as these may configure subsequent modes. For the purposes
of the DEM-ADS7833, only the six modes that are shown
are important. Consult the ADS7833 data sheet for more
information.)
ADS7833 DAC Code:
with reconstruction
The number in this menu is only valid if the ADS7833 DAC
reconstruction menu is configured to OFF (see menu 7).
Menu 5: This controls the value sent to the 16-bit DAC56.
The value ranges from 8000 to 7FFF (hexadecimal, BTC
coding). This corresponds to an output range of –3 to 3V.
The mode of operation is selected via the initial menu
display. Use the UP/DOWN buttons to select the mode:
Channel Select Mode:
V1-1/S1 V2-1/S3 V3-1/S5
DAC56 Code:
2AAA
with reconstruction off
Note that mode 4 is an unusual one for the ADS7833. In this
mode, the sample/holds SH2 and SH4 only return to the
sample configuration when the next mode does not use SH2
and SH4. This means that the ADS7833 cannot remain in
mode 4 continuously, but must alternate with another mode.
For this reason and while in this mode, the ADS7833 will
continuously alternate modes and the results from the
alternate mode will be discarded. In several cases discussed
later, this will mean that the ADS7833 appears to be converting at 1/2 of the rate set by menu 11.
The number in this menu is only valid if the DAC56 DAC
reconstruction menu is configured to OFF (see menu 8).
Also, the DAC56 value can be changed in menu 2 via the
UP/DOWN buttons (the change will be reflected in the
number displayed in this menu).
Menu 6: This menu controls a key option in regards to the
menus that follow. Figure 3 shows that this menu (as well as
menu 10) controls which A/D converter result will be used
in the next four menus. The flow of converter results shown
in Figure 3 is based solely on software design and does not
reflect any hardware limitation of the ADS7833.
Menu 2: The next menu shows the conversion results from
the most recent conversion. Two display options are available for the results: SLOW and FAST (see menu 12 for more
details). Note that the results are displayed in hexadecimal,
binary two’s complement (BTC) coding.
This menu (and menu 10) always determine which converter
result will appear on the parallel connector and that will be
monitored for the “Stats ADCX” display (menu 10). In
addition, it determines which result can be reconstructed via
the 8-bit DAC on the ADS7833 and/or the DAC56. There
are three possible options selected via the UP/DOWN
buttons: ADC1, ADC2, or ADC3.
V1-1/S1 V2-1/S3 V3-1/S5
001
002
FFF
The UP/DOWN buttons in this menu control the DAC56
(16-bit DAC) output voltage (if DAC56 reconstruction is
off). This facilitates connecting the DAC56 to a particular
input and varying the DAC output to achieve a particular
ADC1 to P2-PARALLEL,
DAC Reconstruct, & Stats
®
DEM-ADS7833
80
off
4
ADS7833 DAC Code:
80
with reconstruction off
P1
AOUT
ADS7833 DAC
ADC1
7833 DAC Reconstruct OFF
ADC1 result on P1-AOUT
ADC2
Serial-to-Parallel
Stats
ADC1:
ADC3
ADC1 to P2-PARALLEL,
DAC Reconstruct, & Stats
Min
019
Avg
019
Min
019
Avg
019
Max
01B
Statistics Computation
or
Stats
ADC1:
P2
PARALLEL
ADC1 Results Used to
Compute Average: 512
Max
01B
DAC56 Reconstruct OFF
ADC1 result on P1-DAC56
DAC56
DAC56 Code:
2AAA
with reconstruction off
P1
DAC56
FIGURE 3. Flow of ADC Results and Relationship to Various Menus.
Note that the parallel output connector will output data at
1/2 the conversion rate when the ADS7833 is in mode 4
(menu 1). In this mode, only every other conversion result
from the ADS7833 is valid (this is a hardware limitation of
the ADS7833).
Menu 8: The current ADC result selected via menu 6 (or 10)
can be reconstructed by the 16-bit DAC56. The UP/DOWN
buttons toggle this option ON or OFF.
DAC56 Reconstruct OFF
ADC1 result on P1-DAC56
Menu 7: The current ADC result selected via menu 6 (or 10)
can be reconstructed by the 8-bit DAC on the ADS7833. The
UP/DOWN buttons toggle this option ON or OFF.
Note that the least four significant bits for the DAC56 are
zero. Also, in Mode 4 (menu 1), only every other conversion
result from the ADS7833 is valid (this is a hardware limitation of the ADS7833). Therefore, the update rate of the
DAC56 will appear to be 1/2 of the conversion rate. Also,
due to the output range of the DAC56 (–3 to 3V), the output
voltage will obviously not be the same as the input voltage
to the A/D converter—but will relate in a linear manner.
7833 DAC Reconstruct OFF
ADC1 result on P1-AOUT
Note that the least four significant bits from the conversion
result are simply truncated. Also, in Mode 4 (menu 1), only
every other conversion result from the ADS7833 is valid
(this is a hardware limitation of the ADS7833). Therefore,
the update rate of the 8-bit DAC will appear to be 1/2 of the
conversion rate. Also, due to the output range of the DAC
(0 to 2.5V), the output voltage will obviously not be the
same as the input voltage to the A/D converter—but will
relate in a linear manner.
Menu 9: For the “Stats ADCX” display, the N latest conversions from the currently selected ADC (menu 6 and 10) are
averaged. The number N is selected via the UP/DOWN
buttons and this menu. The possible selections are 2, 4, 8, 16,
32, 64, 128, 256, and 512.
ADC1 Results Used to
Compute Average: 512
®
5
DEM-ADS7833
Note that the average is not a running average. The last N
conversions are summed and averaged. Then, the sum is
cleared and the next N conversions are summed and averaged.
Menu 13: The last menu displays the United States Toll-free
applications support telephone number.
Applications Hotline
1-800-548-6132
Menu 10: This menu display the statistics for the currently
selected A/D converter (this menu and menu 6): the minimum conversion result, the average of the last N conversions
(N selected in menu 9), and the maximum conversion result.
The CLEAR button can be used to reset the minimum and
maximum.
Stats
ADC1:
Min
019
Avg
019
Note that this number is valid in the United States and
Canada only. Customers in other parts of the world should
contact their local sales office for technical support.
REMOTE OPERATION
There is one additional menu which cannot be reached via
the user interface. This menu is displayed when the
REMOTE pin on P3 or the C01 pin on P2 is tied LOW (the
DEM-ADS7833 contains a pull-up on this line).
Max
01B
The maximum and minimum are continually calculated
regardless of which menu is currently active. The CLEAR
button only functions for this menu and only while this menu
is displayed. The minimum and maximum are reset when the
mode is changed (menu 1), the gain is changed (menu 3), or
the A/D converter being monitored is changed (menu 6 and
10).
REMOTE low, DSP off: set
high, push RESET to exit
When remote operation is enabled, the DSP is placed in its
STOP state after displaying the above message. This means
that the ADS7833 is no longer controlled by the DSP56004.
Instead, the ADS7833 can be controlled by a processor
external to the DEM-ADS7833. To resume normal operation, REMOTE and C01 must be a valid logic HIGH, and the
DSP must reset by pushing the RESET button or cycling the
power to the DEM-ADS7833.
Menu 11: The next menu controls the ADS7833 cycle time
(acquisition time plus conversion time). This is presented as
a formula in case the crystal oscillator frequency (U7 of the
DEM-ADS7833) is changed. With a 48MHz crystal, the
cycle time can be varied between 5.3µs (187.5kHz) and
171µs (5.86kHz). The default is 5.67µs (150kHz).
(Note that the ADS7833 is guaranteed for a minimum cycle
time of 5.67µs [maximum of 150kHz conversion rate] and
operation faster than this time is not recommended. The
ability to operate the ADS7833 faster than this is for evaluation purposes only.)
If either REMOTE or C01 is LOW when power is first
applied to the DEM-ADS7833, the serial interface lines
which connect the DSP to the ADS7833 are never taken out
of tri-state. Thus, the connection to the external processor
should be made while power is off. If this is not done, then
the possibility exists that two interface signals to the ADS7833
could be active at the same time (in contention). This is true
even if the physical connector between the two systems has
REMOTE or C01 tied low. (The detection of the remote
mode is done in software—it could take several hundred
milliseconds before the DSP detects REMOTE or C01 going
low and tri-stating the serial interface signals.)
Menu 12: The next menu simply controls how often results
are displayed in menu 2 and menu 10. The UP/DOWN
buttons select one of two speeds: SLOW or FAST. When
SLOW is selected, the results are updated approximately
twice every second. When FAST is selected, the results are
updated as fast as possible. This will vary depending on the
conversion speed of the ADS7833 (less time in the interrupt
routine means more time handling the user interface), but
will be at least 10 or more times per second.
Finally, note that it is also possible to connect the DSP56004
to an external system and have it control the ADS7833 in
that system. In this case, the interface signals to the external
ADS7833 must be connected to the DEM-ADS7833, and
the external system must be able to release control of these
signals. Connector P3 provides an easy way to make the
necessary connection. If this mode of operation is desired,
the ADS7833 that is installed in the DEM-ADS7833 must
be physically removed.
ADS7833 Cycle Time:
=(32*(1+09h))/fOSC
Note that the UP/DOWN buttons change a hexadecimal
value embedded in a formula whose other values are expressed in decimal.
LCD
Update
SLOW
CONNECTORS
Rate:
The DEM-ADS7833 has five major connectors as shown in
Figure 4: P1 (ANALOG I/O)—analog input and output
connections to the ADS7833 and the DAC56, P2 (PARALLEL I/O)—digital output connection for parallel data, P3
®
DEM-ADS7833
6
(ADS7833 DIGITAL I/O INTERFACE)—serial digital input and output connections to the ADS7833, P4 (POWER
INPUT)—±5V power connection, and P5 (OnCE PORT)—
the DSP56004 On-Chip Emulation port.
two-position blocks and P4 is made up of a single threeposition block.
DEM-ADS7833 POWER
The DEM-ADS7833 requires +5V and –5V power. These
should be provided via good quality laboratory power
supplies. Switching power supplies may degrade the performance of the ADS7833 and DAC56 unless properly filtered.
Most of the connections to these connectors are obvious and
clearly labeled on the DEM-ADS7833 and in Figure 4. P5
(the OnCE PORT) is described in the literature available
from Motorola, and this connector will be of use only to
those users who are developing a DSP5600X/ADS7833
system.
The DEM-ADS7833 has the following current requirements:
The P2 (PARALLEL I/O) connector is very straightforward.
Via the user interface, one of the three A/D converter results
is selected for output on this connector—one result for every
ADS7833 conversion period. The MSB of the result is
placed on B01 and the LSB on B12. Pins B13 through B16
are always low. DV (data valid) is used to clock the data into
an external system. Data is valid on the rising edge of DV
(500ns minimum setup and hold time). C01 duplicates the
REMOTE pin on P3 and is a digital input (with a pull-up).
C02 is also an input, but is not currently used for any
function. Finally OE is a digital input (with a pull-down)
which causes pins B01 through B16 to tri-state when high.
SUPPLY
CURRENT REQUIRED
+5V
–5V
250mA
50mA
Care should be taken so that the power supplies do not
exceed their respective voltages by more than 10%. If this is
not observed, the DEM-ADS7833 could be damaged. Likewise, the supplies should not be reversed. However, in this
case, the board does contain protection diodes which should
protect the on-board components from damage.
The P3 (ADS7833 DIGITAL I/O INTERFACE) connector
is also straightforward. Consult the ADS7833 data sheet to
understand pins DCLOCK through SOUT2. The REMOTE
pin is a digital input (with a pull-up) that causes the DSP to
enter its STOP mode when low. See the REMOTE OPERATION section of this data sheet for more information. Note
that the REMOTE pin is duplicated on P2, C01.
IMPORTANT NOTES
• The parallel output is updated by the DSP software—there
is some jitter on when the results are updated. This should
not be a problem for the majority of users, but could cause
a problem for some. The parallel data is always valid on
the rising edge of DV (data valid).
• It is not possible to get more than one conversion result
per conversion through the parallel connector. This is
limited by the DEM-ADS7833 software.
Note that the “blocks” which make up connectors P1 and P4
can be removed from the board. To do this, grasp a block
firmly by the sides and pull straight up. P1 is made up of 12
PIN 1
DAC56 Output (16-Bit DAC)
GND
V1-3P
V1-3N
V1-2P
V1-2N
V1-1P
V1-1N
AOUT (8-Bit DAC)
GND
V3-4N
V3-4P
V3-3N
V3-3P
V3-2N
V3-2P
V3-1N
V3-1P
V2-1N
V2-1P
V2-2N
V2-2P
V2-3N
V2-3P
B01 (MSB)
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12 (LSB)
B13
B14
B15
B16
DV
C01 (REMOTE)
C02
OE
PIN 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P2
PARALLEL I/O
PIN 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DCLOCK
BUSY
SERIN
ASH
CONV
CLK
SOUT1
SOUT3
SOUT2
REMOTE
DSI/ OS0
DSO
DSCK/OS1
DR
RESET
NO CONNECT
NO CONNECT
GND
GND
GND
GND
GND
GND
P5
OnCE PORT
P3
DIGITAL I/O
INTERFACE
–5V
GND
+5V
P4
POWER
INPUT
P1
ANALOG I/O
FIGURE 4. DEM-ADS7833 Connector Pin Definitions.
®
7
DEM-ADS7833
• It is not possible to reconstruct more than one ADS7833
A/D converter. If both DACs are in the reconstruct mode,
they are “reconstructing” the same A/D conversion. This
is limited by the DEM-ADS7833 software.
right hand side of connector P1). These are used to connect
one or both of the differential inputs associated with each
channel to ground. These should all be open.
• As was noted in the description of menu 1, while in mode
4 (V1-3/S2 V2-3/S4 V3-3/S5) DAC reconstruction and
parallel output data will appear at 1/2 of the rate given by
the equation in menu 11. This is a hardware limitation of
the ADS7833. Every other conversion must be in a different mode in order for the sample/holds S2 and S4 to
sample their respective input signals. The conversion
results from the alternate mode are discarded. See the
ADS7833 data sheet for more information.
THEORY OF OPERATION
Figure 5 shows a simplified connection diagram for the
DSP56004, the ADS7833 and the DAC56. The discussion
that follows pertains to this diagram. The rest of the
DEM-ADS7833 consists of a fairly classic embedded system with ROM, RAM, “keyboard,” and display. A full
schematic diagram of the DEM-ADS7833 is included in this
manual.
The DSP56004 is interfaced to the ADS7833 and DAC56
with no glue logic. This is accomplished by using both the
serial audio interface and the serial host interface of the
DSP56004. For this application, the serial host interface is
slaved to the serial audio interface and configured for 16-bit
SPI operation. With the appropriate software, this enables
the serial host interface to act as an additional serial audio
channel. (Note: the left/right signals (WST and WSR) of the
serial audio interface are ignored.)
RESTORING THE DEM-ADS7833
TO ITS ORIGINAL CONFIGURATION
It may become necessary to restore the DEM-ADS7833 to
its original “shipped” condition. This is fairly straightforward. The DEM-ADS7833 has no jumpers and the software
has no permanent memory. Therefore, simply cycling the
power or pressing RESET will ensure that the software is in
its original operational mode.
While there are no jumpers, there are “solder switches”
associated with each input channel of the ADS7833 (on the
DSP56004
ADS7833
WST
CONV
SDO0
SERIN
SDO1
ASH
SDO2
CLK
SCKT
SERIAL AUDIO
INTERFACE
SCKR
SOUT1
SDI0
SOUT2
SDI1
SOUT3
WSR
BUSY
SCK/SCL
DCLOCK
MISO/SDA
MOSI/HA0
HREQ
SS/HA2
DAC56
R34
10kΩ
LE
CLK
DATA
FIGURE 5. Basic Connection between the DSP56004, the ADS7833, and the DAC56.
®
DEM-ADS7833
8
SERIAL HOST
INTERFACE
The two interfaces operating together provide four serial
output channels (SDO0, SDO1, SDO2, MISO/SDA) and
three serial input channels (SDI0, SDI1, MOSI/HA0). Since
the ADS7833 has three serial outputs (SOUT1, SOUT2,
SOUT3), the connection between the ADS7833 and
DSP56004 is very simple for these signals (see Figure 5).
“Microprocessor Interface for Motorola DSP56004/7,” in
the ADS7833 data sheet. In the DEM-ADS7833, the slave
select line on the DSP56004 (SS/HA2) is tied low. This
allows the SDO2 pin to provide the asynchronous
sample/hold (ASH) signal to the ADS7833 while the
MISO/SDA signal is used for the DAC56.
The serial signals that must be provided to the ADS7833
consist of the following: a convert command (CONV), a
serial input (SERIN), and, optionally, an asynchronous
sample/hold (ASH). The signals which must be provided to
the DAC56 are: latch enable (LE) and serial data (DATA).
Of these five signals, two can be the same as long as the
ADS7833 is clocked at a rate of 16 clock cycles per “conversion cycle” (acquire and convert). If this done, LE and
CONV can be the same signal.
There is one major concern regarding the configuration used
for the DEM-ADS7833 (and the reason the ADS7833 data
sheet shows a different configuration): it is in violation of
guidelines for using the serial audio interface as outlined in
the DSP56004 User’s Manual. The violation is in regards to
changing the speed of the serial clock (SCKT) while the
serial audio interface is enabled. In the DEM-ADS7833
configuration, this must be done if SS/HA2 is tied low. In
Figure 4 of the ADS7833 data sheet, the speed of the serial
audio interface does not have to be changed while the
interface is enabled.
The end result is that four serial outputs are available on the
DSP56004 and four serial inputs are needed for the ADS7833
and DAC56 (CONV/LE, SERIN, ASH, DATA). Again,
Figure 5 shows the overall connections between the components. Note that the transmit clock (SCKT) of the serial
audio interface provides the master clock for serial communication to all the other synchronous clocks (SCKR,
SCK/SCL, CLK (ADS7833), and CLK (DAC56)).
In terms of the DEM-ADS7833, this violation is not a
concern. All of the DSP56004s are from the same revision
and the software has been verified to work. (The DSP56004
User Manual is not clear as to why the speed cannot be
changed. Tests were run to discover what problems occurred
when the guideline was violated and to see if it was possible
to avoid the problems. This turned out to be the case: there
are specific conditions under which the speed of the serial
clock can and can’t be changed.) Unfortunately, Burr-Brown
cannot recommend the SDO2/ASH connection and SS/HA2
tied low configuration shown in Figure 5. It is possible that
later revisions of the DSP56004 (of which there are already
several) may not work in this configuration.
Figure 6 is a simplified timing diagram of the serial signals
between the various components over a single conversion
cycle (acquire and convert). The SOUT2 (SDI1) and SOUT3
(MOSI/HA0) signals are not shown in Figure 6 as they are
the same as the SOUT1 (SDI0) signal.
IMPORTANT NOTE: the connection diagram shown in
Figure 5 is different from the diagram shown in Figure 4,
CLK (2),SCKT,
SCKR, SCK/SCL
CONV, LE
SDO0
SERIN,
SD01
B0
B7
(MSB)
8-BIT DAC CODE
GS0
(LSB)
GS1
GAIN SEL
IS0
IS1
IS2
B0
INPUT SELECT
(MSB)
ASH,
SD02
ASH CONTROL
SOUT1,
SDI0
B0
(MSB)
DATA,
MISO/SDA
B15
B11
ADC1 OUTPUT CODE
B0
(LSB) (MSB)
(LSB)
B15
DAC56 INPUT CODE
B0
(LSB) (MSB)
Pin names shown in bold are the source of the signal.
FIGURE 6. Basic Timing between the DSP56004, the ADS7833, and the DAC56.
®
9
DEM-ADS7833
Solder Switch
–
+
–
+
–
+
–
+
–
+
V3-2
V3-1
V2-1
V2-2
V2-3
FIGURE 7. DEM-ADS7833 Schematic.
®
10
P4
1
2
3
1
2
+5
-5
-5
R28
220
R29
220
R19
220
R17
220
R15
220
R13
220
R11
220
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
V2-3P
V2-3N
DNC
V2-2P
V2-2N
DNC
V2-1P
V2-1N
DNC
C4
2.2UF
C16
C15
27
34
2.2UF
+5
C13
-5
C14
.1UF
32
33
31
30
29
.1UF
28
2.2UF
35
36
37
ADS7833
U1
61
62
63
64
65
66
67
68
1
2
3
4
5
6
.1UF
C8
C7
2.2UF
7
.1uf
C3
-5
8
.1UF
C2
C1
2.2UF
9
+
SMBJ5.0GICT
D3
D4
+5
-5
220
R20
220
R18
220
R16
220
R14
220
R12
220
R10
+
D2
SW7
1
12
6
7
2
5
8
+5
11
POWER
P1-V2-3
1
2
P1-V2-2
1
2
P1-V2-1
1
2
P1-V3-1
1
2
P1-V3-2
1
2
D1
SMBJ5.0GICT
+5
GND
–5
–
+
V3-3
R9
220
TP1
DEM-ADS7833
TP2
P1-V3-3
+5
V3-1P
CLK
220
R8
V3-1N
SOUT1
R7
220
DNC
38
ASH
1
2
V3-2P
CONV
P1-V3-4
V3-2N
VDIG+
V3-3P
DGND
V3-3N
DNC
V3-4P
VDIG-
V3-4N
SOUT2
VANA+
SOUT3
AGND
39
40
41
42
DNC
–
+
+
VANASERIN
REFGND
43
DNC
V3-4
+
REFIN
BUSY
REFOUT
DCLCLOCK
AOUT
+
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
V1-3P
V1-3N
DNC
V1-2P
V1-2N
DNC
V1-1P
V1-1N
DNC
.1UF
C6
C5
2.2UF
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
3 +
2 6
-5
220
R1
220
R3
220
R5
4 OPA132U
U2
7
+5
R2
220
R4
220
R6
220
220 R21
220 R22
220 R23
220 R24
220 R25
220 R26
220 R27
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
DCLOCK
BUSY
SERIN
ASH
CONV
CLK
SOUT1
SOUT3
SOUT2
TP1
-5
+5
-5
U3
REMOTE
16
15
14
13
12
11
10
9
P3
2
4
6
8
10
12
14
16
18
20
+5
ADS7833
DIGITAL I/O
INTERFACE
1
3
5
7
9
11
13
15
17
19
SDO1
SDO2
SDO0
SCKT
SDI0
MOSI/HA0
SDI1
MISOSDA
-VS
+VS
DCOM
TRIM
+VL MSB ADJ
NC
IOUT
CLK
ACOM
LE
SJ
DATA
RF
-VL
VOUT
DAC56U
V1-3
V1-2
V1-1
AOUT
ADC BUS
+
DNC
–
+
P1-DAC56
–
+
P1-V1-3
–
+
P1-V1-2
–
+
P1-V1-1
–
+
P1-AOUT
DAC56
2
1
2
1
2
1
2
1
2
1
DEM-ADS7833
2
A
DRAWING NUMBER
VERSION
HEET
LCD1
LCD2
DB7
DB6
DB5
DB4
DB2
DB1
DB1
DB0
OF
P6
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RS
R/W
E
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
DV
C01
C02
OE
14
13
12
11
10
9
8
7
4
5
6
2
R50
10K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VO
VDD
VSS
OESW
3
2
1
CLKO2
CLKO1
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
U8
74ACT32
1Y
R51
220
+5
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
1
2
4
5
9
10
12
13
8D
7D
6D
5D
4D
3D
2D
1D
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
9
8
7
6
5
4
3
2
1
OE*
11
CLK
U10
74ACT574
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
1A
≥1 1B
6
2A
2Y
2B
8
3Y
3A
3B
11
4Y
4A
4B
3
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
U1
CLKO2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
12
13
14
15
16
17
18
19
13
14
15
18
19
20
21
22
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
11
12
13
15
16
17
18
19
U5
MCM6206CP35
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
20
E*
27
W*
22
G*
11
10
9
8
7
6
5
4
29
28
24
27
3
30
31
2
VPP
23
CE*
25
OE*
R49
10K
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
DR
LCD2
LCD1
+5
DR*
MD7
MD6
MD5
MD4
DGND
MD3
MD2
MD1
DVCC
MD0
DGND
GPIO3
GPIO2
GPIO1
GPIO0
MRD*
MWR*
MA17/MCS1*/MRAS*
MA16/MCS2*/MCAS*
+
+5
SW4
SW3
SW5
CLEAR
UP
DOWN
SW2
NEXT DISPLAY
SW1
PREVIOUS DISPLAY
SW6
RESET
REMOTE
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DSCKOS1
DSIOS0
DSO
SDI0
SDI1
WSRWST
+5
C18
2.2UF
R39
10K
MA14
MA13
CLKO1
MA12
10K R45
1
OE*
11
CLK
+5
SCKT
+5
+5
D5
BAS16
+5
10K R46
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P2
10K R47
U12
74ACT574
SCKT
+5
MA11
MA10
MA9
MA8
10K R48
1
OE*
11
CLK
10K R44
U9
74ACT574
SDO0
SDO1
SD02
MA7
10K
R34
+5
1
AGND
2
MSC0*
3
MA15/MCS3*
4
MA14
5
MA13
6
AVCC
7
MA12
8
AGND
9
QVCC
10
QGND
11
MA11
12
MA10
13
MA9
14
MA8
15
AGND
16
MA7
17
AVCC
18
MA6
19
MA5
20
MA4
MA6
MA5
MA4
10K R43
11
10K R42
PARALLEL
I/O
MOSIHAO
MOSI/HA0
SS*/HA2
HREQ*
SGND
SDO2
SDO1
SDO0
SVCC
SCKT
WST
SCKR
QGND
QVCC
SGND
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
OESW
+5
ADDRESS BUS
2
1
2
3
4
5
6
7
8
9
11
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
U9
DSP56004FJ
+V
U7
1D
2D
3D
4D
5D
6D
7D
8D
C
OE*
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
U11
74ACT573
48.0MHZ
+5
+5
+5
19
18
17
16
15
14
13
12
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
FOSC
3
4
220 R40
GND OUT
NC
MA0
MA1
MA2
MA3
+5
220 R38
+5
10K R37
10K R36
10K R35
C19
390PF
ADC/ONCE BUS
SVCC
MODC/NMI*
MODB/IRQB*
MODA/IRQA*
RESET*
MISO/SDA
SGND
PVCC
PCAP
PGND
PINIT
QGND
QVCC
EXTAL
SCK/SCL
MA0
MA1
MA2
MA3
AGND
10K R41
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
FIGURE 7. (Cont) DEM-ADS7833 Schematic.
®
C24
.1UF
C17
.1UF
SCKT
MISOSDA
+5
+5
10K R32
10K R33
C25
.1UF
C20
.1UF
+5
+5
C26
.1UF
C21
.1UF
DR
DSCKOS1
DSO
DSIOS0
+5
10K R31
+5
+5
C27
.1UF
C22
.1UF
+5
+5
+5
10K R30
C28
.1UF
C23
.1UF
+5
+5
C11
.1UF
C10
.1UF
P5
-5
+5
13
11
9
7
5
3
1
+
-5
+
+5
14
12
10
8
6
4
2
OnCE PORT
C12
2.2UF
C9
2.2UF
FIGURE 8. DEM-ADS7833 Top Silkscreen.
®
DEM-ADS7833
12
FIGURE 9. DEM-ADS7833 Interconnection (Top Layer).
®
13
DEM-ADS7833
FIGURE 10. DEM-ADS7833 Ground Plane (Inner Layer).
®
DEM-ADS7833
14
FIGURE 11. DEM-ADS7833 +5V and –5V Power Planes (Inner Layer).
®
15
DEM-ADS7833
FIGURE 12. DEM-ADS7833 Interconnection (Bottom Layer).
®
DEM-ADS7833
16
REF. DES.
QTY.
PART NUMBER
MANUFACTURER
C19
C2
C3
C6
C8
C10
C11
C13
C15
C17
C20
C21
C22
C23
C24
C25
C26
C27
C28
C1
C4
C5
C7
C9
C12
C14
C16
C18
D1
D2
D3
D4
D5
P1-DAC56
P1-V1-3
P1-V1-2
P1-V1-1
P1-AOUT
P1-V3-4
P1-V3-3
P1-V3-2
P1-V3-1
P1-V2-1
P1-V2-2
P1-V2-3
P1
P4
P4
P2
P3
P5
P6-LCD
P6
P6-LCD
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C0805C391K5GAC
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
C1206C104K5RAC7800
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
TAJA225K010
SMBJ5.0AGICT-ND
SMBJ5.0AGICT-ND
LT1075-ND
LT1075-ND
BAS16
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31165102
31024124
31165103
31024103
CSS-103-20
CSS-103-10
CSS-103-7
MTLW-107-06-G-D-130
SLW-107-01-G-D
DMC-24227N-B
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
KEMET
AVX
AVX
AVX
AVX
AVX
AVX
AVX
AVX
AVX
GI/Digi-Key
GI/Digi-Key
LITEON/Digi-Key
LITEON/Digi-Key
Philips
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
RIA Electronics
Components Corporation
Components Corporation
Components Corporation
Samtec
Samtec
Optrex
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
DESCRIPTION
390PF ±10% 50V NPO 0805 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
.1µF ±10% 50V X7R 1206 Ceramic Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
2.2µF ±10% 10V 3216 Tantalum Chip Capacitor
5.0V Transient Voltage Suppressors DO-214AA J-Bend
5.0V Transient Voltage Suppressors DO-214AA J-Bend
Orange LED SOT23
Orange LED SOT23
Small-Signal Diode SOT-23
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
2-Pin Term Block, 3.5mm Centers
24-Pin Header, 3.5mm Centers
3-Pin Term Block, 3.5mm Centers
3-Pin Header, 3.5mm Centers
Header 20 x 2, 2.54mm Centers
Header 10 x 2, 2.54mm Centers
Header 7 x 2, 2.54mm Centers, pin 8 removed
7 x 2 Header, 2.54mm Centers, install in LCD module
7 x 2 Socket, 2.54mm Centers
24 x 2 LCD Display Module
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
TABLE I. DEM-ADS7833 Parts List.
®
17
DEM-ADS7833
REF. DES.
QTY.
PART NUMBER
MANUFACTURER
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
SW1
SW2
SW3
SW4
SW5
SW6
SW7
TP1
U1
U4
U1
U2
U3
U7
U5
U9
U10
U11
U12
U6
U8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
4
4
4
1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-221JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
Not installed
CRCW0805-103JRT1
CRCW0805-221JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-103JRT1
CRCW0805-221JRT1
EVQ-PAC04M
EVQ-PAC04M
EVQ-PAC04M
EVQ-PAC04M
EVQ-PAC04M
EVQ-PAC04M
EG4208
TP-105-09-06
822280-1
AT27C256R-12JC
ADS7833N
OPA132U
DAC56U
OECS-480-1-A101A
IDT71256SA20Y
IDT74FCT574ATSO
IDT74FCT574ATSO
IDT74FCT573ATSO
IDT74FCT574ATSO
DSP56004FJ50
TC74ACT32FN
SJ-5003-0-ND
SS6978-0.250-01
0919-2
KFS2-256
A038B
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
E-Switch
Components Corporation
AMP
Atmel
Burr-Brown
Burr-Brown
Burr-Brown
ECS
IDT
IDT
IDT
IDT
IDT
Motorola
Toshiba
3M/Digi-Key
LYN-TRON
Crescent
PENN Engineering
Moore Printed Circuits
TABLE I. (Cont) DEM-ADS7833 Parts List.
®
DEM-ADS7833
18
DESCRIPTION
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
10kΩ 5% Thick Film 0805 Chip Resistor
220Ω 5% Thick Film 0805 Chip Resistor
Pushbutton Switch
Pushbutton Switch
Pushbutton Switch
Pushbutton Switch
Pushbutton Switch
Pushbutton Switch
Slide Switch
9 x 1 Test Points
68-Pin PLCC Surface Mount Socket
32K x 8 OTP EPROM PLCC32
ADC
Op-Amp SO8
16-Bit DAC SO16
48.000MHZ CMOS Crystal Oscillator DIP
32K x 8 SRAM 20nS SOJ28
8-Bit Latch SO20
8-Bit Latch SO20
8-Bit Latch SO20
8-Bit Latch SO20
50MHz DSP PQFP100
Quad OR Gate SO14
.44D" x .20H" Black Round Bumpons”
2-56 x .250" M/F 3/16 Hex SS Standoff”
2-56 x 3/16" SS Phillips Pan-Head Screw”
2-56 PCB Self-Cinching Nut
Printed Circuit Board