DG221 Quad SPST CMOS Analog Switch with Latches Features Benefits Applications Compatible with Most P Buses Allows Wide Power Supply Tolerance Without Affecting TTL Compatibility Reduced Power Consumption Allows Flexibility of Design Accepts 150-ns Write Pulse Width 5-V On-Chip Regulator Built on PLUS-40 Process Latches Are Transparent with WR Low Low On-Resistance: 60 P Based Systems Automatic Test Equipment Communication Systems Data Acquisition Systems Medical Instrumentation Factory Automation Description The DG221 is a monolithic quad single-pole, single-throw analog switch designed for precision switching applications in communication, instrumentation and process control systems. Featuring independent onboard latches and a common WR pin, each DG221 can be memory mapped, and addressed as a single data byte for simultaneous switching. Designed on the Siliconix PLUS-40 CMOS process, the DG221 combines low power and low on-resistance (60 typical) while handling continuous currents up to 20 mA. An epitaxial layer prevents latchup. The device features true bidirectional performance in the on condition. These switches guarantee a rail-to-rail blocking capability (44 V max), in the off condition. Functional Block Diagram and Pin Configuration Four Latchable SPST Switches per Package Dual-In-Line and SOIC 1 16 IN2 D1 2 15 D2 S1 3 14 S2 13 V+ 12 WR Input Latch IN1 V– 4 GND 5 S4 6 11 S3 D4 7 10 D3 IN4 8 IN3 Top View 0 0 ON 1 0 OFF Control data latched-in, switches on or off as selected by last INX X X 1 Maintains previous state Logic “0” 0.8 V Logic “1” 2.4 V Ordering Information Temp Range Package 0C to 70C 16-Pin Plastic DIP DG221CJ –40C to 85C 16-Pin Narrow SOIC DG221DY –55C to 125C 16-Pin CerDIP Part Number DG221AK/883 Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70041. Siliconix S-52881—Rev. C, 28-Apr-97 1 DG221 Absolute Maximum Ratings Voltages Referenced to V– V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . . 70 mA Storage Temperature: (AK Suffix) . . . . . . . . . . . . . . –65 to 150C (CJ and DY Suffix) . . . . . . . . –65 to 125C Power Dissipation (Package)b 16-Pin CerDIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 16-Pin Plastic DIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 16-Pin SOICe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 12 mW/C above 75C d. Derate 6.5 mW/C above 25C e. Derate 7.7 mW/C above 75C Schematic Diagram (Typical Channel) V+ 5V Reg S GND INX V– – + Latch V– V+ WR Level Shift/ Drive V+ – + D V– Figure 1. 2 Siliconix S-52881—Rev. C, 28-Apr-97 DG221 Specificationsa Test Conditions Unless Otherwise Specified Parameter Symbol V = 15 V, V V– V = –15 15 V V+ VIN = 2.4 V, 0.8f V, WR = 0 Tempb Typc A Suffix D Suffix –55 to 125C –40 to 85C Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee VANALOG Drain-Source On-Resistance rDS(on) Source Off Leakage Current IS(off) Drain Off Leakage Current ID(off) Drain On Leakage Current ID(on) IINL , IINH Full –15 15 –15 V 90 135 Room Full 60 Room Full "0.01 –1 –100 1 100 –5 –100 5 100 Room Full "0.02 –1 –100 1 100 –5 –100 5 100 VS = VD = "14 V Room Full "0.01 –1 –200 1 200 –5 –200 5 200 VIN = 0 V or = 2.4 V Room Full –0.0004 –1 –10 1 10 –1 –10 1 10 IS = –10 mA, VD = "10 V VS = "14 V V, VD = #14 V 90 135 15 nA Digital Control Input Current A Dynamic Characteristics Turn-On Time Room 550 550 Room 340 340 Room 550 550 tOFF, WR Room 340 340 Write Pulse Width tW Room 120 150 150 Input Setup Time tS Room 130 180 180 Input Hold Time tH Full 0 20 20 Charge Injection Q Room 20 Room 8 Room 9 Room 29 VS = 1 Vp-p p p, f = 100 kHz CL = 15 pF, F RL = 1 k Room 70 Room 90 All Channels On or Off VIN = 0 V or 22.4 4V Full 0.8 Room –0.4 Turn-Off Time Turn-On Time Write Turn-Off Time Write tON tOFF tON, WR Source-Off Capacitance CS(off) Drain-Off Capacitance CD(off) Channel-On Capacitance CD(on) Off Isolation OIRR Interchannel Crosstalk XTALK See Figure 2 See Figure 3 See Figure 4 CL = 1000 pF VGEN = 0 V, RGEN = 0 f = 1 MHz, VS, VD = 0 V ns pC pF dB Power Supplies Positive Supply Current I+ Negative Supply Current I– 1.5 –1 1.5 mA –1 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. Siliconix S-52881—Rev. C, 28-Apr-97 3 DG221 Test Circuits +15 V V+ 2V S D IN GND WR V– VO RL 1 k 3V Logic Input 50% Switch Input CL 35 pF tr < 10 ns tf < 10 ns 0V VS 90% Switch Output VO tON –15 V tOFF CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) Figure 2. Switching Time +15 V 3V 0V 2V WR S WR V+ D IN GND V– IN VO RL 1 k 50% 0V 3V tr < 10 ns tf < 10 ns 0V CL 35 pF VS VOUT –15 V tON, WR CL (includes fixture and stray capacitance) VO = VS 90% VO tOFF , WR RL RL + rDS(on) Figure 3. WR Switching Time 3V 50% IN tS tH tS tH 3V 50% WR tW tH = Hold Time tS = Setup Time tW = WR Pulse Width VOUT The latches are level sensitive. When WR is held low the latches are transparent and the switches respond to the digital inputs. The digital inputs are latched on the rising edge of WR. Figure 4. WR Setup Conditions 4 Siliconix S-52881—Rev. C, 28-Apr-97 DG221 Test Circuits (Cont’d) +15 V DVO V+ Rg S Vg VO D VO CL 1000 pF IN 3V WR INX OFF V– ON OFF DVO = measured voltage error due to charge injection The charge injection in coulombs is Q = CL x DVO –15 V Figure 5. Charge Injection +15 V +15 V C C V+ V+ S VS S1 VS VO D Rg = 50 W Rg = 50 W 2.4 V NC GND WR V– 50 W IN1 0V RL IN D1 C 0V S2 D2 VO RL IN2 GND WR V– C –15 V Off Isolation = 20 log –15 V VS VO C = RF bypass XTALK Isolation = 20 log C = RF bypass VS VO Figure 7. Channel-to-Channel Crosstalk Figure 6. Off Isolation Application Hintsa WR (V) VIN Logic Input Voltage VINH(min)/VINL(max) (V) VS or VD Analog Voltage Range (V) 0 2.4/0.8 2.4/0.8 –15 to 15 –20 0 2.4/0.8 2.4/0.8 –20 to 20 –10 0 2.4/0.8 2.4/0.8 –10 to 10 –5 0 2.4/0.8 2.4/0.8 –5 to 10 V+ Positive Supply Voltage (V) V– Negative Supply Voltage (V) GND (V) 15 –15 20 10 10 Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. Siliconix S-52881—Rev. C, 28-Apr-97 5 DG221 Applications VIN +15 V V+ 9 M DG221 IN1 D C S1 Q 900 k D1 S2 IN2 D C Q 90 k D2 Data Bus S3 IN3 D C Q 9 k D3 S4 IN4 D C WR Q 1 k D4 WR GND V– CS Address Decoder Address Bus + TL081 – –15 V The TL081 is used as an output buffer while the voltage divider provides attenuation. VO Figure 8. P-Controlled Analog Signal Attenuator Truth Table Output Attenuation for Figure 8 IN1 IN2 IN3 IN4 WRa 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 On Switch WR IN1 IN2 IN3 IN4 Gain All 0 0 1 1 1 0.1 0 None 0 1 0 1 1 0.01 0 1 0 1 1 0 1 0.001 1 0 2 0 1 1 1 0 0.0001 0 1 0 3 1 0 0 4 Notes: a. WR may be held at “0” for temporary operation similar to DG201A/DG201B. With WR at “0” SW1 will remain on as long as IN1 is held at “0”. 6 Siliconix S-52881—Rev. C, 28-Apr-97