LM6121/LM6221/LM6321 High Speed Buffer General Description Features These high speed unity gain buffers slew at 800 V/ms and have a small signal bandwidth of 50 MHz while driving a 50X load. They can drive g 300 mA peak and do not oscillate while driving large capacitive loads. The LM6121 family are monolithic ICs which offer performance similar to the LH0002 with the additional features of current limit and thermal shutdown. These buffers are built with National’s VIPTM (Vertically Integrated PNP) process which provides fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation. Y Y Y Y Y Y Y Y Y Y 800 V/ms 50 MHz g 300 mA 5 MX Applications Y Y Y Simplified Schematic High slew rate Wide bandwidth Slew rate and bandwidth 100% tested Peak output current High input impedance LH0002H pin compatible No oscillations with capacitive loads 5V to g 15V operation guaranteed Current and thermal limiting Fully specified to drive 50X lines Line Driving Radar Sonar Connection Diagrams Metal Can Plastic DIP TL/H/9223 – 2 *Heat-sinking pins. See Application section on heat sinking requirements. Order Number LM6221N, LM6321N or LM6121J/883 See NS Package Number J08A or N08E TL/H/9223 – 3 Top View Note: Pin 6 connected to case. Order Number LM6221H or LM6121H/883 See NS Package Number H08C Plastic SO TL/H/9223 – 1 Numbers in ( ) are for 8-pin N DIP. TL/H/9223 – 7 *Pin 3 must be connected to the negative supply. **Heat-sinking pins. See Application section on heat-sinking requirements. These pins are at Vb potential. Order Number LM6321M See NS Package Number M14A VIPTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/9223 RRD-B30M75/Printed in U. S. A. LM6121/LM6221/LM6321 High Speed Buffer December 1994 Absolute Maximum Ratings (Note 1) ESD Tolerance (Note 8) g 2000V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Junction Temperature (TJ(max)) Supply Voltage 36V ( g 18) Operating Ratings g 7V Operating Temperature Range LM6121H/883 LM6221 LM6321 Input to Output Voltage (Note 2) Input Voltage Output Short-Circuit to GND (Note 3) Storage Temperature Range g Vsupply Continuous 260§ C (Note 10) Power Dissipation b 55§ C to a 125§ C b 40§ C to a 85§ C 0§ C to a 70§ C 4.75 to g 16V Operating Supply Range Thermal Resistance (iJA), (Note 4) H Package N Package M Package b 65§ C to a 150§ C Lead Temperature (Soldering, 10 seconds) 150§ C 150§ C/W 47§ C/W 69§ C/W 17§ C/W Thermal Resistance (iJC), H Package DC Electrical Characteristics The following specifications apply for Supply Voltage e g 15V, VCM e 0, RL t 100 kX and RS e 50X unless otherwise noted. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. Symbol Parameter Conditions Typ LM6121 LM6221 LM6321 Limit (Notes 5, 9) Limit (Note 5) Limit (Note 5) Units AV1 Voltage Gain 1 RL e 1 kX, VIN e g 10V 0.990 0.980 0.970 0.980 0.950 0.970 0.950 AV2 Voltage Gain 2 RL e 50X, VIN e g 10V 0.900 0.860 0.800 0.860 0.820 0.850 0.820 AV3 Voltage Gain 3 (Note 6) RL e 50X, V a e 5V VIN e 2 Vpp (1.5 Vpp) 0.840 0.780 0.750 0.780 0.700 0.750 0.700 VOS Offset Voltage RL e 1 kX 15 30 50 30 60 50 100 mV Max IB Input Bias Current RL e 1 kX, RS e 10 kX 1 4 7 4 7 5 7 mA Max RIN Input Resistance RL e 50X CIN Input Capacitance RO Output Resistance IOUT e g 10 mA IS1 Supply Current 1 RL e % IS2 Supply Current 2 RL e % , V a e 5V VO1 Output Swing 1 VO2 5 V/V Min MX 3.5 pF 3 5 10 5 10 5 6 15 18 20 18 20 20 22 14 16 18 16 18 18 20 RL e 1k 13.5 13.3 13 13.3 13 13.2 13 Output Swing 2 RL e 100X 12.7 11.5 10 11.5 10 11 10 VO3 Output Swing 3 RL e 50X 12 11 9 11 9 10 9 VO4 Output Swing 4 RL e 50X, (Note 6) 1.8 1.6 1.3 1.6 1.4 1.6 1.5 VPP Min PSSR Power Supply Rejection Ratio V g e g 5V to g 15V 70 60 55 60 50 60 50 dB Min V a e 5V 2 X Max mA Max gV Min AC Electrical Characteristics The following specifications apply for Supply Voltage e g 15V, VCM e 0, RL t 100 kX and RS e 50X unless otherwise noted. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. Symbol Parameter Conditions LM6121 LM6221 LM6321 Typ Limit (Note 5) Limit (Note 5) Limit (Note 5) Units SR1 Slew Rate 1 VIN e g 11V, RL e 1 kX 1200 550 550 550 SR2 Slew Rate 2 VIN e g 11V, RL e 50X (Note 7) 800 550 550 550 SR3 Slew Rate 3 VIN e 2 VPP, RL e 50X V a e 5V (Note 6) 50 550 550 550 BW b 3 dB Bandwidth VIN e g 100 mVPP, RL e 50X CL s 10 pF 50 30 30 30 tr, tf Rise Time Fall Time RL e 50X, CL s 10 pF VO e 100 mVPP 7.0 ns tpd Propagation Delay Time RL e 50X, CL s 10 pF VO e 100 mVPP 4.0 ns OS Overshoot RL e 50X, CL s 10 pF VO e 100 mVPP 10 % V/ms Min MHz Min Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. Note 2: During current limit or thermal limit, the input current will increase if the input to output differential voltage exceeds 8V. For input to output differential voltages in excess of 8V the input current should be limited to g 20 mA. Note 3: The LM6121 series buffers contain current limit and thermal shutdown to protect against fault conditions. Note 4: The thermal resistance iJA of the device in the N package is measured when soldered directly to a printed circuit board, and the heat-sinking pins (pins 1, 4, 5 and 8) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal resistance iJA of the N package is 84§ C/W. The thermal resistance iJA of the device in the M package is measured when soldered directly to a printed circuit board, and the heat-sinking pins (pins 1, 2, 6, 7, 8, 9, 13, 14) are connected to 1 square inch of 2 oz. copper. Note 5: Limits are guaranteed by testing or correlation. Note 6: The input is biased to 2.5V and VIN swings Vpp about this value. The input swing is 2 Vpp at all temperatures except for the AV3 test at b 55§ C where it is reduced to 1.5 Vpp. Note 7: Slew rate is measured with a g 11V input pulse and 50X source impedance at 25§ C. Since voltage gain is typically 0.9 driving a 50X load, the output swing will be approximately g 10V. Slew rate is calculated for transitions between g 5V levels on both rising and falling edges. A high speed measurement is done to minimize device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to g 10V for measurements at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/ms. Note 8: The test circuit consists of the human body model of 120 pF in series with 1500X. Note 9: For specification limits over the full Military Temperature Range, see RETS6121X. Note 10: The maximum power dissipation is a function of TJ(max), iJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD e (TJ(max) –TA)/iJA. 3 Typical Performance Characteristics TJ e 25§ C, unless otherwise specified Frequency Response Frequency Response Slew Rate vs Temperature Overshoot vs Capacitive Load Large Signal Response RL e 1 kX Large Signal Response RL e 50X Supply Current b 3 dB Bandwidth Slew Rate Slew Rate Power Bandwidth TL/H/9223 – 4 4 Typical Performance Characteristics Input Return Gain (S11) TJ e 25§ C, unless otherwise specified (Continued) Forward Transmission Gain (S12) Current Limit TL/H/9223 – 5 Application Hints If the buffer’s input-to-output differential voltage is allowed to exceed 7V, a base-emitter junction will be in reversebreakdown, and will be in series with a forward-biased baseemitter junction. Referring to the LM6121 simplified schematic, the transistors involved are Q1 and Q3 for positive inputs, and Q2 and Q4 for negative inputs. If any current is allowed to flow through these junctions, localized heating of the reverse-biased junction will occur, potentially causing damage. The effect of the damage is typically increased offset voltage, increased bias current, and/or degraded AC performance. Furthermore, this will defeat the short-circuit and over-temperature protection circuitry. Exceeding g 7V input with a shorted output will destroy the device. The device is best protected by the insertion of the parallel combination of a 100 kX resistor (R1) and a small capacitor (C1) in series with the buffer input, and a 100 kX resistor (R2) from input to output of the buffer (see Figure 1 ). This network normally has no effect on the buffer output. However, if the buffer’s current limit or shutdown is activated, and the output has a ground-referred load of significantly less than 100 kX, a large input-to-output voltage may be present. R1 and R2 then form a voltage divider, keeping the input-output differential below the 7V Maximum Rating for input voltages up to 14V. This protection network should be sufficient to protect the LM6121 from the output of nearly any op amp which is operated on supply voltages of g 15V or lower. POWER SUPPLY DECOUPLING The method of supply bypassing is not critical for stability of the LM6121 series buffers. However, their high current output combined with high slew rate can result in significant voltage transients on the power supply lines if much inductance is present. For example, a slew rate of 900 V/ms into a 50X load produces a di/dt of 18 A/ms. Multiplying this by a wiring inductance of 50 nH (which corresponds to approximately 1(/2× of 22 gauge wire) result in a 0.9V transient. To minimize this problem use high quality decoupling very close to the device. Suggested values are a 0.1 mF ceramic in parallel with one or two 2.2 mF tantalums. A ground plane is recommended. LOAD IMPEDANCE The LM6121 is stable to any load when driven by a 50X source. As shown in the Overshoot vs Capacitive Load graph, worst case is a purely capacitive load of about 1000 pF. Shunting the load capacitance with a resistor will reduce overshoot. SOURCE INDUCTANCE Like any high frequency buffer, the LM6121 can oscillate at high values of source inductance. The worst case condition occurs at a purely capacitive load of 50 pF where up to 100 nH of source inductance can be tolerated. With a 50X load, this goes up to 200 nH. This sensitivity may be reduced at the expense of a slight reduction in bandwidth by adding a resistor in series with the buffer input. A 100X resistor will ensure stability with source inductances up to 400 nH with any load. OVERVOLTAGE PROTECTION The LM6121 may be severely damaged or destroyed if the Absolute Maximum Rating of 7V between input and output pins is exceeded. TL/H/9223 – 6 FIGURE 1. LM6121 with Overvoltage Protection 5 Application Hints Figure 3 shows copper patterns which may be used to dissipate heat from the LM6321. HEATSINK REQUIREMENTS A heatsink may be required with the LM6321 depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible operating conditions, the junction temperature must be within the range specified under Absolute Maximum Ratings. To determine if a heatsink is required, the maximum power dissipated by the buffer, P(max), must be calculated. The formula for calculating the maximum allowable power dissipation in any application is PD e (TJ(max)bTA)/iJA. For the simple case of a buffer driving a resistive load as in Figure 2 , the maximum DC power dissipation occurs when the output is at half the supply. Assuming equal supplies, the formula is PD e IS (2V a ) a V a 2/2 RL. 8-Pin DIP TL/H/9223 – 9 14-Pin SO TL/H/9223–8 TL/H/9223 – 10 FIGURE 2 *For best results, use L e 2H FIGURE 3. Copper Heatsink Patterns Table II shows some values of junction-to-ambient thermal resistance (iJ – A) for values of L and W for 2 oz. copper: The next parameter which must be calculated is the maximum allowable temperature rise, TR(max). This is calculated by using the formula: TR(max) e TJ(max) b TA(max) TABLE II where: TJ(max) is the maximum allowable junction temperature TA(max) is the maximum ambient temperature Using the calculated values for TR(max) and P(max), the required value for junction-to-ambient thermal resistance, i(J–A), can now be found: i(J – A) e TR(max)/P(max) The heatsink for the LM6321 is made using the PC board copper. The heat is conducted from the die, through the lead frame (inside the part), and out the pins which are soldered to the PC board. The pins used for heat conduction are: TABLE I Part Package Pins LM6321N 8-Pin DIP 1, 4, 5, 8 LM6321M 14-Pin SO 1, 2, 3, 6, 7, 8, 9, 13, 14 6 Package L (in.) H (in.) iJ – A (§ C/W) 8-Pin DIP 2 0.5 47 14-Pin SO 1 0.5 69 2 1 57 7 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LM6221H or LM6121H/883 NS Package Number H08C 8-Pin Ceramic Dual-In-Line Package (J) Order Number LM6121J/883 NS Package Number J08A 8 Physical Dimensions inches (millimeters) (Continued) 14-Pin Small Outline Package (M) Order Number LM6321M NS Package Number M14A 9 LM6121/LM6221/LM6321 High Speed Buffer Physical Dimensions inches (millimeters) (Continued) Lit. Ý108239 Molded Dual-In-Line Package (N) Order Number LM6221N or LM6321N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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