LM6121/LM6221/LM6321 High Speed Buffer General Description Features These high speed unity gain buffers slew at 800 V/µs and have a small signal bandwidth of 50 MHz while driving a 50Ω load. They can drive ± 300 mA peak and do not oscillate while driving large capacitive loads. The LM6121 family are monolithic ICs which offer performance similar to the LH0002 with the additional features of current limit and thermal shutdown. These buffers are built with National’s VIP™ (Vertically Integrated PNP) process which provides fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation. n n n n n n n n n n High slew rate: 800 V/µs Wide bandwidth: 50 MHz Slew rate and bandwidth 100% tested Peak output current: ± 300 mA High input impedance: 5 MΩ LH0002H pin compatible No oscillations with capacitive loads 5V to ± 15V operation guaranteed Current and thermal limiting Fully specified to drive 50Ω lines Applications n Line Driving n Radar n Sonar Simplified Schematic 00922301 Numbers in ( ) are for 8-pin N DIP. VIP™ is a trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS009223 www.national.com LM6121/LM6221/LM6321 High Speed Buffer March 2004 LM6121/LM6221/LM6321 Connection Diagrams Plastic DIP 00922302 *Heat-sinking pins. See Application section on heat sinking requirements. Order Number LM6221N, LM6321N or LM6121J/883 See NS Package Number J08A or N08E Metal Can 00922303 Note: Pin 6 connected to case. Top View Order Number LM6221H or LM6121H/883 See NS Package Number H08C Plastic SOIC 00922307 *Pin 3 must be connected to the negative supply. **Heat-sinking pins. See Application section on heat-sinking requirements. These pins are at V− potential. Order Number LM6321M See NS Package Number M14A www.national.com 2 Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Range LM6121H/883 36V ( ± 18) Supply Voltage Output Short-Circuit to GND Thermal Resistance (θJA), (Note 4) Continuous H Package (Note 3) Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 10 seconds) 150˚C/W N Package 47˚C/W M Package 69˚C/W Thermal Resistance (θJC), H Package 260˚C Power Dissipation 0˚C to +70˚C 4.75 to ± 16V Operating Supply Range ± Vsupply Input Voltage −40˚C to +85˚C LM6321 ± 7V Input to Output Voltage (Note 2) −55˚C to +125˚C LM6221 17˚C/W (Note 10) ESD Tolerance (Note 8) ± 2000V Junction Temperature (TJ(MAX)) +150˚C DC Electrical Characteristics The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ≥ 100 kΩ and RS = 50Ω unless otherwise noted. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol AV1 AV2 AV3 Parameter Voltage Gain 1 Voltage Gain 2 Conditions RL = 1 kΩ, VIN Typ = ± 10V 0.990 RL = 50Ω, VIN = ± 10V 0.900 + Voltage Gain 3 RL = 50Ω, (Note 6) VIN = 2 Vpp (1.5 Vpp) VOS Offset Voltage RL = 1 kΩ 15 IB Input Bias Current RL = 1 kΩ, RS = 10 kΩ 1 RIN Input Resistance CIN Input Capacitance RO Output Resistance IS1 Supply Current 1 V = 5V 0.840 RL = 50Ω LM6121 LM6221 LM6321 Limit Limit Limit (Notes 5, 9) (Note 5) (Note 5) 0.980 0.980 0.970 0.970 0.950 0.950 0.860 0.860 0.850 V/V 0.800 0.820 0.820 Min 0.780 0.780 0.750 0.750 0.700 0.700 30 30 50 mV 50 60 100 Max 4 4 5 µA 7 7 7 Max 5 MΩ 3.5 IOUT = ± 10 mA pF 5 5 5 Ω 10 10 6 Max 18 18 20 20 20 22 mA Max 14 16 16 18 3 RL = ∞ Units 15 IS2 Supply Current 2 RL = ∞, V+ = 5V 18 18 20 VO1 Output Swing 1 RL = 1k 13.5 13.3 13.3 13.2 13 13 13 VO2 Output Swing 2 RL = 100Ω 12.7 11.5 11.5 11 ±V 10 10 10 Min VO3 Output Swing 3 RL = 50Ω 12 11 11 10 9 9 9 VO4 Output Swing 4 RL = 50Ω, + V = 5V 1.8 (Note 6) PSSR Power Supply V± = ± 5V to ± 15V 70 Rejection Ratio 3 1.6 1.6 1.6 VPP 1.3 1.4 1.5 Min 60 60 60 dB 55 50 50 Min www.national.com LM6121/LM6221/LM6321 Absolute Maximum Ratings (Note 1) LM6121/LM6221/LM6321 AC Electrical Characteristics The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ≥ 100 kΩ and RS = 50Ω unless otherwise noted. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter SR1 Slew Rate 1 SR2 Slew Rate 2 Conditions Typ LM6121 LM6221 LM6321 Limit Limit Limit (Note 5) (Note 5) (Note 5) VIN = ± 11V, RL = 1 kΩ 1200 550 550 550 VIN = ± 11V, RL = 50Ω 800 550 550 550 50 550 550 550 50 30 30 30 Units V/µs Min (Note 7) SR3 Slew Rate 3 VIN = 2 VPP, RL = 50Ω + V = 5V (Note 6) BW −3 dB Bandwidth VIN = ± 100 mVPP, RL = 50Ω CL ≤ 10 pF t r , tf tpd OS Rise Time RL = 50Ω, CL ≤ 10 pF Fall Time VO = 100 mVPP Propagation RL = 50Ω, CL ≤ 10 pF Delay Time VO = 100 mVPP Overshoot MHz Min RL = 50Ω, CL ≤ 10 pF 7.0 ns 4.0 ns 10 % VO = 100 mVPP Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. Note 2: During current limit or thermal limit, the input current will increase if the input to output differential voltage exceeds 8V. For input to output differential voltages in excess of 8V the input current should be limited to ± 20 mA. Note 3: The LM6121 series buffers contain current limit and thermal shutdown to protect against fault conditions. Note 4: The thermal resistance θJA of the device in the N package is measured when soldered directly to a printed circuit board, and the heat-sinking pins (pins 1, 4, 5 and 8) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal resistance θJA of the N package is 84˚C/W. The thermal resistance θJA of the device in the M package is measured when soldered directly to a printed circuit board, and the heat-sinking pins (pins 1, 2, 6, 7, 8, 9, 13, 14) are connected to 1 square inch of 2 oz. copper. Note 5: Limits are guaranteed by testing or correlation. Note 6: The input is biased to 2.5V and VIN swings VPP about this value. The input swing is 2 VPP at all temperatures except for the AV 3 test at −55˚C where it is reduced to 1.5 VPP. Note 7: Slew rate is measured with a ± 11V input pulse and 50Ω source impedance at 25˚C. Since voltage gain is typically 0.9 driving a 50Ω load, the output swing will be approximately ± 10V. Slew rate is calculated for transitions between ± 5V levels on both rising and falling edges. A high speed measurement is done to minimize device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to ± 10V for measurements at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/µs. Note 8: The test circuit consists of the human body model of 120 pF in series with 1500Ω. Note 9: For specification limits over the full Military Temperature Range, see RETS6121X. Note 10: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)–TA)/θJA. www.national.com 4 LM6121/LM6221/LM6321 Typical Performance Characteristics TJ = 25˚C, unless otherwise specified Frequency Response Frequency Response 00922311 00922312 Slew Rate vs Temperature Overshoot vs Capacitive Load 00922313 00922314 Large Signal Response RL = 50Ω Large Signal Response RL = 1 kΩ 00922315 00922316 5 www.national.com LM6121/LM6221/LM6321 Typical Performance Characteristics TJ = 25˚C, unless otherwise specified Supply Current (Continued) −3 dB Bandwidth 00922317 00922318 Slew Rate Slew Rate 00922319 00922320 Power Bandwidth Input Return Gain (S11) 00922321 www.national.com 00922322 6 Forward Transmission Gain (S12) (Continued) Current Limit 00922323 00922324 inputs, and Q2 and Q4 for negative inputs. If any current is allowed to flow through these junctions, localized heating of the reverse-biased junction will occur, potentially causing damage. The effect of the damage is typically increased offset voltage, increased bias current, and/or degraded AC performance. Furthermore, this will defeat the short-circuit and over-temperature protection circuitry. Exceeding ± 7V input with a shorted output will destroy the device. The device is best protected by the insertion of the parallel combination of a 100 kΩ resistor (R1) and a small capacitor (C1) in series with the buffer input, and a 100 kΩ resistor (R2) from input to output of the buffer (see Figure 1). This network normally has no effect on the buffer output. However, if the buffer’s current limit or shutdown is activated, and the output has a ground-referred load of significantly less than 100 kΩ, a large input-to-output voltage may be present. R1 and R2 then form a voltage divider, keeping the inputoutput differential below the 7V Maximum Rating for input voltages up to 14V. This protection network should be sufficient to protect the LM6121 from the output of nearly any op amp which is operated on supply voltages of ± 15V or lower. Application Hints POWER SUPPLY DECOUPLING The method of supply bypassing is not critical for stability of the LM6121 series buffers. However, their high current output combined with high slew rate can result in significant voltage transients on the power supply lines if much inductance is present. For example, a slew rate of 900 V/µs into a 50Ω load produces a di/dt of 18 A/µs. Multiplying this by a wiring inductance of 50 nH (which corresponds to approximately 11⁄2" of 22 gauge wire) result in a 0.9V transient. To minimize this problem use high quality decoupling very close to the device. Suggested values are a 0.1 µF ceramic in parallel with one or two 2.2 µF tantalums. A ground plane is recommended. LOAD IMPEDANCE The LM6121 is stable source. As shown in graph, worst case is 1000 pF. Shunting the reduce overshoot. LM6121/LM6221/LM6321 Typical Performance Characteristics TJ = 25˚C, unless otherwise specified to any load when driven by a 50Ω the Overshoot vs Capacitive Load a purely capacitive load of about load capacitance with a resistor will SOURCE INDUCTANCE Like any high frequency buffer, the LM6121 can oscillate at high values of source inductance. The worst case condition occurs at a purely capacitive load of 50 pF where up to 100 nH of source inductance can be tolerated. With a 50Ω load, this goes up to 200 nH. This sensitivity may be reduced at the expense of a slight reduction in bandwidth by adding a resistor in series with the buffer input. A 100Ω resistor will ensure stability with source inductances up to 400 nH with any load. FIGURE 1. LM6121 with Overvoltage Protection OVERVOLTAGE PROTECTION The LM6121 may be severely damaged or destroyed if the Absolute Maximum Rating of 7V between input and output pins is exceeded. If the buffer’s input-to-output differential voltage is allowed to exceed 7V, a base-emitter junction will be in reversebreakdown, and will be in series with a forward-biased baseemitter junction. Referring to the LM6121 simplified schematic, the transistors involved are Q1 and Q3 for positive HEATSINK REQUIREMENTS A heatsink may be required with the LM6321 depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible operating conditions, the junction temperature must be within the range specified under Absolute Maximum Ratings. To determine if a heatsink is required, the maximum power dissipated by the buffer, P(max), must be calculated. The formula for calculating the maximum allowable power dissi- 00922306 7 www.national.com LM6121/LM6221/LM6321 Application Hints TR(max) = TJ(max) − TA(max) where: TJ(max) is the maximum allowable junction temperature TA(max) is the maximum ambient temperature (Continued) pation in any application is PD = (TJ(max)−TA)/θJA. For the simple case of a buffer driving a resistive load as in Figure 2, the maximum DC power dissipation occurs when the output is at half the supply. Assuming equal supplies, the formula is PD = IS (2V+) + V+2/4 RL. Using the calculated values for TR(max) and P(max), the required value for junction-to-ambient thermal resistance, θ(J–A), can now be found: θ(J–A) = TR(max)/P(max) The heatsink for the LM6321 is made using the PC board copper. The heat is conducted from the die, through the lead frame (inside the part), and out the pins which are soldered to the PC board. The pins used for heat conduction are: TABLE 1. 00922308 FIGURE 2. Part Package Pins LM6321N 8-Pin DIP 1, 4, 5, 8 LM6321M 14-Pin SO 1, 2, 3, 6, 7, 8, 9, 13, 14 The next parameter which must be calculated is the maximum allowable temperature rise, TR(max). This is calculated by using the formula: Figure 3 shows copper patterns which may be used to dissipate heat from the LM6321. 8-Pin DIP 00922309 14-Pin SOIC 00922310 *For best results, use L = 2H FIGURE 3. Copper Heatsink Patterns TABLE 2. L (in.) H (in.) θJA (˚C/W) 8-Pin DIP 2 0.5 47 14-Pin SO 1 0.5 69 2 1 57 Package Table 2 shows some values of junction-to-ambient thermal resistance (θJA) for values of L and W for 2 oz. copper: www.national.com 8 LM6121/LM6221/LM6321 Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LM6221H or LM6121H/883 NS Package Number H08C 8-Pin Ceramic Dual-In-Line Package (J) Order Number LM6121J/883 NS Package Number J08A 9 www.national.com LM6121/LM6221/LM6321 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Pin Small Outline Package (M) Order Number LM6321M NS Package Number M14A Molded Dual-In-Line Package (N) Order Number LM6221N or LM6321N NS Package Number N08E www.national.com 10 LM6121/LM6221/LM6321 High Speed Buffer Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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