HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Package Dimensions DESCRIPTION SEATING PLANE The HCPL-0600/0601optocouplers consist of a 870 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10 kV/µs. 0.164 (4.16) 0.144 (3.66) Pin 1 0.010 (0.25) 0.006 (0.16) 0.143 (3.63) 0.123 (3.13) FEATURES 0.244 (6.19) 0.224 (5.69) 0.008 (0.20) 0.003 (0.08) 0.021 (0.53) 0.011 (0.28) • • • • • • • • 0.019 [0.48] 0.202 (5.13) 0.182 (4.63) 0.050 (1.27) TYP Lead Coplanarity : 0.004 (0.10) MAX Compact SO8 package Very high speed-10 MBit/s Superior CMR-10 kV/µs Fan-out of 8 over -40°C to +85°C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E90700) NOTE All dimensions are in inches (millimeters) N/C 1 + 2 8 VCC 7 VE V F APPLICATIONS • • • • • • • _ Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface 3 N/C 4 6 VO 5 GND Single-channel circuit drawing TRUTH TABLE (Positive Logic) Input Enable Output H H L L H H H L H L L H H NC L L NC H A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1) 2001 Fairchild Semiconductor Corporation DS300397 4/30/01 1 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C) Parameter Symbol Value Units Storage Temperature TSTG -55 to +125 °C Operating Temperature TOPR -40 to +85 °C Lead Solder Temperature TSOL 260 for 10 sec °C IF 50 mA VE 5.5 V Reverse Input Voltage VR 5.0 V Power Dissipation PI 45 mW VCC (1 minute max) 7.0 V EMITTER DC/Average Forward Input Current Enable Input Voltage Not to exceed VCC by more than 500 mV DETECTOR Supply Voltage Output Current IO 50 mA Output Voltage VO 7.0 V Collector Output Power Dissipation PO 85 mW RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Units IFL 0 250 µA Input Current, High Level IFH *6.3 15 mA Supply Voltage, Output VCC 4.5 5.5 V Input Current, Low Level Enable Voltage, Low Level VEL 0 0.8 V Enable Voltage, High Level VEH 2.0 VCC V Operating Temperature TA -40 +85 °C Fan Out (TTL load) N 8 * 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less www.fairchildsemi.com 2 OF 11 4/30/01 DS300397 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.) INDIVIDUAL COMPONENT CHARACTERISTICS Parameter EMITTER Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Input Diode Temperature Coefficient DETECTOR High Level Supply Current Test Conditions (IF = 10 mA) TA =25°C (IR = 10 µA) (VF = 0, f = 1 MHz) (IF = 10 mA) Low Level Supply Current Low Level Enable Current High Level Enable Current High Level Enable Voltage Low Level Enable Voltage (VCC Output Rise Time (10-90%) Output Fall Time (90-10%) Enable Propagation Delay Time to Output High Level Enable Propagation Delay Time to Output Low Level Min 1.3 1.4 5.0 VF BVR CIN VF/TA (VCC = 5.5 V, IF = 0 mA) (VE = 0.5 V) (VCC = 5.5 V, IF = 10 mA) (VE = 0.5 V) (VCC = 5.5 V, VE = 0.5 V) (VCC = 5.5 V, VE = 2.0 V) (VCC = 5.5 V, IF = 10 mA) = 5.5 V, IF = 10 mA) (Note 2) SWITCHING CHARACTERISTICS AC Characteristics Propagation Delay Time to Output High Level Propagation Delay Time to Output Low Level Pulse Width Distortion Symbol Unit V V pF mV/°C ICCH 7 10 mA ICCL 9 13 mA IEL IEH VEH VEL -0.8 -0.6 -1.6 -1.6 mA mA V V 2.0 0.8 (TA = -40°C to +85°C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.) Test Conditions (Note 3) (TA =25°C) (RL = 350 1, CL = 15 pF) (Fig. 12) (Note 4) (TA =25°C) (RL = 350 1, CL = 15 pF) (Fig. 12) (RL = 350 1, CL = 15 pF) (Fig. 12) (RL = 350 1, CL = 15 pF) (Note 5) (Fig. 12) (RL = 350 1, CL = 15 pF) (Note 6) (Fig. 12) (IF = 7.5 mA, VEH = 3.5 V) (RL = 350 1, CL = 15 pF) (Note 7) (Fig. 13) (IF = 7.5 mA, VEH = 3.5 V) (RL = 350 1, CL = 15 pF) (Note 8) (Fig. 13) Device Symbol Min 20 Typ 45 All TPLH All TPHL 25 TPHL-TPLH 45 100 3 All All tr 50 ns All tf 12 ns All tELH 20 ns All tEHL 20 ns CMH Common Mode (RL = 350 1) (TA =25°C) Transient Immunity (IF = 7.5 mA, VOL (Max.) = 0.8 V) (at Output Low Level) (Note 10)(Fig. 14) CML 4/30/01 Max 1.8 1.75 60 -1.4 Common Mode (RL = 350 1) (TA =25°C) VCM = 10 V HCPL-0600 Transient Immunity (IF = 0 mA, VOH (Min.) = 2.0 V) (at Output High Level) (Note 9)(Fig. 14) VCM = 50 V HCPL-0601 DS300397 Typ** — 3 OF 11 Unit 35 ns ns ns 10,000 5000 VCM = 10 V HCPL-0600 VCM = 50 V HCPL-0601 Max 75 100 75 10,000 V/µs 10,000 5000 10,000 V/µs www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.) DC Characteristics Test Conditions High Level Output Current Low Level Output Voltage Symbol (VCC = 5.5 V, VO = 5.5 V) Typ** IOH (IF = 250 µA, VE = 2.0 V) (Note 2) (VCC = 5.5 V, IF = 5 mA) (VE = 2.0 V, IOL = 13 mA) (Note 2) Input Threshold Current Min (VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA) Max Unit 100 µA VOL .35 0.6 V IFT 3 5 mA Typ** Max Unit 1.0* µA ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.) Characteristics Test Conditions Symbol Min (Relative humidity = 45%) Input-Output Insulation Leakage Current (TA = 25°C, t = 5 s) (VI-O = 3000 VDC) II-O (Note 11) Withstand Insulation Test Voltage Resistance (Input to Output) Capacitance (Input to Output) (RH < 50%, TA = 25°C) (Note 11) ( t = 1 min.) VISO 2500 VRMS (VI-O = 500 V) (Note 11) RI-O 1012 1 (f = 1 MHz) (Note 11) CI-O 0.6 pF ** All typical values are at VCC = 5 V, TA = 25°C NOTES 1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 3. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse. 6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse. 7. tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 8. tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 9. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs). 10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs). 11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together. www.fairchildsemi.com 4 OF 11 4/30/01 DS300397 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Fig. 1 Forward Current vs. Input Forward Voltage Fig. 2 Output Voltage vs. Forward Current 1000 6 Vcc = 5 V TA = 25 ˚C IF - FORWARD CURRENT (mA) TA = 25˚C 5 Vo - OUTPUT VOLTAGE (V) 100 10 1 0.1 4 3 2 1 0.01 1.100 0 1.200 1.300 1.400 1.500 1.600 0 1 VF - FORWARD VOLTAGE (V) IOH - HIGH LEVEL OUTPUT CURRENT (µA) ITH - INPUT THRESHOLD CURRENT (mA) VCC = 5.0 V VO = 0.6 V 5 RL = 350 Ω 3 2 RL = 1 kΩ 1 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE (˚C) DS300397 4/30/01 4 5 6 Fig. 4 High Level Output Current vs. Temperature Fig. 3 Input Threshold Current vs. Temperature 0 -60 3 IF - FORWARD INPUT CURRENT (mA) 6 4 2 8 6 4 VCC = 5.5 V VO = 5.5 V VE = 2.0 V IF = 250 µA 2 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE (˚C) 5 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Fig. 5 Low Level Output Voltage vs. Temperature Fig. 6 Low Level Output Current vs. Temperature 0.7 IOL - LOW LEVEL OUTPUT CURRENT (mA) VOL - LOW LEVEL OUTPUT VOLTAGE (V) 0.8 VCC = 5.5 V VE = 2.0 V IF = 5.0 mA 0.6 IO = 12.8 mA 0.5 IO = 16 mA 0.4 0.3 0.2 IO = 9.6 mA IO = 6.4 mA 0.1 0.0 -60 -40 -20 0 20 40 60 80 70 VCC = 5.0 V VE = 2.0 V VOL = 0.6 V 60 IF = 10-15 mA 50 40 30 IF = 5 mA 20 -60 100 -40 -20 TA - TEMPERATURE (˚C) Fig. 7 Propagation Delay vs. Temperature 20 40 60 80 100 Fig. 8 Propagation Delay vs. Pulse Input Current 120 100 TP - PROPAGATION DELAY (ns) tPLH, RL = 1 kΩ VCC = 5.0 V IF = 7.5 mA TP - PROPAGATION DELAY (ns) 0 TA - TEMPERATURE (˚C) 80 tPHL, RL = 350 Ω, 1 kΩ 60 40 tPLH, RL = 350 Ω 20 VCC = 5.0 V TA = 25˚C 105 tPLH, RL = 1 kΩ 90 75 tPLH, RL = 350 Ω 60 45 tPHL, RL = 350 Ω, 1 kΩ 0 -60 30 -40 -20 0 20 40 60 80 100 www.fairchildsemi.com 5 7 9 11 13 15 IF - PULSE INPUT CURRENT (mA) TA - TEMPERATURE (˚C) 6 OF 11 4/30/01 DS300397 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Fig. 9 Typical Enable Propagation Delay vs. Temparature Fig. 10 Typical Rise and Fall Time vs. Temperature 180 Vcc = 5.0 V VEH= 3.0 V VEL = 0 V IF = 7.5 mA 60 tELH, RL = 1 kΩ tELH, RL = 350 Ω 30 tEHL, RL = 350 Ω, 1 kΩ 0 -60 -40 Vcc = 5.0 V IF = 7.5 mA 160 tr, tf - RISE, FALL TIME (ns) tE - ENABLE PROPAGATION DELAY (ns) 90 -20 0 20 140 RL = 1 kΩ tRISE 120 tFall 100 RL = 350 Ω 80 60 40 RL = 350 Ω, 1 kΩ 20 40 60 80 0 -60 100 -40 -20 TA - TEMPERATURE (˚C) 0 20 40 60 80 100 TA - TEMPERATURE (˚C) Fig. 11 Typical Pulse Width Distortion vs. Temperature PWD - PULSE WIDTH DISTORTION (ns) 40 30 RL = 1 kΩ Vcc = 5.0 V IF = 7.5 mA 20 RL = 350 Ω 10 0 -10 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE (˚C) DS300397 4/30/01 7 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Pulse Generator tr = 5ns Z O = 50 1 +5V I F = 7.5 mA 1 VCC I F = 3.75 mA Input (I F) 8 t PHL 2 Input Monitor (I F) 7 .1 Ef bypass RL Output (VO ) 6 3 CL 471 4 GND tPLH Output (VO ) 1.5 V 90% Output (VO ) 10% 5 tf tr Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf. Pulse Generator tr = 5ns Z O = 50 1 Input Monitor (V E) +5V 3.0 V Input (VE ) VCC 1 8 1.5 V t EHL 7.5 mA 7 2 .1 Ef bypass RL 1.5 V Output (VO ) 6 3 tELH Output (VO ) CL 4 GND 5 Fig. 13 Test Circuit tEHL and tELH. www.fairchildsemi.com 8 OF 11 4/30/01 DS300397 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 VCC IF A 1 8 2 7 3 6 +5V .1 Ef bypass 350 1 B VFF 4 GND Output (VO) 5 VCM Pulse Gen Peak VCM 0V CM H 5V Switching Pos. (A), I F= 0 VO VO (Min) VO (Max) VO 0.5 V Switching Pos. (B), I F= 7.5 mA CM L Fig. 14 Test Circuit Common Mode Transient Immunity DS300397 4/30/01 9 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 ORDERING INFORMATION Option Order Entry Identifier Description R1 .R1 Tape and Reel (500 per Reel) R2 .R2 Tape and Reel (2500 per Reel) Carrier Tape Specifications 8.0 ± 0.1 3.5 ± 0.2 2 ± 0.05 0.3 MAX 4.0 ± 0.1 Ø1.5 MIN 1.75 ± 0.10 5.5 ± 0.05 12.0 ± 0.3 8.3 ± 0.1 5.2 ± 0.2 0.1 MAX 6.4 ± 0.2 Ø1.5 + 0.1/-0 User Direction of Feed www.fairchildsemi.com 10 OF 11 4/30/01 DS300397 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in labeling, can be reasonably expected to result in a significant injury of the user. DS300397 4/30/01 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 11 OF 11 www.fairchildsemi.com