FAIRCHILD FOD063L

FOD060L, FOD260L, FOD063L
LVTTL/LVCMOS 3.3V High Speed-10 MBit/s
Logic Gate Optocouplers
Single Channel: FOD060L, FOD260L
Dual Channel: FOD063L
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■
■
■
Features
■
■
■
■
■
■
■
■
■
Compact SO8 package (except FOD260L – 8-pin DIP)
Very high speed – 10 MBit/s
Superior CMR — 50 kV/µs at 2,000V peak
Fan-out of 8 over -40°C to +85°C
Logic gate output
Strobable output (single channel devices)
Wired OR-open collector
U.L. recognized (File # E90700) (pending)
UDE approval pending
Data multiplexing
Switching power supplies
Pulse transformer replacement
Computer-peripheral interface
Description
These optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate.
Single channel devices include a strobable output. This output
features an open collector, thereby permitting wired OR outputs.
The output consists of bipolar transistors in a Bi-CMOS process
for reduced power consumption. The coupled parameters are
guaranteed over the temperature range of -40°C to +85°C. A
maximum input signal of 5 mA (3 mA for the FODX6XL versions) will provide a minimum output sink current of 13 mA (fan
out of 8). An internal noise shield provides superior common
mode rejection of typically 50 kV/µs at 2,000V common mode.
Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
Package
N/C 1
8
8 VCC
+ 1
8 VCC
V
F1
1
+ 2
7 VE
_ 2
6 VO
_
7 V01
VF
_
3
3
6 V02
VF2
8
8
1
N/C 4
5 GND
+ 4
5 GND
1
Single-channel circuit drawing
(FOD060L, FOD260L)
Dual-channel circuit drawing
(FOD063L)
Truth Table (Positive Logic)
Input
Enable
Output
H
L
H
L
H*
L*
H
H
L
L
NC*
NC*
L
H
H
H
L*
H*
*Dual channel devices or single channel devices with pin 7 not connected.
A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
©2005 Fairchild Semiconductor Corporation
FOD060L, FOD260L, FOD063L Rev. 1.0.0
1
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
June 2005
Parameter
Symbol
Value
Units
Storage Temperature
TSTG
-40 to +125
°C
Operating Temperature
TOPR
-40 to +85
°C
IF
50
mA
VE
VCC + 0.5V
V
VR
5.0
V
PI
45
mW
VCC
(1 minute max)
7.0
V
EMITTER
DC/Average Forward Input Current (each channel)
Enable Input Voltage
Not to exceed VCC by more than 500 mV
Single Channel
Reverse Input Voltage (each channel)
Power Dissipation
Single Channel
Dual Channel
DETECTOR
Supply Voltage
Output Current (each channel)
IO
50
mA
Output Voltage (each channel)
VO
7.0
V
PO
85
mW
Collector Output Power Dissipation
Single Channel
Dual Channel
Recommended Operating Conditions
Parameter
Symbol
Min
Max
Units
IFL
0
250
µA
Input Current, High Level
IFH
*6.3
15
mA
Supply Voltage, Output
VCC
2.7
3.3
V
Input Current, Low Level
Enable Voltage, Low Level (Single Channel)
VEL
0
0.8
V
Enable Voltage, High Level (Single Channel)
VEH
2.0
VCC
V
-40
+85
°C
Operating Temperature
TA
Fan Out (TTL load)
N
Output Pull-up Resistor
RL
8
330
4K
Ω
*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or less.
2
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings (No derating required up to 85°C)
Parameter
Test Conditions Symbol Min Typ** Max Unit
EMITTER
(IF = 10 mA)
Input Forward Voltage
VF
Input Reverse Breakdown Voltage
Input Capacitance
DETECTOR
(IR = 10 µA)
BVR
CIN
(IF = 10 mA)
(VE = 0.5 V)
Single Channel
High Level Supply Current
(IF = 0 mA, VCC = 3.3 V)
Dual Channel
Low Level Supply Current
(VE = 0.5 V)
Single Channel
Low Level Enable Current
(IF = 10 mA, VCC = 3.3 V)
Dual Channel
(VCC = 3.3 V, VE = 0.5 V)
Single Channel
V
1.75
(VF = 0, f = 1 MHz)
Input Diode Temperature Coefficient
5.0
V
pF
∆VF/∆TA
mV/°C
ICCH
7
mA
10
ICCL
10
IEL
-1.6
mA
mA
-1.6
mA
15
High Level Enable Current
(VCC = 3.3 V, VE = 2.0 V)
Single Channel
IEH
High Level Enable Voltage
(VCC = 3.3 V, IF = 10 mA)
Single Channel
VEH
(VCC = 3.3 V, IF = 10 mA) (Note 2)
Single Channel
VEL
Low Level Enable Voltage
1.8
TA =25°C
2.0
V
0.8
V
Switching Characteristics (TA = -40°C to +85°C, VCC = 3.3 V, IF = 7.5 mA unless otherwise specified.)
AC Characteristics
Test Conditions Device
Propagation Delay Time
to Output High Level
(Note 3)
Symbol
Min
Typ
Max Unit
All
TPLH
90
ns
All
TPHL
75
ns
(RL = 350Ω, CL = 15 pF) (Fig. 9)
Propagation Delay Time
to Output Low Level
(Note 4)
(RL = 350Ω, CL = 15 pF) (Fig. 9)
(RL = 350Ω, CL = 15 pF) (Fig. 9)
All
|TPHL-TPLH|
25
ns
(RL = 350Ω, CL = 15 pF) (Note 5)
All
tPSK
40
ns
Output Rise Time
(10-90%)
(RL = 350Ω, CL = 15 pF) (Note 6) (Fig. 9)
All
tr
ns
Output Fall Time
(90-10%)
(RL = 350Ω, CL = 15 pF) (Note 7) (Fig. 12)
All
tf
ns
Pulse Width Distortion
Propagation Delay Skew
Enable Propagation
Delay Time to Output
High Level
(VEH = 3 V, RL = 350Ω,
CL = 15 pF)
(Note 8) (Fig. 10)
Single
Channel
All
tELH
ns
Enable Propagation
Delay Time to Output
Low Level
(VEH = 3 V, RL = 350Ω,
CL = 15 pF)
(Note 9) (Fig. 10)
Single
Channel
All
tEHL
ns
Common Mode
Transient Immunity
(at Output High Level)
(RL = 350Ω) (TA =25°C) |VCM| = 50 V
(IF = 0 mA, VOH (Min.) = 2.0V )
(Note 10) (Fig. 11)
All
|CMH|
25,000
50,000
V/µs
Common Mode
Transient Immunity
(at Output Low Level)
(RL = 350Ω) (TA =25°C) |VCM| = 50 V
(IF = 7.5 mA, VOL (Max.) = 0.8
V) (Note 11) (Fig. 11)
All
|CMH|
25,000
50,000
V/µs
3
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Electrical Characteristics (TA = -40°C to +85°C unless otherwise specified.)
Individual Component Characteristics
DC Characteristics
Test Conditions Symbol
High Level Output Current
(IF = 250 µA, VCC = 3.3 V, VO = 3.3 V)
(Note 2) VE = 2.0 V
Low Level Output Voltage
(Note 2) VE = 2.0 V
Max
Unit
IOH
50
µA
VOL
0.6
V
IFT
5
mA
Max
Unit
1.0*
µA
Single Channel
(VCC = 3.3 V, VO = 0.6 V, IOL = 13 mA)
(Note 2) VE = 2.0 V
Typ**
Single Channel
(VCC = 3.3 V, IF = 5 mA, IOL = 13 mA)
Input Threshold Current
Min
Single Channel
Isolation Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics
Input-Output
Insulation Leakage Current
Withstand Insulation Test
Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
Device
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 12)
IIO ≤ 10 µA, RH < 50%,
TA = 25°C)
(Note 12) ( t = 1 min.)
Symbol
Min
Typ**
II-O
FOD060L
FOD063L
VISO
FOD260L
2500
VRMS
5000
(VI-O = 500 V) (Note 12)
RI-O
1012
Ω
(f = 1 MHz) (Note 12)
CI-O
0.6
pF
** All typical values are at VCC = 3.3 V, TA = 25°C
Notes
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and
GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the
1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5V
level on the HIGH to LOW transition of the output voltage pulse.
5. tPSK is the worst case difference between tPHL and tPLH for any devices at the stated test conditions.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse
to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse
to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state
(i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
4
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Transfer Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Fig. 1 Input Forward Current vs.
Forward Voltage
Fig. 2 Input Threshold Current vs.
Ambient Temperature
2.5
100
ITH - Input Threshold Current (mA)
VCC = 3.3V
VO = 0.6V
I F - Forward Current (mA)
10
TA = 100°C
1
TA = -40°C
TA = 85°C
0.1
TA = 0°C
TA = 25°C
0.01
0.001
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.0
FOD063L
RL = 350Ω, 1kΩ, 4kΩ
1.5
FOD060L
RL = 350Ω, 1kΩ, 4kΩ
1.0
FOD260L
RL = 350Ω, 1kΩ, 4kΩ
0.5
0.0
-40
1.7
-20
VF - Forward Voltage (V)
0.6
40
60
80
100
20
CC
= 3.3V
I OH - High Level Output Current (nA)
V
VOL - Low Level Output Voltage (V)
20
Fig. 4 High Level Output Current
vs. Ambient Temperature
Fig. 3 Low Level Output Voltage vs.
Ambient Temperature
VE = 2V (Single channel products only)
IF = 5mA
IO = 13mA
0.5
0.4
0.3
0.2
0.1
-40
-20
0
20
40
60
80
16
12
8
4
VO = VCC = 3.3V
VE = 2V (Single channel products only)
IF = 250 µA
0
-40
0.0
100
-20
TA - Ambient Temperature (°C)
35
30
V
CC
40
60
80
100
80
= 3.3V
V
VE = 2V (Single channel products only)
VOL = 0.6V
IF = 5mA
20
15
10
CC
= 3.3V
IF = 7.5mA
70
25
RL = 350Ω
tPLH - FOD060L, FOD063L
tPLH - FOD260L
60
50
40
tPHL - FOD060L, FOD063L
tPHL - FOD260L
30
5
0
-40
20
Fig. 6 Propagation Delay vs.
Ambient Temperature
tP - Propagation Delay (ns)
40
0
TA - Ambient Temperature (°C)
Fig. 5 Low Level Output Current vs.
Ambient Temperature
IOL - Low Level Output Current (mA)
0
TA - Ambient Temperature (°C)
20
-20
0
20
40
60
80
100
-40
TA - Ambient Temperature (°C)
5
FOD060L, FOD260L, FOD063L Rev. 1.0.0
-20
0
20
40
60
80
TA - Ambient Temperature (°C)
100
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Typical Performance Curves
Fig. 7 Rise and Fall Times vs.
Ambient Temperature
Fig. 8 Pulse Width Distortion vs.
Ambient Temperature
30
35
V
= 3.3V
V
IF = 7.5mA
PWD - Pulse Width Distortion (ns)
tr, tf, - Rise, Fall Time (ns)
30
CC
RL = 350Ω
25
tr
20
15
10
5
25
CC
= 3.3V
IF = 7.5mA
RL = 350Ω
20
FOD260L
15
FOD060L
10
FOD063L
5
tf
0
-40
-20
0
20
40
60
80
0
-40
100
TA - Ambient Temperature (°C)
0
20
40
60
80
100
TA - Ambient Temperature (°C)
6
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Typical Performance Curves
Pulse Gen.
ZO = 50 Ω
tf = tr = 5 ns
+3.3V
I F = 7.5 mA
Dual Channel
+3.3V
IF
1
Input
Monitor
(IF)
47Ω
VCC
8
2
7
3
6
4
GND 5
0.1µF
Bypass
Output
(VO)
CL
VCC 8
2
7
3
6
t PHL
RL
Input
Monitoring
Node
RL
1
Output VO
Monitoring
Node
0.1µF
Bypass
RM
CL*
4
GND
I F = 3.75 mA
Input
(I F)
5
tPLH
Output
(VO )
1.5 V
90%
Output
(VO )
10%
tf
Test Circuit for FOD060L,
and FOD260L
tr
Test Circuit for FOD063L
Fig. 9 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
Pulse
Generator
tr = 5ns
Z O = 50Ω
Input
Monitor
(V E)
+3.3V
3.0 V
1
8
2
7
3
6
Input
(VE )
1.5 V
t EHL
7.5 mA
0.1µF
bypass
t ELH
Output
(VO )
RL
1.5 V
Output
(VO )
CL
4
5
Fig. 10 Test Circuit tEHL and tELH.
7
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Pulse Gen.
tf = tr = 5 ns
ZO = 50 Ω
VCC
1
Dual Channel
+3.3V
8
B
A
IF
A
2
7
3
6
4
5
0.1µf
bypass
GND
VCC 8
2
7
3
6
+3.3V
RL
350Ω
VFF
B
VFF
1
Output
(VO)
4
GND
0.1µF
Bypass
Output VO
Monitoring
Node
5
VCM
+
–
Pulse
Generator
ZO = 50 Ω
VCM
Pulse Gen
Test Circuit for FOD060L and FOD260L
Test Circuit for FOD063L
VCM
0V
Peak
CM H
3.3V
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
Switching Pos. (B), IF = 7.5 mA
VO
0.5 V
CM L
Fig. 11 Test Circuit Common Mode Transient Immunity
8
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
IF
Package Dimensions (Surface Mount)
8-Pin Small Outline
PIN 1
ID.
0.024 (0.61)
SEATING PLANE
0.164 (4.16)
0.144 (3.66)
0.060 (1.52)
0.275 (6.99)
0.202 (5.13)
0.182 (4.63)
0.155 (3.94)
0.010 (0.25)
0.006 (0.16)
0.143 (3.63)
0.123 (3.13)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.244 (6.19)
0.224 (5.69)
0.050 (1.27)
0.050 (1.27)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
9
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
8-Pin SOIC
Package Dimensions (Through Hole)
Package Dimensions (Surface Mount)
0.390 (9.91)
0.370 (9.40)
PIN 1
ID.
4
3
2
4
3
2
1
PIN 1
ID.
1
0.270 (6.86)
0.250 (6.35)
5
6
7
0.270 (6.86)
0.250 (6.35)
8
5
SEATING PLANE
SEATING PLANE
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.020 (0.51) MIN
0.200 (5.08)
0.140 (3.55)
6
7
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
0.300 (7.62)
TYP
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
0.140 (3.55)
0.020 (0.51)
MIN
0.154 (3.90)
0.120 (3.05)
0.022 (0.56)
0.016 (0.41)
8
0.016 (0.41)
0.008 (0.20)
0.045 [1.14]
0.022 (0.56)
0.016 (0.41)
15° MAX
0.100 (2.54)
TYP
0.300 (7.62)
TYP
0.315 (8.00)
MIN
0.405 (10.30)
MIN
Lead Coplanarity : 0.004 (0.10) MAX
Package Dimensions (0.4” Lead Spacing)
4
3
2
8-Pin DIP
PIN 1
ID.
1
0.070 (1.78)
0.270 (6.86)
0.250 (6.35)
0.060 (1.52)
5
6
7
8
SEATING PLANE
0.390 (9.91)
0.370 (9.40)
0.100 (2.54)
0.295 (7.49)
0.070 (1.78)
0.045 (1.14)
0.415 (10.54)
0.030 (0.76)
0.004 (0.10) MIN
0.200 (5.08)
0.140 (3.55)
0.154 (3.90)
0.120 (3.05)
0.022 (0.56)
0.016 (0.41)
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
0° to 15°
0.400 (10.16)
TYP
NOTE
All dimensions are in inches (millimeters)
10
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
8-Pin DIP
Option
Order Entry
Identifier
No Suffix
FOD260L
Through Hole (DIP package only)
FOD060L
Surface Mount Lead Form (SOIC-8 package only)
S
FOD260LS
SD
FOD260LSD
Description
Surface Mount Lead Bend (DIP package only)
Surface Mount; Tape and reel (DIP package only)
SV
Pending Approval
Surface Mount; VDE0884 (DIP package only)
SDV
Pending Approval
Surface Mount; Tape and reel, VDE0884 (1000 units per reel) (DIP package only)
T
FOD260LT
TV
Pending Approval
R1
FOD060LR1
R1V
Pending Approval
0.4" Lead Spacing (DIP package only)
0.4" Lead Spacing, VDE0884 (DIP package only)
Tape and Reel (500 units per reel) (SOIC-8 package only)
VDE, Tape and Reel (500 units per reel) (SOIC-8 package only)
R2
FOD060LR2
R2V
Pending Approval
VDE, Tape and Reel (2500 units per reel) (SOIC-8 package only)
Tape and Reel (2500 units per reel) (SOIC-8 package only)
V
Pending Approval
VDE (SOIC-8 package only)
Marking Information
SOIC
DIP
2
V
3
260L
2
XX YY T1
6
X YY S
V
3
5
4
60L
1
1
4
6
5
Definitions
1
Fairchild logo
2
Device number
3
VDE mark (Note: Only appears on parts ordered with VDE option –
See order entry table)
4 (DIP)
Two digit year code, e.g., ‘03’
4 (SOIC)
One digit year code, e.g., ‘3’
5
Two digit work week ranging from ‘01’ to ‘53’
6
Assembly package code
11
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Ordering Information
Carrier Tape Specifications (FOD260L)
12.0 ±0.1
4.0 ±0.1
4.90 ±0.20
Ø1.55 ±0.05
4.0 ±0.1
0.30 ±0.05
1.75 ±0.10
7.5 ±0.1
16.0 ±0.3
13.2 ±0.2
10.30 ±0.20
Ø1.6 ±0.1
10.30 ±0.20
0.1 MAX
User Direction of Feed
Reflow Profile (FOD260L)
• Peak reflow temperature
• Time of temperature higher than 245°C
• Number of reflows
260° C (package surface temperature)
40 seconds or less
Three
10 s
300
260°
245°
Temperature
(°C)
250
200
150
40 s
100
50
50
100
150
Time (s)
12
FOD060L, FOD260L, FOD063L Rev. 1.0.0
200
250
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
8-Pin DIP
Carrier Tape Specifications (FOD060L, FOD063L)
8.0 ± 0.10
3.50 ± 0.20
2.0 ± 0.05
Ø1.5 MIN
4.0 ± 0.10
0.30 MAX
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.3 ± 0.10
5.20 ± 0.20
Ø1.5 ± 0.1/-0
6.40 ± 0.20
0.1 MAX
User Direction of Feed
Reflow Profile (FOD060L, FOD063L)
300
260°C
280
260
>245°C = 42 Sec
240
220
200
180
°C
Time above
183°C = 90 Sec
160
140
120
1.822°C/Sec Ramp up rate
100
80
60
40
33 Sec
20
0
0
60
120
180
270
360
Time (s)
13
FOD060L, FOD260L, FOD063L Rev. 1.0.0
www.fairchildsemi.com
FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
8-Pin SOIC
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failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
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any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I15
14
FOD060L, FOD260L, FOD063L Rev. 1.0.0
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FOD060L, FOD260L, FOD063L LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
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