HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 DESCRIPTION The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10 kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum CMR of 10 kV/µs. 8 1 8 FEATURES • • • • • • • • 8 1 Very high speed-10 MBit/s Superior CMR-10 kV/µs Double working voltage-480V Fan-out of 8 over -40°C to +85°C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E90700) N/C 1 8 VCC 1 + 1 8 VCC VF1 + 2 7 VE _ 2 6 VO _ 7 V01 VF _ 3 V N/C 4 5 GND 3 6 V02 F2 + 4 5 GND APPLICATIONS • • • • • • • Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface 6N137 HCPL-2601 HCPL-2611 HCPL-2630 HCPL-2631 TRUTH TABLE (Positive Logic) Input Enable Output H H L L H H H L H L L H H NC L L NC H A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1) 2001 Fairchild Semiconductor Corporation DS300202 7/9/01 1 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C) Parameter Symbol Value Storage Temperature TSTG -55 to +125 °C Operating Temperature TOPR -40 to +85 °C Lead Solder Temperature TSOL 260 for 10 sec °C EMITTER DC/Average Forward Input Current Single channel Power Dissipation Single channel VE Each channel VR Single channel DETECTOR Single channel Output Voltage Collector Output Power Dissipation Each channel mW V mA 50 7.0 V 85 PO Dual channel (Each channel) V 50 VO Single channel 5.0 7.0 IO Dual channel (Each channel) V 45 VCC (1 minute max) Supply Voltage 5.5 100 PI Dual channel (Each channel) Output Current mA 30 Not to exceed VCC by more than 500 mV Reverse Input Voltage 50 IF Dual channel (Each channel) Enable Input Voltage Units mW 60 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Units Input Current, Low Level IFL 0 250 µA Input Current, High Level IFH *6.3 15 mA Supply Voltage, Output VCC 4.5 5.5 V Enable Voltage, Low Level VEL 0 0.8 V Enable Voltage, High Level VEH 2.0 VCC V Low Level Supply Current TA -40 +85 °C Fan Out (TTL load) N 8 * 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less www.fairchildsemi.com 2 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.) INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions EMITTER (IF = 10 mA) Input Forward Voltage TA =25°C Input Reverse Breakdown Voltage (IR = 10 µA) Input Capacitance (VF = 0, f = 1 MHz) Input Diode Temperature Coefficient (IF = 10 mA) DETECTOR High Level Supply Current Single Channel (VCC = 5.5 V, IF = 0 mA) Dual Channel (VE = 0.5 V) Low Level Supply Current Single Channel (VCC = 5.5 V, IF = 10 mA) Dual Channel (VE = 0.5 V) Low Level Enable Current (VCC = 5.5 V, VE = 0.5 V) High Level Enable Current (VCC = 5.5 V, VE = 2.0 V) High Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) Low Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) (Note 3) SWITCHING CHARACTERISTICS Test Conditions (Note 4) (TA =25°C) (RL = 350 1, CL = 15 pF) (Fig. 12) (Note 5) (TA =25°C) (RL = 350 1, CL = 15 pF) (Fig. 12) (RL = 350 1, CL = 15 pF) (Fig. 12) (RL = 350 1, CL = 15 pF) Output Rise Time (10-90%) (Note 6) (Fig. 12) (RL = 350 1, CL = 15 pF) Output Fall Time (90-10%) (Note 7) (Fig. 12) Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V) to Output High Level (RL = 350 1, CL = 15 pF) (Note 8) (Fig. 13) Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V) to Output Low Level (RL = 350 1, CL = 15 pF) (Note 9) (Fig. 13) Common Mode Transient Immunity (TA =25°C) VCM = 50 V, (Peak) (at Output High Level) (IF = 0 mA, VOH (Min.) = 2.0 V) 6N137, HCPL-2630 (RL = 350 1) (Note 10) HCPL-2601, HCPL-2631 (Fig. 14) HCPL-2611 VCM = 400 V (RL = 350 1) (IF = 7.5 mA, VOL (Max.) = 0.8 V) Common Mode 6N137, HCPL-2630 VCM = 50 V (Peak) Transient Immunity HCPL-2601, HCPL-2631 (TA =25°C) (at Output Low Level) (Note 11) (Fig. 14) HCPL-2611 (TA =25°C) VCM = 400 V 7/9/01 Min VF BVR CIN VF/TA 1.4 Max 1.8 1.75 5.0 ICCL Unit V V pF mV/°C 60 -1.4 ICCH IEL IEH VEH VEL Typ** 7 10 10 9 14 -0.8 -0.6 15 13 21 -1.6 -1.6 2.0 0.8 mA mA mA mA V V (TA = -40°C to +85°C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.) AC Characteristics Propagation Delay Time to Output High Level Propagation Delay Time to Output Low Level Pulse Width Distortion DS300202 Symbol 3 OF 11 Symbol TPLH TPHL Min 20 Typ** 45 25 45 Max 75 100 75 100 35 Unit ns ns TPHL-TPLH 3 tr 50 ns tf 12 ns tELH 20 ns tEHL 20 ns 10,000 10,000 15,000 V/µs CMH 5000 10,000 ns 10,000 CML V/µs 5000 10,000 10,000 15,000 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.) DC Characteristics Test Conditions High Level Output Current Symbol (VCC = 5.5 V, VO = 5.5 V) (VCC = 5.5 V, IF = 5 mA) (VE = 2.0 V, ICL = 13 mA) (Note 2) Input Threshold Current Typ** IOH (IF = 250 µA, VE = 2.0 V) (Note 2) Low Level Output Current Min (VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA) 100 µA .35 0.6 V IFT 3 5 mA Typ** Max Unit 1.0* µA (TA = -40°C to +85°C Unless otherwise specified.) Characteristics Test Conditions Insulation Leakage Current Unit VOL ISOLATION CHARACTERISTICS Input-Output Max Symbol Min (Relative humidity = 45%) (TA = 25°C, t = 5 s) (VI-O = 3000 VDC) II-O (Note 12) Withstand Insulation Test Voltage (RH < 50%, TA = 25°C) (Note 12) ( t = 1 min.) Resistance (Input to Output) Capacitance (Input to Output) VISO 2500 VRMS (VI-O = 500 V) (Note 12) RI-O 1012 1 (f = 1 MHz) (Note 12) CI-O 0.6 pF ** All typical values are at VCC = 5 V, TA = 25°C NOTES 1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Each channel. 3. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 4. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 5. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 6. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse. 7. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse. 8. tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 9. tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 10. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs). 11. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs). 12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together. www.fairchildsemi.com 4 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 TYPICAL PERFORMANCE CURVES Fig. 2 Input Diode Forward Voltage vs. Forward Current Fig.1 Low Level Output Voltage vs. Ambient Temperature 0.8 Conditions: IF = 5 mA VE = 2 V VCC = 5.5V VOL-Low Level Output Voltage (V) 0.7 30 16 10 IOL = 16 mA 0.6 IF = Forward Current (mA) IOL = 12.8 mA 0.5 0.4 0.3 0.2 IOL = 9.6 mA 1 0.1 0.01 0.1 IOL = 6.4 mA 0.0 -40 -20 0 0.001 20 40 60 80 0.9 1.0 TA - Ambient Temperature (˚C) 1.1 1.2 50 VCC = 5 V IOL - Low Level Output Current (mA) TP - Propagation Delay (ns) 80 RL = 4 k1 (TPLH) 60 40 20 RL = 350 1 (TPLH) RL = 1 k1 RL = 4 k1 (TPHL) RL = 350 k1 RL = 1 k 1 (TPLH) 0 1.6 7 9 11 13 45 IF = 10 mA 40 IF = 5 mA 35 30 Conditions: VCC = 5 V VE = 2 V VOL = 0.6 V 25 20 -40 15 -20 20 40 60 80 Fig. 6 Output Voltage vs. Input Forward Current Fig. 5 Input Threshold Current vs. Ambient Temperature 6 4 Conditions: VCC = 5.0 V VO = 0.6 V 0 TA - Ambient Temperature (˚C) IF - Forward Current (mA) 5 RL = 350 1 RL = 350 1 VO - Output Voltage (V) IFT - Input Threshold Current (mA) 1.5 IF = 15 mA 100 3 2 4 RL =4k 1 RL = 1k 1 3 2 1 RL = 1k 1 RL = 4k 1 1 -40 -20 0 20 40 0 60 0 80 TA - Ambient Temperature (˚C) DS300202 1.4 Fig. 4 Low Level Output Current vs. Ambient Temperature Fig.3 Switching Time vs. Forward Current 120 5 1.3 VF - Forward Voltage (V) 7/9/01 1 2 3 4 5 6 IF - Forward Current (mA) 5 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 Fig. 8 Rise and Fall Time vs. Temperature Fig. 7 Pulse Width Distortion vs. Temperature 600 80 Conditions: IF = 7.5 mA VCC = 5 V Tr/Tf - Rise and Fall Time (ns) PWD - Pulse Width Distortion (ns) 500 60 RL = 4 k 1 40 RL = 1 k 1 RL = 350 1 20 0 400 Conditions: IF = 7.5 mA VCC = 5 V RL = 4 k1(tr) 300 RL = 1 k1(tr) 200 RL = 350 1(tr) 100 0 -60 -40 -20 0 20 40 60 80 ] RL = 1 k 1 RL = 4 k 1 (tf) RL = 350 1 -60 100 -40 -20 TA - Temperature (˚C) 0 20 40 60 80 100 TA - Temperature (˚C) Fig. 9 Enable Propagation Delay vs. Temperature Fig. 10 Switching Time vs. Temperature 120 120 RL = 4 k 1(TELH) 100 TP-Propagation Delay (ns) TE-Enable Propagation Delay (ns) 100 80 60 RL = 1 k 1(TELH) RL = 350 1(TELH) 40 RL = 1 k 1TPLH RL = 4 k 1TPLH RL = 350 1TPLH 60 40 20 0 -60 80 ] RL = 350 1 RL = 1 k 1 RL = 4 k 1 -40 -20 0 20 40 60 RL = 1 k 1 RL = 4 k 1 RL = 350 1 (TEHL) 80 20 -60 100 -40 -20 0 TA-Temperature (˚C) 20 40 60 ] TPHL 80 100 TA-Temperature (˚C) Fig. 11 High Level Output Current vs. Temperature IOH-High Level Output Current (µA) 20 Conditions: VCC = 5.5 V VO = 5.5 V VE = 2.0 V IF = 250 µA 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 TA-Temperature (˚C) www.fairchildsemi.com 6 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 Pulse Generator tr = 5ns Z O = 50 1 +5V I F = 7.5 mA 1 VCC I F = 3.75 mA 8 Input (I F) 7 Output (VO ) t PHL 2 Input Monitor (I F) .1 Ef bypass RL Output (VO ) 6 3 CL 471 4 GND tPLH 1.5 V 90% Output (VO ) 10% 5 tf tr Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf. Pulse Generator tr = 5ns Z O = 50 1 Input Monitor (V E) +5V 3.0 V Input (VE ) VCC 1 8 1.5 V t EHL 7.5 mA 7 2 .1 Ef bypass RL 1.5 V Output (VO ) 6 3 tELH Output (VO ) CL 4 GND 5 Fig. 13 Test Circuit tEHL and tELH. DS300202 7/9/01 7 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 VCC IF A 1 8 2 7 3 6 +5V .1 Ef bypass 350 1 B VFF 4 GND Output (VO) 5 VCM Pulse Gen Peak VCM 0V CM H 5V Switching Pos. (A), I F= 0 VO VO (Min) VO (Max) VO 0.5 V Switching Pos. (B), I F= 7.5 mA CM L Fig. 14 Test Circuit Common Mode Transient Immunity www.fairchildsemi.com 8 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 Package Dimensions (Through Hole) Package Dimensions (Surface Mount) 0.390 (9.91) 0.370 (9.40) PIN 1 ID. 3 4 2 4 3 2 1 PIN 1 ID. 1 0.270 (6.86) 0.250 (6.35) 5 6 7 0.270 (6.86) 0.250 (6.35) 8 5 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 6 7 8 0.070 (1.78) 0.045 (1.14) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.300 (7.62) TYP 0.020 (0.51) MIN 0.016 (0.41) 0.008 (0.20) 0.020 (0.51) MIN 0.154 (3.90 ) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.045 [1.14] 0.022 (0.56) 0.016 (0.41) 15° MAX 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP 0.100 (2.54) TYP 0.300 (7.62) TYP 0.315 (8.00) MIN 0.405 (10.30) MIN Lead Coplanarity : 0.004 (0.10) MAX Package Dimensions (0.4”Lead Spacing) 4 3 2 1 PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 5 6 7 8 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) NOTE 0.004 (0.10) MIN All dimensions are in inches (millimeters) 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) DS300202 7/9/01 0° to15° 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP 0.400 (10.16) TYP 9 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 ORDERING INFORMATION Option Order Entry Identifier Description S .S Surface Mount Lead Bend SD .SD Surface Mount; Tape and reel W .W 0.4” Lead Spacing QT Carrier Tape Specifications (“D” Taping Orientation) 12.0 ± 0.1 4.90 ± 0.20 4.0 ± 0.1 0.30 ± 0.05 4.0 ± 0.1 Ø1.55 ± 0.05 1.75 ± 0.10 7.5 ± 0.1 16.0 ± 0.3 13.2 ± 0.2 10.30 ± 0.20 0.1 MAX 10.30 ± 0.20 Ø1.6 ± 0.1 User Direction of Feed www.fairchildsemi.com 10 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in labeling, can be reasonably expected to result in a significant injury of the user. DS300202 7/9/01 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 11 OF 11 www.fairchildsemi.com