IT7020C/CY Durable High-Voltage 240-Channel

IT7020C/CY
Durable High-Voltage 240-Channel
Common Driver for Dot-Matrix STN LCD
Preliminary Specification V0.7
INTEGRATED TECHNOLOGY EXPRESS, INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
Copyright  2003 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related products
included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE’s Standard
Terms and Conditions, a copy of which is included in the back of this document.
ITE, IT7020C/CY is a trademark of ITE, Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE, Inc.
Marketing Department
8F, No. 233-1, Bao Chiao RD., Hsin Tien,
Taipei County 231, Taiwan, R.O.C.
Phone:
Fax:
(02) 29126889
(02) 2910-2551, 2910-2552
ITE (USA) Inc.
Marketing Department
1235 Midas Way
Sunnyvale, CA 94086
U.S.A.
Phone:
Fax:
(408) 530-8860
(408) 530-8861
ITE (USA) Inc.
Eastern U.S.A. Sales Office
896 Summit St., #105
Round Rock, TX 78664
U.S.A.
Phone:
Fax:
(512) 388-7880
(512) 388-3108
If you have any marketing or sales questions, please contact:
Lawrence Liu, at ITE Taiwan: E-mail: [email protected], Tel: 886-2-26579896 X6071,
Fax: 886-2-26578561
David Lin, at ITE U.S.A: E-mail: [email protected], Tel: (408) 530-8860 X238,
Fax: (408) 530-8861
Don Gardenhire, at ITE Eastern USA Office: E-mail: [email protected]
Tel: (512) 388-7880, Fax: (512) 388-3108
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
http://www.iteusa.com
Or e-mail [email protected] for more product information/services.
Revision History
Revision History
Section
Revision
IT7020C/H was changed into IT7020C/CY in this version.
Section 4.2 “Chip Form Package (349 bumps)” of version 0.6 was deleted.
10
The figures in section10 were revised.
25, 26
11
The ordering information was revised.
27
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IT7020C/CY V0.7
Contents
CONTENTS
1. Features ...................................................................................................................................................1
2. General Description ..................................................................................................................................3
3. Block Diagram ..........................................................................................................................................5
4. Pin Configuration ......................................................................................................................................7
5. IT7020C/CY Pin Descriptions....................................................................................................................9
6. System Configuration .............................................................................................................................13
6.1 Overview ....................................................................................................................................13
6.2 LCD Drive Circuit........................................................................................................................13
6.3 Shift Register Circuit ...................................................................................................................13
6.4 Alternating Signal (M) Generation Circuit ....................................................................................13
7. Terminal Configuration............................................................................................................................15
8. DC Electrical Characteristics...................................................................................................................17
8.1 Activation and Inactivation Sequence..........................................................................................17
8.1.1 Power On Sequence ........................................................................................................18
8.1.2 Power Down Sequence ....................................................................................................18
1.1 DC..............................................................................................................................................20
8.2 Electrical Characteristics (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75
°C) .............................................................................................................................................20
9. AC Characteristics ..................................................................................................................................23
9.1 AC Characteristics 1 (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)
...................................................................................................................................................23
9.2 AC Characteristics 2 (Vcc = 2.5 to 4.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)....23
9.3 AC Characteristics 3 (Vcc = 4.5 to 5.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)....23
10. Package Information...............................................................................................................................25
11. Ordering Information...............................................................................................................................27
FIGURES
Figure 4-1. 273-pin TCP.................................................................................................................................7
Figure 5-1. DOC Waveform..........................................................................................................................12
Figure 5-2. LCD Driver Terminal Output Voltage Level .................................................................................12
Figure 7-1. IT7020 Power and Input Terminal Configuration .........................................................................15
Figure 7-2. IT7020 I/O, Input and Output Terminal Configuration..................................................................16
Figure 8-1. IT7020 Power On/Down Scenario ..............................................................................................19
Figure 8-32. LCD Common Drive Output Waveform & Voltage Level............................................................21
Figure 9-1. AC Characteristics Testing Configuration ...................................................................................24
Figure 9-2. IT7020 Timing Diagram ..............................................................................................................24
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TABLES
Table 5-1. Pin Descriptions of Power Signals .................................................................................................9
Table 5-2. Pin Descriptions of Control Signals ................................................................................................9
Table 5-3. Pin Descriptions of LCD Drive Output Signals..............................................................................11
Table 8-1. DC Characteristics (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)20
Table 9-1. AC Characteristics 1(Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)23
Table 9-2. AC Characteristics 2 (Vcc = 2.5 to 4.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C).....23
Table 9-3. AC Characteristics 3 (Vcc = 4.5 to 5.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C).....23
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Features
1. Features
Supports up to 1/240 display duty
Supports 43V LCD drive voltage at
maximum
Supports 2.5 to 5.5V operating voltage
Provides 240 LCD drive circuit
Provides built-in power circuit for
generating –21.5 V
Provides the intermediate voltage interface
Provides 3 selections of output modes:
- 240-output mode
- 200-output mode
- 160-output mode
Built-in alternating signal generation circuit
(programmable through the MWS0 – MWS4
pins) is provided to restrain crosstalk
Supports the display-off function
Package
- 273-pin Flex TCP
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Specifications Subject to Change without Notice
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By Dean Hu, 1/14/2003
ITPM-PN-200301
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General Description
2. General Description
The IT7020C/CY features a high-voltage common driver, which consists of 240 channels. The IT7020C/CY can
drive a dot matrix STN LCD panel, and has been designed specifically to meet the LCD requirement in PDA
devices. It can be used in conjunction with the segment drivers: IT7010C/H or IT7012C/H.
In terms of power consumption, the device is able to reduce the required voltage level and power consumption
considerably. Additionally, the built-in screen display off function supported in the device can also help to
reduce the overall power consumption while the LCD panel is not actively in use. In logic portion, the
IT7020C/CY operates with a low 3V logic drive voltage to help reduce power consumption.
The device can generate a high voltage drive of +21.5V and –21.5V through a 43V high voltage CMOS process
technology. By the built-in power circuit and external capacity, the generation of –21.5V will occur from +21.5V.
In addition, users are allowed the selection of 240-, 200- and 160-channel output mode by conveniently
changing the mode according to what panel resolution they have.
Moreover, ITE also provides users with complete local technical support. The company is dedicated to assisting
customers in procuring multiple competitive edges, such as reducing development time, cost effectiveness and
low power consumption for expanding the STN-LCD market share in a fast move.
ITE is committed to launching the LCD driver and controller series products, and will offer the most competitive
solution through high integration and solid R&D expertise.
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Block Diagram
3. Block Diagram
X1-X240
*2
VHL
VLL
VML
VHR
VLR
VMR
LC D Drive C ircuit
*1
VLCDL/R
Le ve l
S hifte r
Le ve l S hifte r
VEEL/R
S hift re gis te r
S hift re gis te r
S hift re g is te r
S hift re gis te r
D
SR
21
D
SR
41
D
SR
201
D
SR
221
D
Q
~
D
~
DIS P OFF
Q
SR
240
Q
Logic
~
Q
Q
SR
220
Logic
~
Q
Q
SR
200
Logic
~
Q
S4R
0
D
M_S
D
Logic
Logic
Q
Q
S2R
0
D
Logic
S hift re gis te r
D
SR
1
Logic
M
MWS 0 to MWS 4
RE S E T
Alte rna ting s igna l
ge ne ra tion circuit
Logic
CL
VEO
CCL
AMP
C1
C2
DIO1
DIO2
S HL
MODE0
MODE1
P owe r C ircuit
DOC
VCC
G ND
*1. VLCDL a nd VLCDR, a nd VE EL a nd VEER a re inte rna lly conne cte d.
*2. VHL a nd VHR , VLL, VML a nd VMR a re inte rna lly conne cte d.
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VLCDL
VHL
VML
VLL
VEEL
VEO
C1
C2
DIO2
M
RESET
MWS4
MWS3
MWS2
MWS1
MWS0
VCC
MODE1
MODE0
DOC
DISPOFF
AMP
SHL
GND
CL
CCL
M_S
DIO1
VEER
VLR
VMR
VHR
VLCDR
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
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236
237
238
239
240
1
2
3
4
5
X236
X237
X238
X239
X240
X1
X2
X3
X4
X5
Pin Configuration
4. Pin Configuration
Top View
Note: The shape above does not indicate the actual outline.
Figure 4-1. 273-pin TCP
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IT7020C/CY Pin Descriptions
5. IT7020C/CY Pin Descriptions
Table 5-1. Pin Descriptions of Power Signals
Pin(s) No.
267, 266
273, 241
269, 245
257, 250
272, 242
270, 244
271, 243
Symbol
C1, C2
VLCDL/R
VEEL/R
Vcc, GND
VHL/R
VLL/R
VML/R
Attribute
-
-
Description
Connect the external capacitance here when the power
circuit is enabled for VEE generation.
It is advisable that users should not connect any traces to these
pins if the built-in power circuit is not used.
VLCDL/R and VEEL/R are used to provide the power supply for
the usage of LCD drive.
VEEL/R are used to provide the power supply for the usage
of power circuits.
Input
Vcc, GND are used to provide the power supply for the usage of
logic circuits.
These pins are used to provide the power supply for LCD drive
level.
VHL/R and VLL/R indicate the selected level of LCD drive. Note
that VHL/R is set to the same voltage as VLCDL/R while VLL/R is
set to the same voltage as VEEL/R.
VML/R indicates the non-selected LCD drive level. It
provides the power supply for the built-in power circuits as
well.
268
VEO
Output
Connect VEO pin to the VEEL/R pins when the built-in power
circuit is enabled to generate VEE voltage. In this case, the VM
voltage is used as the point of reference and the output voltage of
VEO is equal to (2*VM – VLCD). Users are advised not to connect
any lines to this pin if the built-in power circuit is not used.
Table 5-2. Pin Descriptions of Control Signals
Pin(s) No.
252
Symbol
AMP
Attribute
Input
248
CCL
Input
249
CL
Input
Description
This signal is used to control the on and off states the built-in
power circuit. When the circuit is used, this pin must be tied to
Vcc. When the built-in power circuit is not used, this pin must be
tied to GND.
Indicates the built-in power circuit clock input. When the built-in
power circuit is enabled and VEE is generated, this pin is
connected to the CL pin. When the built-in power circuit is not
used, CCL must be tied to GND.
Shift Clock Input.
Data is shifted and latched at the falling edge of CL in the shift
register.
246
265
DIO1
DIO2
Input/
Output
253
DISPOFF
Input
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Serial Data Input/Output Pin.
When the SHL is high, the DIO1 is the serial output pin and DIO2
is the serial input pin.
When the SHL is low, the DIO1 is the serial input pin and DIO2 is
the serial output pin.
Set LCD drive outputs of X1 to X240 to the VM level by
connecting this pin to GND.
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Table 5-2. Pin Descriptions of Control Signals [cont’d]
Pin(s) No.
254
Symbol
DOC
264
247
M
M_S
255
256
MODE0
MODE1
Attribute
Output
Description
When the M_S pin is set to high level, the output level of DOC pin
is the same as the DISPOFF pin.
When the M_S pin is set to low level, DOC pin outputs low level
until serial data input 16 times. See Figure 5-1 for more details.
Note that when M_S is set to low level, the DOC pin should be
connected to IT7010C DOF_N control pin.
Input/Output Input or output the toggling waveform for LCD drive output level.
Input
Control the LCD display-off function and determine the LCD
display-off signal to output from DOC pin.
When the M_S is set to high level and the DISPOFF is low level,
X1-X240 pins will set to the VM level.
When the M_S is set to low level, the X1-X240 pins will stay on
the VM level until serial data input 16 times (See Figure 5-1).
Input
Input terminals for specifying the effective number of
LCD drive output pins.
MODE0 MODE1 Shift Direction
“H”
“H”
“L”
“L”
258
259
260
261
262
MWS0
MWS1
MWS2
MWS3
MWS4
Input
“H”
“L”
“H”
“L”
240-output (X1, X2, X3…X238, X239, X240)
200-output (X21, X22, X23…X218, X219, X220)
160-output (X41, X42, X43…X198, X199, X200)
Undefined. Use at your own risk!
These pins are used to specify the frequency of the toggling
signal (M signal) in the unit of number of display lines. The
number of display lines is an integer ranging from 2 to 31 and is
specified in the table below. Typically, the number of display lines
ranges from 10 to 31.
If IT7020 is configured in the slave mode, i.e., driven by an
external M signal, MWS0 – MWS4 should be tied to low level.
Number MWS MWS MWS MWS MWS
Line toggling
M-pin
of lines
4
3
2
1
0
waveform
status
0
0
0
0
0
0
Input
1
0
0
0
0
1
Prohibited
Output
2
0
0
0
1
0
2 lines alternated
3
0
0
0
1
1
3 lines alternated
263
RESET
Input
251
SHL
Input
:
:
:
:
:
:
:
31
1
1
1
1
1
31 lines alternated
Initialize the toggling signal (M signal) circuit by connecting
this pin to GND. Tied to Vcc for normal operation.
This pin is used to switch the shift directions.
SHL
MODE0
MODE1
“H”
level
“H”
“H”
“L”
“H”
“L”
“H”
Shift Direction
Right shift
DIO2→SR1…SR240→DIO1
DIO2→SR21…SR220→DIO1
DIO2→SR41…SR200→DIO1
Left shift
“H”
“H”
DIO1→SR240…SR1→DIO2
“H”
“L”
DIO1→SR220…SR21→DIO2
“L”
“H”
DIO1→SR200…SR41→DIO2
SR1, SR2…SR240 are the outputs of the shift registers and
correspond to X1, X2…X240.
“L”
level
Note: The 40 or 80 pins, which are invalidated at the 200 or
160-output mode, will output the non-selected level (VM).
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IT7020C/CY Pin Descriptions
Table 5-3. Pin Descriptions of LCD Drive Output Signals
Pin(s) No.
1 to 240
Symbol
X1 to X240
Attribute
Output
Description
LCD Drive Output.
When DISPOFF is set to Vcc, the output level of X1 – X240 are
determined by the combination of the display data and the M
signal. Either one of VH, VL, or VM is selected and then
transmitted to the output circuit. See Figure 5-2 for more
details.
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IT7020C/CY
DISPOFF
1
2
3
4
5
14 15 16
DIO1/2
DOC
Figure 5-1. DOC Waveform
D
Output
level
0
1
M
1
0
1
0
VL
VM
VH
VM
Figure 5-2. LCD Driver Terminal Output Voltage Level
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System Configuration
6. System Configuration
6.1 Overview
The IT7020 is composed of 4 main elements to work properly: LCD Drive Circuits, Level Shifter, Shift Register
Circuit, and Alternating Signal Generation Circuits. The functional descriptions for each of the 4 elements are
described below:
6.2 LCD Drive Circuit
The device consists of 240 LCD drive circuits, and each of the LCD drive circuit is responsible to select and
output the three level signals for the LCD drive. Either one of VH, VL and VM will be selected and transmitted to
the output circuit by combining the data in the shift register and M signal together. The level shifter is
responsible for boosting a logic voltage to the high for LCD drive.
6.3 Shift Register Circuit
The shift register circuit is made up of 240 bits and is bi-directional. The first line marker signal, coming from
either DIO1 or DIO2 pins, can be sequentially shifted through the shift register circuit via the shift clock. The first
line marker signal can be then sequentially shifted via the shift clock CL. The shifting direction is determined by
SHL pin.
6.4 Alternating Signal (M) Generation Circuit
The alternating Signal Generation circuit is used to generate an alternating signal (M signal) for proper LCD
display. To restrain the crosstalk function, the signal is alternated from several lines to a host of lines. If pins
MWS0 to MWS4 are connected to Vcc or GND, the intended number of signals can be alternated. Note that the
connection of pins MWS0 to MWS4 with GND can be done when the alternating signals are input externally.
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Terminal Configuration
7. Terminal Configuration
VLCD
I
VLCD
VM
I
VH
VEE
VEE
Power Terminal 1
Applicable terminal: VMR/L
* VMR terminal is connected with V ML
terminal in LSI.
Input Terminal 1
Applicable terminal: V HR/L
* VHR terminal is connected with V HL terminal
in LSI.
VLCD
I
VL
VEE
Input Terminal 2
Applicable terminal: V LR/L
* VLR terminal is connected with V LL terminal
in LSI.
Figure 7-1. IT7020 Power and Input Terminal Configuration
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Vcc
Input Da ta
Vcc
GND
Da ta
Output
e na ble
GND
I/O Te rmina l 1
Applica ble te rmina ls : DIO1, DIO2, M
VLC D
Cha rge
P ump
I/O
VLC D
VH
VEE
VL
VM
VLC D
O
VEE
VE E
I/O Te rm ina l 2
Applica ble te rm ina l: C 1,C 2
VM
LCD Drive Output Te rmina l
Applica ble te rmina ls : X1 to X240
Vcc
Vcc
Input
Da ta
I
O
GND
Input Te rm ina l
Applica ble te rmina ls :
CL, CCL, S HL, MODE0, 1, AMP ,
DIS P OFF, R ES ET, MWS 0~4, M_S
Output Te rmina l
Applica ble te rm ina l: DOC
Figure 7-2. IT7020 I/O, Input and Output Terminal Configuration
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DC Electrical Characteristics
8. DC Electrical Characteristics
Absolute Maximum Ratings
*Comments:
Power Supply (Vcc) ......................... -0.3 to +7.0V
Power Supply (VLCD) .................... -0.3 to +25.0V
Power Supply (VEE) ....................... -23.0 to +0.3V
Input Voltage (1) (VT1)................. -0.3 to Vcc +0.3
Input Voltage (2) (VH) ...................... -0.3 to VLCD
Input Voltage (3) (VL)......................... -0.3 to VEE
Input Voltage (4) (VM)...................... -0.3 to +5.0V
Operating temperature (Topr)............ -25 to +75°C
Storage temperature (Tetg)..............-55 to +110°C
Stresses above those listed under ″Absolute
Maximum Ratings″ may cause permanent damage
to this device. These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied or intended. Exposure to the absolute
maximum rating conditions for extended periods
may affect device reliability.
Parameter
Symbol
Ratings
Unit
Notes
Vcc
-0.3 to + 7.0
V
1, 8
VLCD
-0.3 to + 25.0
V
1, 3, 8
VEE
-23.0 to + 0.3
V
1, 4, 8
Input voltage (1)
VT1
-0.3 to Vcc + 0.3
V
1, 2
Input voltage (2)
VH
-0.3 to VLCD
V
1, 5, 8
Input voltage (3)
VL
-0.3 to VEE
V
1, 6, 8
Input voltage (4)
VM
-0.3 to + 5.0
V
1, 7, 8
Operating temperature
Topr
-25 to + 75
°C
-
Storage temperature
Tetg
-55 to + 110
°C
-
Power supply
voltage
Logic circuit
LCD drive circuit
Notes: 1. Indicates the voltage from GND.
2. The input voltage (1) is applicable to DIO1, DISPOFF, SHL, M, MWS0-MWS4, RESET, MODE0,
MODE1, CL, M_S, AMP, CCL, and DIO2.
3. The power supply voltage for LCD drive circuits can be applied to VLCDL/R pins.
4. The power supply voltage for LCD drive circuits can be applied to VEE/R pins.
5. The input voltage (2) is applied to VHL/R pins.
6. The input voltage (3) is applied to VLL/R pins.
7. The input voltage (4) is applied to VML/R pins.
8. See section 8.1 for details.
8.1 Activation and Inactivation Sequence
Make sure to follow activation and inactivation sequence for power supplies and signals as illustrated in the
Figure 8-1. This sequence is applied to the built-in power circuit. It is recommended that users must follow the
sequence correctly; otherwise, the device malfunction, permanent damage, or undesired effects may occur.
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8.1.1
Power On Sequence
1. Power on the power supply in the order listed below:
Power On order: GND-Vcc, GND-VLCD (VH), and VM.
VM-VEE is generated automatically. Input GND power to the DISPOFF pin.
2. The LCD level is forced to output the VM level through the DISPOFF function.
3. The DISPOFF function has a higher priority even if the input signal distortion occurs instantly after Vcc input.
4. Then input the preset signals to get the driver registers initialized. In this case, make sure a period that lasts
more than one frame is reserved.
5. The preceding work for normal display is completed here. At this point, users should cancel the DISPOFF
function by setting the DISPOFF pin to Vcc. The voltage levels of VEE (VL), VLCD (VH) and VM must have
reached the preset voltage respectively.
8.1.2
Power Down Sequence
Shut down the power in an opposite order described for power on sequence on the last page.
1. Firstly, the DISPOFF pin should be set to GND.
2. Secondly, the LCD power supply of GND-VLCD (VH) should be turned off. At the same time, GND-VEE (VL)
gets to VM. Shut off the VM next.
3. Vcc should be set, and the input signal should be set to GND.
4. At this moment, the inputs of pins VEE (VL), VLCD (VH) and VM must go down to 0 V completely.
In addition, an incorrect display may occur at power down or power on. This is because the function of
DISPOFF is inactivated when the Vcc level goes down to GND, which may cause the LCD to output a level
other than VM.
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DC Electrical Characteristics
Vcc
2.5V
2.5V
0ms
VLCD,VH
>0ms
VM
0ms
VEE,VL
0ms
0ms
0ms
0ms
DISPOFF
Input
signal, clock,
or data
Undefined
Initalization
(Longer than one frame
Figure 8-1. IT7020 Power On/Down Scenario
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IT7020C/CY
8.2 DC Electrical Characteristics (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75
°C)
1. The parameter ″ON resistance between Vi Xj″ in the table below indicates a resistance value between of
the X and one of the V pins (either one of VH, VL, or VM) when a load current is applied to one of X1 to
X240 pins. These resistance values are specified under the conditions listed below:
VLCD = VH = 21.75V, VEE = VL =-18.5V, VM = 1.75V, GND = 0V.
Use VH, VL, and VM in the range of VLCD – VM ≥ VH – VM = 21.5 to 7.5V, VEE – VM≤VL – VM = -21.5
to –7.5V in the relation of VH>VM>VL.
2. The current applied between the input and output is removed. The power supply current will increase
through the current flows between the power supplies under the condition that an input to a CMOS gate is
at an intermediate level. Therefore, use VIH = Vcc and VIL = GND.
3. The voltage relationship of each signal is illustrated in Figure 8-2:
Table 8-1. DC Characteristics (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIH
Input high-level
voltage
0.7×Vcc

Vcc
V
VIL
Input low-level
voltage
0

0.3×Vcc
V
Conditions
DIO1, DISPOFF,
SHL, M, M_S,
MWS0~4, RESET
CL, MODE0, MODE1,
AMP, CCL, DIO2
VOH
Output high-level
voltage
Vcc-0.4


V
IOH = -0.4 mA
VOL
Output low-level
voltage


0.4
V
IOL = 0.4 mA
RON
ON resistance
between Vi Xj

0.7
2.0
Input leak current
(1)
-5

5
IIL1
Applicable Pin(s)
M, DOC, DIO1, DIO2
kΩ ION = 150 µA
X1-X240, V pin
µA
DIO1, DISPOFF,
SHL, M, M_S,
MWS0~4, RESET,
CL, MODE0, MODE1,
AMP, CCL, DIO2
IIL2
Input leak current
(2)
-25

25
µA
VH, VL, VM
ICC1
Current
consumption (1)

5
40
µA
Vcc=3.3V,
VLCD - VEE=40V,
FCL=19.2kHZ,
fM=1.5kHz,
ICC2
Current
consumption (2)

10
50
µA
Vcc=5.0V,
VLCD - VEE=40V,
FCL=19.2kHZ,
fM=1.5kHz,
ILCD
Current
consumption (3)

25
100
µA No loading,
Vcc=3.3V,
External charge bump VLCD - VEE=40V,
FCL=19.2kHZ,
fM=1.5kHz,
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IT7020C/CY V0.7
DC Electrical Characteristics
VH: 23.0V
Vcc:3.3V
VM:3.0V
GND:0.0V
VL: -17.0V
Display On
Display Off
Figure 8-32. LCD Common Drive Output Waveform & Voltage Level
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IT7020C/CY V0.7
IT7020C/CY
V0:5.0V
Vcc: 3.3V
VM: 3.0V
V1:1.0V
GND: 0.0V
Dis pla y O n
Dis pla y O ff
Figure 8-3. LCD Segment Drive Output Waveform & Voltage Level
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IT7020C/CY V0.7
AC Characteristics
9. AC Characteristics
9.1 AC Characteristics 1 (Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)
Table 9-1. AC Characteristics 1(Vcc = 2.5 to 5.5V, GND = 0V, VLCD − VEE = 15 to 43V, Ta = −25 to +75 °C)
Symbol
Parameter
Applicable Pins
Min.
Typ.
Max.
Unit
tCYC
Clock cycle time
CL
400

ns
tCWH
CL high-level width
CL
25

ns
tCWL
CL low-level width
CL
370

ns
tr
CL rising time
CL

30
ns
tf
CL falling time
CL

30
ns
tDS
Data set-up time
DIO1, DIO2, CL
100

ns
tDH
Data hold time
DIO1, DIO2, CL
10

ns
tDD
Data output delay time
DIO1, DIO2, CL

200
ns
tMD
M output delay time
M, CL

200
ns
tMS
M setup time
M, CL
20

ns
tMH
M hold time
M, CL
20

ns
tDOC1
DOC delay time 1
DISPOFF, DOC

300
ns
tDOC2
DOC delay time 2
DIO1, DIO2, DOC

300
ns
9.2 AC Characteristics 2 (Vcc = 2.5 to 4.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)
Table 9-2. AC Characteristics 2 (Vcc = 2.5 to 4.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)
Symbol
tpd1
Parameter
Output delay time 1
Applicable Pins
Typ.
X (n), M
Min.
Max.
Unit

1.2
µs
9.3 AC Characteristics 3 (Vcc = 4.5 to 5.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)
Table 9-3. AC Characteristics 3 (Vcc = 4.5 to 5.5V, GND = 0V, VLCD − VEE = 43V, Ta = −25 to +75 °C)
Symbol
tpd1
Parameter
Output delay time 1
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Applicable Pins
X (n), M
23
Typ.
Min.
Max.
Unit

0.7
µs
IT7020C/CY V0.7
IT7020C/CY
Test point
*1: 30 pF
*2: 100 pF
Figure 9-1. AC Characteristics Testing Configuration
tf
CL
tCWL
tr
tCWH
tCYC
0.7 x Vcc
0.3 x Vcc
tDS
tDH
0.7 x Vcc
DIO1
DIO2
0.3 x Vcc
tDD
VOH
DIO1
DIO2
VOL
tMD
VOH
M
(During output)
VOL
tpd1
0.7xVH
0.3xVH
X(n)
0.3xVL
0.7xVL
0.7xVcc
CL
0.3xVcc
tMS
M
(During input)
tMH
0.7xVcc
0.7xVcc
0.3xVcc
0.3xVcc
DISPOFF
0.3xVcc
~
DIO1
DIO2
(During input)
tDOC1
0.3xVcc
tDOC2
0.7xVcc
DOC
0.3xVcc
Figure 9-2. IT7020 Timing Diagram
.
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IT7020C/CY V0.7
Package Information
10. Package Information
TCP Outline Dimensions
unit: mm
INPUT LEAD NAME
NC
VLCDR
VHR
VMR
VLR
VEER
DIO1
M_S
ITE
CCL
CL
GND
SHL
AMP
DISPOFF
DOC
MODE0
MODE1
Vcc
MWS0
MWS1
MWS2
MWS3
MWS4
RESET
IT70
20
M
DIO2
C2
C1
VEO
VEEL
VLL
VML
VHL
VLCDL
NC
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IT7020C/CY V0.7
IT7020C/CY
SHPPING DIRECTION
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IT7020C/CY V0.7
Ordering Information
11. Ordering Information
Part No.
Package
IT7020C/CY
273-TCP
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IT7020C/CY V0.7