ETC IMISG543CYB

SG543
I2C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
PRODUCT FEATURES
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FREQUENCY TABLE (MHz)
Supports Pentium,Pentium II, M2, & K6 CPUs.
Designed to the 440LX specification
Supports Synchronous and Asynchronous PCI.
4 CPU / AGP clocks
Up to 12 SDRAM clocks for 3 DIMMs.
7 PCI synchronous clocks.
Optional common or mixed supply mode:
(VDD = VDDC = VDDP = VDDSD = VDDI = 3.3V)
or (VDD = VDDC = VDDSD = VDDP = 3.3V, VDDI
= VDDC = 2.5)
< 250 pS skew among CPU or SDRAM clocks.
< 250 pS skew among PCI clocks.
2
I C 2-Wire serial interface
Programmable registers featuring:
- Jumperless frequency selection
- enable/disable each output pin
- mode as tri-state, test, or normal
Power Management Capability.
IOAPIC clocks for multiprocessor support.
48 MHz for USB support
Internal Crystal Load Capacitors.
48-pin SSOP package
Spread Spectrum Technology for EMI reduction
REF
IOAPIC
VDDC
B
4
CPU (0:3)
VDDP
S2
S1
S0
dly
6
PCI (0:5)
PCI_F
PLL1
VDDSD [0:2]
MODE
SDATA
SDCLK
B
B
12
SDRAM(0:11)
48 MHz
PLL2
24 MHz
CPU
PCI
0
0
0
50.11
25.06
0
0
1
75.17
30.07
0
1
0
83.52
41.76
0
1
1
69.80
34.90
1
0
0
83.52
33.41
1
0
1
75.17
37.59
1
1
0
60.14
30.07
1
1
1
66.82*
33.41*
VDD
REF0
VSS
XIN
XOUT
VDDP
PCI_F/ S1
PCI0 / S2
VSS
PCI1
PCI2
PCI3
PCI4
VDDP
PCI5 / PS#
VSS
SDRAM11
SDRAM10
VDDSD2
SDRAM9
SDRAM8
VSS
SDATA
SDCLK
VDDI
CS#
PS#
S0
CONNECTION DIAGRAM
REF0
REF1
XOUT
S1
* Supports spread spectrum
BLOCK DIAGRAM
XIN
S2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDI
IOAPIC
REF1 / CS#
VSS
CPU0
CPU1
VDDC
CPU2
CPU3
VSS
SDRAM0
SDRAM1
VDDSD0
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDSD1
SDRAM6
SDRAM7
VSS
48 MHz / S0
24 MHz / Mode
2
NOTE : Purchase of I C components of International Microcircuits,
Inc. or one of its sublicensed Associated Companies conveys a
2
license under the Phillips I C Patent Rights to use these components
2
2
in an I C system, provided that the system conforms to the I C
Standard Specification as defined by Phillips.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 1 of 15
SG543
I2C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
PIN DESCRIPTION
Pin Number
Pin Name
PWR
I/O
Description
4
Xin
VDD
I
5
Xout
PCI_F
VDD
VDDP
O
O
These pins form an on-chip reference oscillator when connected to
terminals of an external parallel resonant crystal (nominally 14.318
MHz). Xin may also serve as input for an externally generated reference
signal. If the external input is used, Pin 5 is left unconnected.
This is a bi-directional pin. During power up, this pin is an input for
frequency selection S1 control bit (see page 1, and app note on page
12) and sets the bit to its initial state. After a fixed period of time (see
S1
VDD
PCI0
VDDP
I
*
O
fig.1, page 3), this pin becomes a low skew PCI clock output that does
2
not stop when PS# (pin 15 or I C register bit) is asserted.
This is a bi-directional pin. During power up, this pin is an input for
frequency selection S2 control bit (see page1,and app note on page 12)
and sets the bit to its initial state. After a fixed period of time (see fig.1,
S2
VDD
PCI (1:4)
PCI5
VDDP
VDDP
I
*
O
O
PS#
VDD
44, 43, 41, 40
CPU(0:3)
VDDC
I
*
O
38, 37, 35, 34, 32, 31,
29, 28, 21, 20, 18, 17
47
SDRAM(0:11)
VDDSD(0:2)
O
page 3), this pin becomes a low skew PCI clock output that stops when
2
PS# (pin 15 or its I C register bit) is asserted.
Low skew (<250 pS) clock outputs for PCI frequencies.
IF MODE=1 this pin becomes low skew (<250 pS) clock outputs for PCI
frequencies.
If MODE=0 then this pin controls whether the PCI clock outputs (except
for PCI-F) are enabled (set to a logic 1) or disabled (set to a logic 0)
Low skew (<250 pS) clock outputs for host frequencies such as CPU,
AGP, Chipset, Cache.
Synchronous DRAM DIM clocks.
IOAPIC
REF1
VDDI
VDD
O
O
CS#
VDD
REF0
48 MHz
VDD
VDD
I
*
O
I/O
S0
VDD
24 MHz
VDD
MODE
VDD
7
8
10, 11, 12, 13
15
46
2
26
I
*
O
25
I
*
Buffered clock of the crystal oscillator (nominally 14.31818 MHz).
IF MODE=1 this pin becomes a buffered copy of the internal crystal
oscillator (nominally 14.31818 MHz)
If MODE=0 then this pin controls whether the CPU clock outputs are
enabled (set to a logic 1) or disabled (set to a logic 0).
This pin is a Buffered output of the crystal reference frequency.
This is a bi-directional pin. During power up, this pin is an input for
frequency selection S0 control bit (see page1,and app note
on page 12) and sets the bit to its initial state. After a fixed period of
time (see fig.1, page 3), this pin becomes a 48 MHz frequency clock.
This is a bi-directional pin. During power up, this pin is an input that
enables (0) or disables (1) the power management shared pins (46 and
15) (see app note on page 12) and sets the bit to its initial state. After a
fixed period of time (see fig.1, page 3), this pin becomes a 24 MHz
frequency clock.
*A 10K ohm resistor to VDD or VSS is required to insure that the device’s internal storage registers are correctly set at
power up.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 2 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
PIN DESCRIPTION (Cont.)
Pin Number
Pin Name
PWR
I/O
23
24
3, 9, 16, 22, 27, 33,
39, 45
1
SDATA
SDCLK
VSS
VDD
VDD
-
I
I
P
Serial Data for I C 2-wire control interface. Has internal pull-up.
2
Serial Clock of I C 2-wire control interface. Has internal pull-up.
Ground pins for the chip.
Description
VDD
-
P
48
6, 14
36, 30, 19
42
VDDI
VDDP
VDDSD [0:2]
VDDC
-
P
P
P
P
Power supply pins for analog circuit, core logic and reference clock
buffers.
Power supply pin for IOAPIC clock. May be either 3.3 or 2.5 Volts.
2
3.3 volt power for PCI clocks.
3.3 volt power for SDRAM clocks
Power supply pin for CPU clocks may be either 2.5 V or 3.3V
A bypass capacitor (0.1µ
µF) should be placed as close as possible to each VDD, VDDSD, VDDI, and VDDP pin. If
these bypass capacitors are not close to the pins their high frequency filtering characteristic will be canceled by
the lead inductances of the traces.
VDD
Power Supply
PCI_F / S1
PCI0 / S2
48 MHz / S0
24 MHz / MODE
toggle , outputs
Hi-Z (tristate), inputs
Fig.1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 3 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
POWER MANAGEMENT FUNCTIONS
When MODE=0, pins 15 and 46 are inputs PS# (PCI_STOP#), and CS# (CPU_STOP#), respectively (when MODE=1,
these functions are not available). A particular output is enabled only when both the serial interface and these pins
indicate that it should be enabled. The IMISG543 clocks may be disabled according to the following table in order to
reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions
from running to stopped. The CPU/AGP and PCI clocks transition between running and stopped by waiting for one
positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are
either enabled or disabled.
CPU_STOP#
PCI_STOP#
CPU
PCI
OTHER CLKs
XTAL & VCOs
0
0
LOW
LOW
RUNNING
RUNNING
0
1
LOW
RUNNING
RUNNING
RUNNING
1
0
RUNNING
LOW
RUNNING
RUNNING
1
1
RUNNING
RUNNING
RUNNING
RUNNING
Please note that all clocks can be individually asynchronously enabled or stopped via the 2-wire I2C control interface. In
this case all clocks are stopped in the low state.
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
Fig. 2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 4 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
2-WIRE I2C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The IMISG543 cannot be read back. Sub-addressing
is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control
interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The IMISG543 will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal
on the SDATA wire following reception of each byte. The IMISG543 will not respond to any other control interface
conditions. Previously set control registers are retained.
SERIAL CONTROL REGISTERS
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power
up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2, ....) will be valid and acknowledged.
Byte 0: Frequency, Function Select Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
1
0
0
Pin#
*
*
*
*
*
*
Description
Reserved
S2 (for frequency table selection by software via I2C)
S1 (for frequency table selection by software via I2C)
S0 (for frequency table selection by software via I2C)
2
enables freq. selection by hardware (set to 0) or software I C (set to 1)
Reserved
Bit1 Bit0
1
1
Tri-State
1
0
Spread-On Normal Operation
0
1
Test Mode
0
0
Spread-Off Normal Operation
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 5 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
SERIAL CONTROL REGISTERS (Cont.)
Function Table
Function
Description
Tri-State
Normal
1
Test Mode
CPU
Hi-Z
see table
TCLK/2
PCI
Hi-Z
see table
TCLK/4
Outputs
SDRAM
Hi-Z
CPU
TCLK/2
Ref
Hi-Z
14.318
TCLK
IOAPIC
Hi-Z
14.318
TCLK
Notes:
1. Tclk is a test clock over driven on the Xin input during test mode.
Byte 1: CPU, SIO, USB Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
x
1
1
1
1
Pin#
26
25
40
41
43
44
Description
48 MHz enable/Stopped
24 MHz enable/Stopped
0 = Reserved for IMI TEST. 1 = normal operation.
Reserved
CPUCLK3 enable/Stopped
CPUCLK2 enable/Stopped
CPUCLK1 enable/Stopped
CPUCLK0 enable/Stopped
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
x
1
1
1
1
1
1
1
Pin#
7
15
13
12
11
10
8
Description
Reserved
PCI_F enable/Stopped
PCI5 enable/Stopped
PCI4 enable/Stopped
PCI3 enable/Stopped
PCI2 enable/Stopped
PCI1 enable/Stopped
PCI0 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 6 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
SERIAL CONTROL REGISTERS (Cont.)
Byte 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped )
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
28
29
31
32
34
35
37
38
Description
SDRAM7 enable/Stopped
SDRAM6 enable/Stopped
SDRAM5 enable/Stopped
SDRAM4 enable/Stopped
SDRAM3 enable/Stopped
SDRAM2 enable/Stopped
SDRAM1 enable/Stopped
SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
x
x
x
x
1
1
1
1
Pin#
17
18
20
21
Description
Reserved
Reserved
Reserved
Reserved
SDRAM11 enable/Stopped
SDRAM10 enable/Stopped
SDRAM9 enable/Stopped
SDRAM8 enable/Stopped
Byte 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
x
x
x
1
x
x
x
1
Pin#
47
46
2
Description
Reserved
Reserved
Reserved
IOAPIC enable/Stopped
Reserved
Reserved
REF1 / CS# enable/Stopped
REF0 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 7 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
SPREAD SPECTRUM CLOCKING
Amplitude
(dB)
Without Spectrum Spread
With Spectrum Spread
Spectrum Analysis
Frequency(MHz)
Center
SPECTRUM SPREADING SELECTION TABLE
Min (MHz)
Center
(MHz)
Max (MHz)
CPU Frequency
% of Frequency Spreading
Mode
65.98
66.82
67.66
66 MHz
-/+ 1.25%
Center
MAXIMUM RATINGS
Voltage Relative to VSS:
-0.3V
Voltage Relative to VDD:
0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +70ºC
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 8 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL
-
-
0.8
Vdc
-
Input High Voltage
VIH
2.0
-
Input Low Current
IIL
-
Vdc
-
-66
µA
Input High Current
IIH
5
µA
Tri-State leakage Current
Ioz
-
-
10
µA
Dynamic Supply Current
Idd
-
-
220
mA
Static Supply Current
Isdd
-
-
35
mA
-
Short Circuit Current
ISC
25
-
-
mA
1 output at a time - 30 seconds
CPU = 66.6 MHz, PCI = 33.3 MHz
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
SWITCHING CHARACTERISTICS
Characteristic
Symbol
Output Duty Cycle
CPU/SDRAM to PCI Offset
Min
Typ
Max
Units
Conditions
-
45
50
55
%
Measured at 1.5V
tOFF
1
-
4
ns
15 pf Load Measured at 1.5V
Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM)
tSKEW1
-
-
+250
pS
15 pf Load Measured at 1.5V
Skew (CPU-SDRAM)
tSKEW2
-
-
+500
pS
15 pf Load Measured at 1.5V
∆Period Adjacent Cycles
∆P
-
-
+250
pS
-
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
500
KHz
Overshoot/Undershoot
Beyond Power Rails
Vover
-
1.5
V
22 ohms @ source of 8 inch PCB run
to 15 pf load
Ring Back Exclusion
VRBE
0.7
2.1
V
note1
-
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
note 1: Ring Back must not enter this range.
JITTER CHARACTERISTICS
Device
Maximum
Conditions
CPU, SDRAM
250 pS
15 pF
PCI
500 pS
30 pF
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 9 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
TB40AX_V TYPE BUFFER CHARACTERISTICS FOR CPU (0:3)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
22
-
31
mA
Vout = VDD -.5V
Pull-Up Current Max
IOHmax
37
-
56
mA
Vout = 1.25V
Pull-Down Current Min
IOLmin
30
-
41
mA
Vout = 0.4V
Pull-Down Current Max
IOLmax
75
-
109
mA
Vout = 1.2V
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRFmin
0.4
-
-
nS
10 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRFmax
-
-
1.6
nS
20 pF Load
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = 2.5 + 5%, TA = 0ºC to +70ºC
TB40AX TYPE BUFFER CHARACTERISTICS FOR REF0 and SDRAM(0:11)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
30
-
39
mA
Vout = VDD - .5V
Pull-Up Current Max
IOHmax
44
-
64
mA
Vout = 1.5V
Pull-Down Current Min
IOLmin
30
-
40
mA
Vout = 0.4V
Pull-Down Current Max
IOLmax
75
-
103
mA
Vout = 1.2V
Rise/Fall Time Min
Between 0.4 V and 2.4 V
TRFmin
0.5
-
-
nS
20 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.4 V
TRFmax
-
-
1.3
nS
30 pF Load
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 10 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
BT4LP112C TYPE BUFFER CHARACTERISTICS FOR PCICLK(0:5,F) AND REF1
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
18
-
23
mA
Vout = VDD - .5V
Pull-Up Current Max
IOHmax
44
-
64
mA
Vout = 1.5V
Pull-Down Current Min
IOLmin
18
-
25
mA
Vout = 0.4V
Pull-Down Current Max
IOLmax
50
-
70
mA
Vout = 1.5V
Rise/Fall Time Min
Between 0.4 V and 2.4 V
TRFmin
0.5
-
-
nS
15 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.4 V
TRFmax
-
-
2.0
nS
30 pF Load
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
TB4L1_V TYPE BUFFER CHARACTERISTICS FOR IOAPIC
Characteristic
Symbol
Min
Typ
Max
Units
Pull-Up Current Min
IOHmin
13
-
20
mA
Vout = VDD - .5V
Pull-Up Current Max
IOHmax
22
-
37
mA
Vout = 1.25V
Pull-Down Current Min
IOLmin
18
-
23
mA
Vout = 0.4V
Pull-Down Current Max
IOLmax
50
-
61
mA
Vout = 1.5V
TRF
0.4
-
1.6
nS
20 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.4 V
Conditions
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
BT5LP1 TYPE BUFFER CHARACTERISTICS FOR 24M, 48M
Characteristic
Symbol
Min
Typ
Max
Units
Pull-Up Current Min
IOHmin
13
-
17
mA
Vout = VDD - .5V
Pull-Up Current Max
IOHmax
30
-
44
mA
Vout = 1.5V
Pull-Down Current Min
IOLmin
13
-
19
mA
Vout = 0.4V
Pull-Down Current Max
IOLmax
32
-
44
mA
Vout = 1.5V
TRF
-
-
2.0
nS
20 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.4 V
Conditions
VDD = VDDP = VDDSD(0:2) =3.3V ±5%, VDDC = VDDI = 2.5 + 5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 11 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
CRYSTAL AND REFERENCE OSCILLATOR PARAMETERS
Characteristic
Symbol
Min
Typ
Max
Units
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
Calibration note 1
TS
-
-
+/- 100
PPM
Stability (Ta -10 to +60C) note 1
TA
-
-
5
PPM
Aging (first year @ 25C) note 1
Mode
Pin Capacitance
OM
CP
-
36
-
DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Startup time
Ts
-
-
30
µS
Load Capacitance
CL
-
20
-
pF
Effective Series
resistance (ESR)
R1
-
-
40
Ohms
Power Dissipation
DL
-
-
0.10
mW
pF
Conditions
Parallel Resonant
Capacitance of XIN and Xout pins to
ground (each)
the crystals rated load. note 1
note 1
crystals internal package
Shunt Capacitance
CO
-8
pF
capacitance (total)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
= 2.0 pF
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore = 18.0 pF
the total parasitic capacitance would therefore be
= 20.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 12 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
APPLICATION NOTE FOR SELECTION ON BIDIRECTIONAL PINS
Pins 7, 8, 25 and 26 are Power up bidirectional pins and
are used for selecting different functions in this device
(see Pin description, Page 2). During power-up of the
device, these pins are in input mode (see Fig1, page4),
therefore, they are considered input select pins internal
to the IC, these pins have a large value pull-up each
(250KΩ), therefore, a selection “1” is the default. If the
system uses a slow power supply (over 5mS settling
time), then it is recommended to use an external Pullup
(Rup) in order to insure a high selection. In this case,
the designer may choose one of two configurations, see
FIG.3A and Fig. 3B.
Vdd
Rd
Load
Bidirectional
JP1
JUMPER
FIG.3A
Rdn
5K
Fig 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.3A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd) close
to the pin.
Fig 3B represents a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads 1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rup
50K
IMISG543
Vdd
IMISG543
JP2
3 Way Jumper
Rsel
10K
Rd
Load
Bidirectional
If the system power supply is fast (less than 5mS
settling time), then FIG3A only applies and Pull up Rup
resistor is not necessary.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
FIG.3B
Rev.1.7
8/14/98
Page 13 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
PCB LAYOUT SUGGESTION
IMISG543
Via to VDD Island
1
VCC
Via to GND plane
FB1
Via to VCC plane
C35
C34
22µF
C36
C37
C38
VCC1
FB3
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
C3
FB2
VCC2
C4
C5
C40
22µF
C39
C41
22µF
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 14 of 15
SG543
2
I C Clock Generator for 3 DIMM, Pentium, Pentium II & Pro Boards.
Approved Product
PACKAGE DRAWING AND DIMENSIONS
48 PIN SSOP OUTLINE DIMENSIONS
INCHES
C
L
SYMBOL
H
E
D
MIN
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.20
0.31
0.41
A2
0.085
0.090
0.095
2.16
2.29
2.41
b
0.008
0.010
0.0135
0.203
0.254
0.343
c
0.005
.008
0.010
0.127
0.20
0.254
D
0.620
0.625
0.637
15.75
15.88
16.18
E
0.291
0.295
0.299
7.39
7.49
7.59
a
A2
A
e
A1
B
MILLIMETERS
e
0.0256 BSC
0.640 BSC
H
0.395
0.408
0.420
10.03
10.36
10.67
L
0.024
0.030
0.040
0.61
0.76
1.02
a
0º
4º
8º
0º
4º
8º
ORDERING INFORMATION
Part Number
Package Type
IMISG543CYB
48 PIN SSOP
Note:
Production Flow
Commercial, 0ºC to +70ºC
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example:
IMI
SG543CYB
Date Code, Lot #
IMISG543CYB
Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
Page 15 of 15