19-0513; Rev 0; 5/06 KIT ATION EVALU E L B A AVAIL High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Features The MAX19588 is a 3.3V, high-speed, high-performance analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 16-bit converter core. The MAX19588 is optimized for multichannel, multimode receivers, which require the ADC to meet very stringent dynamic performance requirements. With a -82dBFS noise floor, the MAX19588 allows for the design of receivers with superior sensitivity requirements. At 100Msps, the MAX19588 achieves a 79dB signal-tonoise ratio (SNR) and an 82.1dBc/97.7dBc single-tone spurious-free dynamic range performance (SFDR1/ SFDR2) at fIN = 70MHz. The MAX19588 is not only optimized for excellent dynamic performance in the 2nd Nyquist region, but also for high-IF input frequencies. For instance, at 130MHz, the MAX19588 achieves an 82.3dBc SFDR and its SNR performance stays flat (within 2.3dB) up to 175MHz. This level of performance makes the part ideal for high-performance digital receivers. The MAX19588 operates from a 3.3V analog supply voltage and a 1.8V digital voltage, features a 2.56VP-P full-scale input range, and allows for a guaranteed sampling speed of up to 100Msps. The input track-and-hold stage operates with a 600MHz full-scale, full-power bandwidth. ♦ 100Msps Conversion Rate ♦ -82dBFS Noise Floor ♦ Excellent Low-Noise Characteristics SNR = 79.4dB at fIN = 10MHz SNR = 79dB at fIN = 70MHz ♦ Excellent Dynamic Range (SFDR1/SFDR2) 93.2dBc/102.5dBc at fIN = 10MHz 82.1dBc/97.7dBc at fIN = 70MHz ♦ Less than 0.1ps Sampling Jitter ♦ 1275mW Power Dissipation ♦ 2.56VP-P Fully Differential Analog Input Voltage Range ♦ CMOS-Compatible Two’s-Complement Data Output ♦ Separate Data Valid Clock and Over-Range Outputs ♦ Flexible Input Clock Buffer ♦ Small 56-Pin, 8mm x 8mm x 0.8mm Thin QFN Package ♦ EV Kit Available for MAX19588 (Order MAX19588EVKIT) Ordering Information PART TEMP RANGE PIN-PACKAGE The MAX19588 features parallel, low-voltage CMOScompatible outputs in two’s-complement output format. MAX19588ETN-D -40°C to +85°C 56 Thin QFN-EP* T5688-2 The MAX19588 is manufactured in an 8mm x 8mm, 56-pin thin QFN package with exposed paddle (EP) for low thermal resistance, and is specified for the extended industrial (-40°C to +85°C) temperature range. MAX19588ETN+D -40°C to +85°C 56 Thin QFN-EP* T5688-2 Applications PKG CODE +Denotes lead-free package. D = Dry pack. *EP = Exposed paddle. Pin Configuration Cellular Base-Station Transceiver Systems (BTS) Multistandard Receivers E911 Location Receivers High-Performance Instrumentation Antenna Array Processing DVDD DGND DGND D0 D1 D2 D3 D4 D5 D6 D7 D8 TOP VIEW DVDD Multicarrier Receivers DVDD Wireless Local Loop (WLL) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D9 43 28 AGND D10 44 27 REFIN D11 45 26 REFOUT D12 46 25 AVDD D13 47 24 AVDD D14 48 23 AVDD 22 AGND D15 49 MAX19588 DAV 50 21 AGND DVDD 51 20 AGND DGND 52 19 AVDD 18 AVDD DOR 53 N.C. 54 17 AVDD EP 16 N.C. AVDD 55 15 N.C. 10 11 12 13 14 AGND CLKN 9 AGND CLKP 8 AGND AGND 7 INN AVDDA 6 INP 5 AGND 4 AGND 3 AGND 2 AGND 1 AVDDA AVDD 56 THIN QFN 8mm x 8mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19588 General Description MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor ABSOLUTE MAXIMUM RATINGS AVDD, AVDDA to AGND ........................................ -0.3V to +3.6V DVDD to DGND..................................................... -0.3V to +2.4V AGND to DGND.................................................... -0.3V to +0.3V INP, INN, CLKP, CLKN, REFP, REFN, REFIN, REFOUT to AGND....................-0.3V to (AVDD + 0.3V) D0–D15, DAV, DOR to GND ....................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 56-Pin Thin QFN-EP (derate 47.6mW/°C above +70°C) .........................3809.5mW Operating Temperature Range ..........................-40°C to +85°C Thermal Resistance θJA ..................................................21°C/W Thermal Resistance θJC .................................................0.6°C/W Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0–D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution N 16 Offset Error VOS 0 Gain Error GE -3.5 10 Bits 20 mV +3.5 %FS ANALOG INPUTS (INP, INN) Input Voltage Range VDIFF Fully differential input, VIN = VINP - VINN 2.56 VP-P Common-Mode Voltage VCM Internally self-biased 2.4 V Differential Input Resistance RIN 10 ±20% kΩ Differential Input Capacitance CIN Full-Power Analog Bandwidth BW-3dB 7 pF 600 MHz 1.28 ±10% V 1.28 V AIN < -35dBFS -82 dBFS fIN = 10MHz, AIN = -2dBFS 79.4 -3dB rolloff for FS Input REFERENCE INPUT/OUTPUT (REFIN, REFOUT) Reference Input Voltage Range REFIN Reference Output Voltage REFOUT DYNAMIC SPECIFICATIONS (fCLK = 100Msps) Thermal Plus Quantization Noise Floor Signal-to-Noise Ratio (First 4 Harmonics Excluded) (Note 2) 2 NF SNR fIN = 70MHz, AIN = -2dBFS, TA = +25°C 77.5 fIN = 70MHz, AIN = -2dBFS 75.3 79 79 fIN = 105MHz, AIN = -2dBFS 78.3 fIN = 130MHz, AIN = -2dBFS 77.5 fIN = 168MHz, AIN = -2dBFS 76.6 _______________________________________________________________________________________ dB High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0–D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP 75 77.1 73.5 77.1 fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25°C Signal-to-Noise Plus Distortion (Note 2) Spurious-Free Dynamic Range (Worst Harmonic, 2nd and 3rd) SINAD SFDR1 fIN = 70MHz, AIN = -2dBFS 77.1 fIN = 130MHz, AIN = -2dBFS 75.8 fIN = 168MHz, AIN = -2dBFS 70.8 79.6 79.3 fIN = 130MHz, AIN = -2dBFS Spurious-Free Dynamic Range (Worst Harmonic, 4th and Higher) (Note 2) Second-Order Harmonic Distortion SFDR2 Third-Order Intermodulation Distortion Two-Tone SFDR HD3 IM3 TTSFDR dBc 82.3 75.4 fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25°C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS 102.5 97.7 97.7 94.2 90.4 85 dBc 94.1 fIN = 168MHz, AIN = -2dBFS 91.5 fIN = 10MHz, AIN = -2dBFS -94.3 fIN = 70MHz, AIN = -2dBFS, TA = +25°C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS -93 -93 -88 fIN = 130MHz, AIN = -2dBFS Third-Order Harmonic Distortion dB 93.2 82.1 82.1 86.6 fIN = 168MHz, AIN = -2dBFS fIN = 130MHz, AIN = -2dBFS HD2 UNITS 79 fIN = 105MHz, AIN = -2dBFS fIN = 10MHz, AIN = -2dBFS fIN = 70MHz, AIN = -2dBFS, TA = +25°C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS MAX -83 -78.3 dBc -82.3 fIN = 168MHz, AIN = -2dBFS -77.6 fIN = 10MHz, AIN = -2dBFS -94.3 fIN = 70MHz, AIN = -2dBFS, TA = +25°C fIN = 70MHz, AIN = -2dBFS fIN = 105MHz, AIN = -2dBFS -82.1 -82.1 -87.4 fIN = 130MHz, AIN = -2dBFS -92.5 fIN = 168MHz, AIN = -2dBFS -75.4 fIN1 = 65.1MHz, AIN1 = -8dBFS fIN2 = 70.1MHz, AIN2 = -8dBFS -87.7 dBc 98 dBFS fIN1 = 65.1MHz, fIN2 = 70.1MHz, -100dBFS < AIN < -10dBFS -79.6 -79.3 dBc CONVERSION RATE Maximum Conversion Rate fCLKMAX Minimum Conversion Rate fCLKMIN Aperture Jitter tJ 100 MHz 20 85 MHz fsRMS _______________________________________________________________________________________ 3 MAX19588 ELECTRICAL CHARACTERISTICS (continued) MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor ELECTRICAL CHARACTERISTICS (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven differentially, CL = 5pF at digital outputs (D0–D15, DOR), CL = 15pF for DAV, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLOCK INPUTS (CLKP, CLKN) Differential Input Swing VDIFFCLK Fully differential inputs Common-Mode Voltage VCMCLK Self-biased 1.0 to 5.0 VP-P 1.6 V Differential Input Resistance RINCLK 10 kΩ Differential Input Capacitance CINCLK 3 pF CMOS-COMPATIBLE DIGITAL OUTPUTS (D0–D15, DOR, DAV) Digital Output High Voltage VOH ISOURCE = 200µA Digital Output Low Voltage VOL ISINK = 200µA DVDD 0.2 V 0.2 V TIMING SPECIFICATIONS (Figures 4, 5), CL = 7.5pF (D0–D15, DOR); CL = 35pF (DAV) CLKP - CLKN High tCLKP (Note 3) 4 CLKP - CLKN Low tCLKN (Note 3) 4 ns ns Effective Aperture Delay tAD -300 ps Output Data Delay tDAT 3.4 ns Data Valid Delay tDAV Pipeline Latency (Note 3) 2.5 tLATENCY 4 5.2 7 CLKP Rising Edge to DATA Not Valid tDNV (Note 3) CLKP Rising Edge to DATA Guaranteed Valid tDGV (Note 3) ns Clock Cycles 1.1 ns 7.5 ns DATA Setup Time Before Rising DAV tS Clock duty cycle = 50% (Note 3) 2 ns DATA Hold Time After Rising DAV tH Clock duty cycle = 50% (Note 3) 2.5 ns POWER SUPPLIES Analog Power-Supply Voltage AVDD, AVDDA 3.13 3.3 3.46 V Digital Output Power-Supply Voltage DVDD 1.7 1.8 1.9 V IAVDD + IAVDDA 369 450 mA Digital Output Power-Supply Current IDVDD 31 42 mA Power Dissipation PDISS 1275 1561 mW Analog Power-Supply Current Note 1: TA ≥ +25°C guaranteed by production test, TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C. Note 2: AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier are excluded. For SNR and SINAD measurements, bins dominated by production test system noise are excluded. Note 3: Parameter guaranteed by design and characterization. 4 _______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor FFT PLOT (524,288-POINT DATA RECORD) -60 -80 3 2 -100 82 SNR 80 -40 78 -60 -80 2 3 -100 0 5 68 0 10 15 20 25 30 35 40 45 10 15 20 25 30 35 40 45 5 0 40 60 80 100 120 140 160 180 ANALOG INPUT FREQUENCY (MHz) fIN (MHz) SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) HD2/HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) SNR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) HD3 -80 80 85 SNR (dB, dBFS) HD2/HD3 (dBc) 90 -90 HD2 -100 SNR (dBFS) 70 100 95 MAX19588toc06 SFDR2 90 MAX19588toc05 -70 MAX19588toc04 105 60 50 40 SNR (dB) 30 80 20 -110 SFDR1 75 10 0 -120 70 0 20 40 60 0 80 100 120 140 160 180 20 40 60 -80 80 100 120 140 160 180 -70 -60 -50 -40 -30 -20 -10 fIN (MHz) fIN (MHz) ANALOG INPUT AMPLITUDE (dBFS) SFDR1 vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) SFDR2 vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 10MHz) SNR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN = 70MHz) 100 SFDR2 (dBc, dBFS) SFDR1 (dBFS) 90 80 70 SFDR1 (dBc) 60 50 SFDR = 90dB REFERENCE LINE 40 30 -80 -70 -60 -50 -40 -30 -20 -10 ANALOG INPUT AMPLITUDE (dBFS) 0 120 110 100 90 80 70 60 50 40 30 20 10 0 90 SFDR2 (dBFS) 80 SFDR2 (dBc) SNR (dBFS) 70 SNR (dB, dBFS) 110 MAX19588toc08 MAX19588toc07 120 0 MAX19588toc09 SFDR1/SFDR2 (dBc) 20 ANALOG INPUT FREQUENCY (MHz) 110 SFDR1 (dBc, dBFS) SINAD 74 70 -140 -140 76 72 -120 -120 MAX19588 toc03 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 fCLK = 100MHz fIN = 130.001MHz AIN = -1.98dBFS SNR/SINAD (dB) fCLK = 100MHz fIN = 70.164MHz AIN = -1.94dBFS -20 0 MAX19588 toc01 0 SNR/SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 100MHz, AIN = -2dBFS) MAX19588 toc02 FFT PLOT (524,288-POINT DATA RECORD) 60 50 SNR (dB) 40 30 SFDR = 90dB REFERENCE LINE 20 10 0 -80 -70 -60 -50 -40 -30 -20 -10 ANALOG INPUT AMPLITUDE (dBFS) 0 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) _______________________________________________________________________________________ 5 MAX19588 Typical Operating Characteristics (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0–D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records.) Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0–D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records.) SFDR1 vs. ANALOG INPUT AMPLITUDE SFDR2 vs. ANALOG INPUT AMPLITUDE SNR/SINAD vs. SAMPLING FREQUENCY (fCLK = 100MHz, fIN = 70MHz) (fCLK = 100MHz, fIN = 70MHz) (fIN = 10MHz, AIN = -2dBFS) 40 30 20 10 SFDR = 90dB REFERENCE LINE 0 -80 -70 -60 -50 -40 -30 -10 MAX19588toc12 SNR 79 SFDR2 (dBc) SFDR = 90dB REFERENCE LINE 77 SINAD 76 75 74 73 72 71 -70 -60 -50 -40 -30 -20 -10 0 20 30 40 50 60 70 80 90 100 110 ANALOG INPUT AMPLITUDE (dBFS) fCLK (MHz) SFDR1/SFDR2 vs. SAMPLING FREQUENCY (fIN = 10MHz, AIN = -2dBFS) HD2/HD3 vs. SAMPLING FREQUENCY (fIN = 10MHz, AIN = -2dBFS) SNR/SINAD vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) -80 HD2/HD3 (dBc) 100 95 90 SFDR1 85 SNR 80 HD3 78 -85 -90 -95 HD2 -100 -105 80 MAX19588toc15 -75 SNR/SINAD (dB) SFDR2 82 MAX19588toc14 -70 MAX19588toc13 105 76 74 SINAD 72 -110 75 70 -115 70 68 -120 20 30 40 50 60 70 80 20 90 100 110 30 40 50 60 70 80 20 90 100 110 30 40 50 60 70 80 90 100 110 fCLK (MHz) fCLK (MHz) fCLK (MHz) SFDR1/SFDR2 vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) HD2/HD3 vs. SAMPLING FREQUENCY (fIN = 70MHz, AIN = -2dBFS) SNR/SINAD vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) HD3 82 MAX19588toc18 100 -75 MAX19588toc17 -70 MAX19588toc16 105 SNR 80 HD2/HD3 (dBc) SFDR2 90 SFDR1 85 SNR/SINAD (dB) -80 95 80 -85 -90 -95 78 SINAD 76 HD2 -100 75 74 -105 70 72 -110 20 30 40 50 60 70 fCLK (MHz) 6 80 78 -80 0 81 ANALOG INPUT AMPLITUDE (dBFS) 110 SFDR1/SFDR2 (dBc) -20 SFDR2 (dBFS) SNR/SINAD (dB) SFDR1 (dBc) 120 110 100 90 80 70 60 50 40 30 20 10 0 MAX19588toc11 100 90 80 70 60 50 SFDR2 (dBc, dBFS) SFDR1 (dBFS) 110 SFDR1 (dBc, dBFS) MAX19588toc10 120 SFDR/SFDR2 (dB) MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor 80 90 100 110 20 30 40 50 60 70 fCLK (MHz) 80 90 100 110 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor HD2/HD3 vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) SFDR2 105 82 MAX19588toc20 -80 MAX19588toc19 110 SNR/SINAD vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) -85 SNR 80 90 SFDR1 85 -90 SNR/SINAD (dB) HD2/HD3 (dBc) HD2 -95 HD3 -100 78 76 SINAD 80 74 -105 -110 70 10 35 60 72 -40 85 -15 35 60 85 -40 SFDR1/SFDR2 vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) SFDR2 -70 -80 HD2/HD3 (dBc) 100 90 80 HD3 -75 -85 -90 -95 HD2 -100 SFDR1 -105 70 1290 60 85 -15 TEMPERATURE (°C) 1.29 1.28 1.27 1.26 1.25 1.24 -40 -15 10 35 TEMPERATURE (°C) 60 85 IAVDD + IAVDDA, PDISS (mA, mW) REFERENCE VOLTAGE (V) 1.30 1270 1260 1250 10 35 60 -40 85 -15 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 35 REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS PDISS 10 TEMPERATURE (°C) POWER DISSIPTATION vs. ANALOG SUPPLY VOLTAGE MAX19588toc25 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS 85 1280 TEMPERATURE (°C) REFERENCE VOLTAGE vs. TEMPERTURE 1.31 60 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS 1230 -40 1.280 IAVDD + IAVDDA fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS 1.279 1.278 REFERENCE VOLTAGE (V) 35 85 1240 MAX19588toc26 10 60 1300 -115 -15 35 POWER DISSIPATION vs. TEMPERATURE -110 60 10 TEMPERATURE (°C) HD2/HD3 vs. TEMPERATURE (fCLK = 100MHz, fIN = 70.1MHz, AIN = -2dBFS) MAX19588toc22 110 -40 -15 TEMPERATURE (°C) TEMPERATURE (°C) SFDR1/SFDR2 (dBc) 10 POWER DISSIPATION (mW) -15 MAX19588toc23 -40 MAX19588toc24 75 MAX19588toc27 SFDR1/SFDR2 (dBc) 100 95 MAX19588toc21 SFDR1/SFDR2 vs. TEMPERATURE (fCLK = 100MHz, fIN = 10.1MHz, AIN = -2dBFS) 1.277 1.276 1.275 1.274 1.273 1.272 1.271 1.270 3.15 3.20 3.25 3.30 3.35 3.40 ANALOG SUPPLY VOLTAGE (V) 3.45 3.15 3.20 3.25 3.30 3.35 3.40 3.45 ANALOG SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX19588 Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0–D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records.) Typical Operating Characteristics (continued) (AVDD = AVDDA = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL = 7.5pF at digital outputs (D0–D15, DOR), CL = 35pF for DAV, fCLK = 100MHz, TA = +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records.) 100 SNR 77 76 SINAD 75 -80 95 SFDR2 90 85 80 74 3.25 3.30 3.35 3.40 3.45 -110 3.15 ANALOG SUPPLY VOLTAGE (V) 3.20 3.25 3.30 3.35 3.40 3.45 -20 -40 fIN2 fIN1 fIN2 - fIN1 -80 -20 -40 fIN1 -60 -80 2fIN1 - fIN2 fIN2 2fIN2 - fIN1 -120 -120 5 0 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TWO-TONE SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN1 = 10.1MHz, fIN2 = 15.1MHz) TWO-TONE SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 100MHz, fIN1 = 65.1MHz, fIN2 = 70.1MHz) MAX19588toc33 0 TTSFDR (dBFS) TTSFDR (dBc, dBFS) TTSFDR (dBc, dBFS) 3.35 -100 -100 TTSFDR (dBc) TTSFDR = 90dB REFERENCE LINE -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) 8 3.30 fCLK = 100MHz fIN1 = 70.102MHz AIN = -8.03dBFS fIN2 = 65.097MHz AIN2 = -8.13dBFS IM3 = -87.7dBc 2fIN2 - fIN1 120 110 100 90 80 70 60 50 40 30 20 10 0 3.25 3.40 ANALOG SUPPLY VOLTAGE (V) 0 AMPLITUDE (dBFS) fCLK = 100MHz fIN1 = 10.098MHz AIN1 = -7.95dBFS fIN2 = 14.871MHz AIN2 = -8.01dBFS IM3 = -104.1dBc 3.20 TWO-TONE SFDR PLOT (32,786-POINT DATA RECORD) MAX19588 toc31 0 AMPLITUDE (dBFS) 3.15 ANALOG SUPPLY VOLTAGE (V) TWO-TONE SFDR PLOT (32,786-POINT DATA RECORD) -60 HD2 MAX19588 toc32 3.20 -95 -105 70 3.15 HD3 -90 -100 SFDR1 75 73 -85 120 110 100 90 80 70 60 50 40 30 20 10 0 MAX19588toc34 78 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS -75 HD2/HD3 (dBc) 79 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS 105 SFDR1/SFDR2 (dBc) 80 -70 MAX19588toc29 fCLK = 100MHz fIN = 70.1MHz AIN = -2dBFS HD2/HD3 vs. ANALOG SUPPLY VOLTAGE 110 MAX19588toc28 81 SFDR1/SFDR2 vs. ANALOG SUPPLY VOLTAGE MAX19588toc30 SNR/SINAD vs. ANALOG SUPPLY VOLTAGE SNR/SINAD (dB) MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor TTSFDR (dBFS) TTSFDR (dBc) TTSFDR = 90dB REFERENCE LINE -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) _______________________________________________________________________________________ 3.45 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor PIN NAME FUNCTION 1, 2 AVDDA Auxiliary Analog Supply Voltage. Connect these pins together and connect to AVDD through a 50Ω series resistor. 3, 6–9, 12, 13, 14, 20, 21, 22, 28 AGND Converter Ground. Analog, digital, and output-driver grounds are internally connected to the same potential. Connect the converter’s exposed paddle (EP) to GND. 4 CLKP Differential Clock, Positive Input Terminal 5 CLKN Differential Clock, Negative Input Terminal 10 INP Differential Analog Input, Positive Terminal 11 INN Differential Analog Input, Negative Terminal 15, 16, 54 N.C. No Connection. Do not connect to this pin. 17, 18, 19, 23, 24, 25, 55, 56 AVDD Analog Supply Voltage. Provide local bypassing to ground with 0.01µF and 0.1µF capacitors. 26 REFOUT 27 REFIN Reference Voltage Input 29, 41, 42, 51 DVDD Digital Supply Voltage. Provide local bypassing to ground with 0.01µF and 0.1µF capacitors. 30, 31, 52 DGND 32 D0 Digital CMOS Output Bit 0 (LSB) 33 D1 Digital CMOS Output Bit 1 34 D2 Digital CMOS Output Bit 2 35 D3 Digital CMOS Output Bit 3 36 D4 Digital CMOS Output Bit 4 37 D5 Digital CMOS Output Bit 5 38 D6 Digital CMOS Output Bit 6 39 D7 Digital CMOS Output Bit 7 40 D8 Digital CMOS Output Bit 8 43 D9 Digital CMOS Output Bit 9 44 D10 Digital CMOS Output Bit 10 45 D11 Digital CMOS Output Bit 11 46 D12 Digital CMOS Output Bit 12 47 D13 Digital CMOS Output Bit 13 48 D14 Digital CMOS Output Bit 14 49 D15 Digital CMOS Output Bit 15 (MSB) 50 DAV Data Valid Output. This output can be used as a clock control line to drive an external buffer or dataacquisition system. The typical delay time between the falling edge of the converter clock and the rising edge of DAV is 4ns. 53 DOR Data Over-Range Bit. This control line flags an over-/under-range condition in the ADC. If DOR transitions high, an over-/under-range condition was detected. If DOR remains low, the ADC operates within the allowable full-scale range. — EP Internal Bandgap Reference Output Converter Ground. Digital output-driver ground. Exposed Paddle. Must be connected to AGND. _______________________________________________________________________________________ 9 MAX19588 Pin Description MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Detailed Description Figure 1 provides an overview of the MAX19588 architecture. The MAX19588 employs an input track-andhold (T/H) amplifier, which has been optimized for low thermal noise and low distortion. The high-impedance differential inputs to the T/H amplifier (INP and INN) are self-biased at approximately 2.4V, and support a fullscale 2.56VP-P differential input voltage. The output of the T/H amplifier is applied to a multistage pipelined ADC core, which is designed to achieve a very low thermal noise floor and low distortion. A clock buffer receives a differential input clock waveform and generates a low-jitter clock signal for the input T/H. The signal at the analog inputs is sampled at the rising edge of the differential clock waveform. The differential clock inputs (CLKP and CLKN) are highimpedance inputs, are self-biased at 1.6V, and support differential clock waveforms from 1VP-P to 5VP-P. The outputs from the multistage pipelined ADC core are delivered to error correction and formatting logic, which deliver the 16-bit output code in two’s-complement format to digital output drivers. The output drivers provide 1.8V CMOS-compatible outputs. Analog Inputs (INP, INN) The signal inputs to the MAX19588 (INP and INN) are balanced differential inputs. This differential configuration provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. The differential CLKP CLKN signal inputs to the MAX19588 should be AC-coupled and carefully balanced to achieve the best dynamic performance (see Differential, AC-Coupled Analog Inputs in the Applications Information section for more details). ACcoupling of the input signal is required because the MAX19588 inputs are self-biasing as shown in Figure 2. Although the track-and-hold inputs are high impedance, the actual differential input impedance is nominally 10kΩ because of the two 5kΩ resistors connected to the common-mode bias circuitry. Avoid injecting any DC leakage currents into these analog inputs. Exceeding a DC leakage current of 10µA shifts the self-biased common-mode level, adversely affecting the converter’s performance. On-Chip Reference Circuit The MAX19588 incorporates an on-chip 1.28V, low-drift bandgap reference. This reference potential establishes the full-scale range for the converter, which is nominally 2.56V P-P differential (Figure 3). The internal reference voltage can be monitored by REFOUT. To use the internal reference voltage the reference input (REFIN) must be connected to REFOUT through a 10kΩ resistor. Bypass both pins with separate 1µF capacitors to AGND. The MAX19588 also allows an external reference source to be connected to REFIN, enabling the user to overdrive the internal bandgap reference. REFIN accepts a 1.28V ±10% input voltage range. AVDD CLOCK BUFFER AGND DVDD DAV CMOS DRIVER INP T/H INN PIPELINE ADC CMOS OUTPUT DRIVERS DOR 16 D0–D15 DGND MAX19588 REFERENCE REFOUT REFIN Figure 1. Block Diagram 10 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor System Timing Requirements Figure 4 depicts the general timing relationships for the signal input, clock input, data output, and DAV output. Figure 5 shows the detailed timing specifications and signal relationships, as defined in the Electrical Characteristics table. The MAX19588 samples the input signal on the rising edge of the input clock. Output data is valid on the rising edge of the DAV signal, with a 7 clock-cycle data latency. Note that the clock duty cycle should typically be 50% ±10% for proper operation. T/H AMPLIFIER TO FIRST QUANTIZER STAGE INP 5kΩ OTA 5kΩ TO FIRST QUANTIZER STAGE INN Digital Outputs (D0–D15, DAV, DOR) For best performance, the capacitive loading on the digital outputs of the MAX19588 should be kept as low as possible (< 10pF). Due to the current-limited dataoutput driver of the MAX19588, large capacitive loads increase the rise and fall time of the data and can make it more difficult to register the data into the next IC. The loading capacitance can be kept low by keeping the output traces short and by driving a single CMOS buffer or latch input (as opposed to multiple CMOS inputs). The output data is in two’s-complement format, as illustrated in Table 1. Data is valid at the rising edge of DAV (Figures 4, 5). DAV may be used as a clock signal to latch the output data. Note that the DAV output driver is not current limited, hence it allows for higher capacitive loading. The converter’s DOR output signal is used to identify over- and under-range conditions. If the input signal exceeds the positive or negative full-scale range for the MAX19588 then DOR will be asserted high. The timing for DOR is identical to the timing for the data outputs, and DOR therefore provides an over-range indication on a sample-by-sample basis. T/H AMPLIFIER Figure 2. Simplified Analog Input Architecture +640mV 2.56VP-P DIFFERENTIAL FSR INP INN COMMON-MODE VOLTAGE (2.4V) -640mV Figure 3. Full-Scale Voltage Range ______________________________________________________________________________________ 11 MAX19588 Clock Inputs (CLKP, CLKN) The differential clock buffer for the MAX19588 has been designed to accept an AC-coupled clock waveform. Like the signal inputs, the clock inputs are self-biasing. In this case, the self-biased potential is 1.6V and each input is connected to the reference potential with a 5kΩ resistor. Consequently, the differential input resistance associated with the clock inputs is 10kΩ. While differential clock signals as low as 0.5VP-P can be used to drive the clock inputs, best dynamic performance is achieved with 1VP-P to 5VP-P clock input voltage levels. Jitter on the clock signal translates directly to jitter (noise) on the sampled signal. Therefore, the clock source must be a very low-jitter (low-phase-noise) source. Additionally, extremely low phase-noise oscillators and bandpass filters should be used to obtain the true AC performance of this converter. See the Differential, AC-Coupled Clock Inputs and Testing the MAX19588 topics in the Applications Information section for additional details on the subject of driving the clock inputs. MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor 7 CLOCK-CYCLE LATENCY (tLATENCY) N+1 N+2 N N+3 N+7 N+4 ANALOG INPUT N+6 N+5 CLOCK INPUT D0–D15 N-5 N-6 N-7 N-4 N-3 N-2 N-1 DAV Figure 4. General System Output Timing Diagram INP INN tCLKP tAD tCLKN CLKN N N+1 N+2 N+3 CLKP tDAT tDNV tDGV D0–D15 N-7 N-6 N-5 N-4 DOR tS tDAV tH DAV ENCODE AT CLKP - CLKN > 0 (RISING EDGE) tCLKP: CLKP - CLKN > 0 tCLKN: CLKP - CLKN < 0 EFFECTIVE APERTURE DELAY tAD: tDAT: DELAY FROM CLKP TO OUTPUT DATA TRANSITION tDAV: tDNV: tDGV: tS: tH : DELAY FROM CLKN TO DATA VALID CLOCK DAV CLKP RISING EDGE TO DATA NOT VALID CLKP RISING EDGE TO DATA GUARANTEED VALID DATA SETUP TIME BEFORE RISING DAV DATA HOLD TIME AFTER RISING DAV Figure 5. Detailed Timing Information for Clock Operation 12 ______________________________________________________________________________________ N High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 Table 1. MAX19588 Digital Output Coding INP ANALOG VOLTAGE LEVEL INN ANALOG VOLTAGE LEVEL D15–D0 TWO’S-COMPLEMENT CODE VCM + 0.64V VCM - 0.64V 0111111111111111 (positive full-scale) VCM VCM 0000000000000000 (midscale + δ) 1111111111111111 (midscale - δ) VCM - 0.64V VCM + 0.64V 1000000000000000 (negative full-scale) Applications Information Differential, AC-Coupled Clock Inputs The clock inputs to the MAX19588 are driven with an AC-coupled differential signal, and best performance is achieved under these conditions. However, it is often the case that the available clock source is single-ended. Figure 6 demonstrates one method for converting a single-ended clock signal into a differential signal with a transformer. In this example, the transformer turns ratio from the primary to secondary side is 1:1.414. The impedance ratio from primary to secondary is the square of the turns ratio, or 1:2. So terminating the sec- ondary side with a 100Ω differential resistance results in a 50Ω load looking into the primary side of the transformer. The termination resistor in this example is composed of the series combination of two 50Ω resistors with their common node AC-coupled to ground. Figure 6 illustrates the secondary side of the transformer to be coupled directly to the clock inputs. Since the clock inputs are self-biasing, the center tap of the transformer must be AC-coupled to ground or left floating. If the center tap of the transformer’s secondary side is DC-coupled to ground, it is necessary to add blocking capacitors in series with the clock inputs. AVDD DVDD D0–D15 INP MAX19588 INN 0.1μF BACK-TO-BACK DIODE 16 CLKP CLKN AGND DGND T2-1T-KK81 49.9Ω 49.9Ω 0.1μF Figure 6. Transformer-Coupled Clock Input Configuration ______________________________________________________________________________________ 13 MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Clock jitter is generally improved if the clock signal has a high slew rate at the time of its zero-crossing. Therefore, if a sinusoidal source is used to drive the clock inputs, the clock amplitude should be as large as possible to maximize the zero-crossing slew rate. The back-to-back Schottky diodes shown in Figure 6 are not required as long as the input signal is held to a differential voltage potential of 3VP-P or less. If a larger amplitude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential signal swing at the clock inputs. Note that all AC specifications for the MAX19588 are measured within this configuration and with an input clock amplitude of approximately 12dBm. Any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the SNR performance of the MAX19588. Any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. Consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. See the Signal Routing section for more discussion on the subject of noise coupling. side of the transformer, the secondary side is terminated with a 100Ω differential load. This load, in shunt with the differential input resistance of the MAX19588, results in a 100Ω differential load on the secondary side. It is reasonable to use a larger transformer turns ratio to achieve a larger signal step-up, and this may be desirable to relax the drive requirements for the circuitry driving the MAX19588. However, the larger the turns ratio, the larger the effect of the differential input impedance of the MAX19588 on the primary-referred input impedance. As stated previously, the signal inputs to the MAX19588 must be accurately balanced to achieve the best evenorder distortion performance. Differential, AC-Coupled Analog Inputs The MAX19588 EV kit is a 6-layer board, and the assignment of layers is discussed in this context. It is recommended that the ground plane be on a layer between the signal routing layer and the supply routing layer(s). This prevents coupling from the supply lines into the signal lines. The MAX19588 EV kit PC board places the signal lines on the top (component) layer and the ground plane on layer 2. Any region on the top layer not devoted to signal routing is filled with the ground plane with vias to layer 2. Layers 3 and 4 are devoted to supply routing, layer 5 is another ground plane, and layer 6 is used for the placement of additional components and for additional signal routing. The analog inputs INP and INN are driven with a differential AC-coupled signal. It is important that these inputs be accurately balanced. Any common-mode signal applied to these inputs degrades even-order distortion terms. Therefore, any attempt at driving these inputs in a single-ended fashion will result in significant even-order distortion terms. Figure 7 presents one method for converting a singleended signal to a balanced differential signal using a transformer. The primary-to-secondary turns ratio in this example is 1:1.414. The impedance ratio is the square of the turns ratio, so in this example the impedance ratio is 1:2. To achieve a 50Ω input impedance at the primary One note of caution in relation to transformers is important. Any DC current passed through the primary or secondary windings of a transformer may magnetically bias the transformer core. When this happens the transformer is no longer accurately balanced and a degradation in the distortion of the MAX19588 may be observed. The core must be demagnetized to return to balanced operation. Layer Assignments AVDD DVDD POSITIVE TERMINAL 0.1μF ADT2-1T T1-1T-KK81 INP 49.9Ω D0–D15 MAX19588 16 49.9Ω INN 0.1μF CLKP CLKN AGND DGND Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Balun Transformer 14 ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor Signal Routing To preserve good even-order distortion, the signal lines (those traces feeding the INP and INN inputs) must be carefully balanced. To accomplish this, the signal traces should be made as symmetric as possible, meaning that each of the two signal traces should be the same length and should see the same parasitic environment. As mentioned previously, the signal lines must be isolated from the supply lines to prevent coupling from the supplies to the inputs. This is accomplished by making the necessary layer assignments as described in the previous section. Additionally, it is crucial that the clock lines be isolated from the signal lines. On the MAX19588 EV kit this is done by routing the clock lines on the bottom layer (layer 6). The clock lines then connect to the ADC through vias placed in close proximity to the device. The clock lines are isolated from the supply lines as well by virtue of the ground plane on layer 5. As with all high-speed designs, digital output traces should be kept as short as possible to minimize capacitive loading. The ground plane on layer 2 beneath these traces should not be removed so that the digital groundreturn currents have an uninterrupted path back to the bypass capacitors. Grounding The practice of providing a split ground plane in an attempt to confine digital ground-return currents has often been recommended in ADC application literature. However, for converters such as the MAX19588 it is strongly recommended to employ a single, uninterrupted ground plane. The MAX19588 EV kit achieves excellent dynamic performance with such a ground plane. The exposed paddle of the MAX19588 should be soldered directly to a ground pad on layer 1 with vias to the ground plane on layer 2. This provides excellent electrical and thermal connections to the PC board. Supply Bypassing The MAX19588 EV kit uses 220µF capacitors (and smaller values such as 47µF and 2µF) on power-supply lines AVDD, AVDDA, and DVDD to provide low-frequency bypassing. The loss (series resistance) associated with these capacitors is beneficial in eliminating high-Q supply resonances. Ferrite beads are also used on each of the power-supply lines to enhance supply bypassing (Figure 8). BYPASSING—ADC LEVEL BYPASSING—BOARD LEVEL DVDD AVDD 0.01μF AVDD 0.1μF 0.1μF FERRITE BEAD 0.01μF 47μF 2μF AGND 220μF ANALOG POWERSUPPLY SOURCE 220μF DIGITAL POWERSUPPLY SOURCE DGND 50Ω AVDD AVDDA DVDD D0–D15 DVDD FERRITE BEAD MAX19588 16 2μF AGND 47μF DGND Figure 8. Grounding, Bypassing, and Decoupling Recommendations for the MAX19588 ______________________________________________________________________________________ 15 MAX19588 A four-layer implementation is also feasible using layer 1 for signal lines, layer 2 as a ground plane, layer 3 for supply routing, and layer 4 for additional signal routing. However, care must be taken to ensure that the clock and signal lines are isolated from each other and from the supply lines. MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor FFT PLOT (542,288-POINT DATA RECORD) SIGNAL PATH AGILENT 8644B 0 BANDPASS FILTER 10dB AGILENT 8644B MAX19588 CLOCK PATH BANDPASS FILTER AMPLITUDE (dBFS) 3dB PAD BOTH SIGNAL GENERATORS ARE PHASE-LOCKED fCLK = 100MHz fIN = 67.6MHz AIN = -1.98dBFS -20 -40 -60 -80 3 -100 2 -120 Figure 9a. Standard High-Speed ADC Test Setup (Simplified Diagram) -140 0 5 10 15 20 25 30 35 40 45 ANALOG FREQUENCY (MHz) FFT PLOT (524,288-POINT DATA RECORD) 0 fCLK = 100MHz fIN = 70.1MHz AIN = -2.04dBFS AMPLITUDE (dBFS) -20 -40 -60 -80 3 -100 2 -120 -140 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) Figure 9b. 70MHz FFT with Standard High-Speed ADC Test Setup Combinations of small value (0.01µF and 0.1µF), lowinductance surface-mount capacitors should be placed at each supply pin or each grouping of supply pins to attenuate high-frequency supply noise. Place these capacitors on the top side of the board and as close to the converter as possible with short connections to the ground plane. Supply/Clock Sequencing Power up the MAX19588 (any sequence will be acceptible) and then apply the clock. If the clock is present before the MAX19588 is powered up, ensure that DVDD is brought up first followed by AVDD. 16 Figure 9c. 68MHz FFT with Standard High-Speed ADC Test Setup Testing the MAX19588 The MAX19588 has a very low thermal noise floor (-82dBFS) and very low jitter (< 100fs). As a consequence, test system limitations can easily obscure the performance of the ADC. Figure 9a is a block diagram of a conventional high-speed ADC test system. The input signal and the clock source are generated by low-phase-noise synthesizers (e.g., HP/Agilent 8644B). Bandpass filters in both the signal and the clock paths then attenuate noise and harmonic components. Figure 9b shows the resulting power spectrum, which results from this setup for a 70MHz input tone and a 100Msps clock. Note the substantial lift in the noise floor near the carrier. The bandwidth of this particular noise-floor lift near the carrier corresponds to the bandwidth of the filter in the input signal path. Figure 9c illustrates the impact on the spectrum if the input frequency is shifted away from the center frequency of the input signal filter. Note that the fundamental tone has moved, but the noise-floor lift remains in the same location. This is evidence of the validity of the claim that the lift in the noise floor is due to the test system and not the ADC. In this figure, the magnitude of the lift in the noise floor increased relative to the previous figure because the signal is located on the skirt of the filter and the signal amplitude had to be increased to obtain a signal near full scale. ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor MAX19588 AGILENT 8644B SIGNAL PATH VARIABLE BANDPASS ATTENUATOR FILTER REF PLL SIGNAL TUNE 10dB 3dB PAD VCXO MAX19588 LOW-NOISE PLL AGILENT 8644B BOTH SIGNAL GENERATORS ARE PHASE-LOCKED REF PLL SIGNAL TUNE CLOCK PATH BANDPASS FILTER 10dB VCXO LOW-NOISE PLL Figure 9d. Improved Test System Employing Narrowband PLLs (Simplified Diagram) FFT PLOT (524,288-POINT DATA RECORD) SNR vs. RMS JITTER PERFORMANCE 110 0 fCLK = 100MHz fIN = 70.164MHz AIN = -1.94dBFS INPUT FREQUENCY = 70MHz 100 -40 95 90 -60 -80 SNR (dB) AMPLITUDE (dBFS) -20 105 3 2 -100 85 80 75 70 -120 INPUT FREQUENCY = 140MHz 65 60 -140 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) 10 100 1000 RMS JITTER (fs) Figure 9e. 70MHz FFT with Improved High-Speed ADC Test Setup Figure 9f. SNR vs. System Jitter Performance Graph To truly reveal the performance of the MAX19588, the test system performance must be improved substantially. Figure 9d depicts such an improved test system. In this system, the synthesizers provide reference inputs to two dedicated low-noise phase-locked loops (PLLs), one centered at approximately 100MHz (for the clock path) and the other centered at 70MHz (for the signal path). The oscillators in these PLLs are very low-noise oscillators, and the PLLs act as extremely narrow bandwidth filters (on the order of 20Hz) to attenuate the noise of the synthesizers. The system provides a total system jitter on the order of 20fs. Note that while the low-noise oscillators could be used by themselves without being locked to their respective signal sources, this would result in FFTs that are not coherent and which would require windowing. Figure 9e is an FFT plot of the spectrum obtained when the improved test system is employed. The noise-floor lift in the vicinity of the carrier is now almost completely eliminated. The SNR associated with this FFT is 79dB, whereas the SNR obtained using the standard test system is 77.2dB. Figure 9f demonstrates the impact of test system jitter on measured SNR. The figure plots SNR due to test system jitter only, neglecting all other sources of noise, for two different input frequencies. For example, note that for a 70MHz input frequency a test system jitter number of 100fs results in an SNR (due to the test system alone) of about 87dB. In the case of the MAX19588, which has a -82dBFS noise floor, this is not an inconsequential amount of additional noise. ______________________________________________________________________________________ 17 MAX19588 High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor In conclusion, careful attention must be paid to both the input signal source and the clock signal source, if the true performance of the MAX19588 is to be properly characterized. Dedicated PLLs with low-noise VCOs, such as those used in Figure 9d, are capable of providing signals with the required low jitter performance. Parameter Definitions Offset Error In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first four harmonics (HD2 through HD5), and the DC offset. SNR = 20 x log (SIGNALRMS / NOISERMS) Signal-to-Noise Plus Distortion (SINAD) Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the midscale MAX19588 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Gain Error SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR1 reflects the MAX19588 spurious performance based on worst 2ndor 3rd-order harmonic distortion. SFDR2 is defined by the worst spurious component excluding 2nd- and 3rdorder harmonic spurs and DC offset. Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX19588 transition occurs at 1.5 LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude of less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR[max] = 6.02 x N + 1.76 18 Spurious-Free Dynamic Range (SFDR1 and SFDR2) Two-Tone Spurious-Free Dynamic Range (TTSFDR) Two-tone SFDR is the ratio of the full scale of the converter to the RMS value of the peak spurious component. The peak spurious component can be related to the intermodulation distortion components, but does not have to be. Two-tone SFDR for the MAX19588 is expressed in dBFS. 3rd-Order Intermodulation (IM3) IM3 is the power of the largest 3rd-order intermodulation product relative to the input power of either of the input tones f IN1 and f IN2 . The individual input tone power levels are set to -8dBFS for the MAX19588. The 3rd-order intermodulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1. Aperture Jitter Aperture jitter (tAJ) represents the sample-to-sample variation in the aperture delay specification. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 5). ______________________________________________________________________________________ High-Dynamic-Range, 16-Bit, 100Msps ADC with -82dBFS Noise Floor 56L THIN QFN.EPS PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 1 2 PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2006 Maxim Integrated Products Freed FREED Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX19588 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)