MAXIM MAX1419

19-3011; Rev 0; 10/03
KIT
ATION
EVALU
LE
B
A
IL
A
AV
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
Features
♦ 65Msps Minimum Sampling Rate
♦ -79.3dBFS Noise Floor
♦ Excellent Dynamic Performance
76.2dB SNR at fIN=15MHz and AIN = -1dBFS
93.1dBc/95.5dBc Single-Tone SFDR1/SFDR2 at
fIN = 15MHz and AIN = -1dBFS
-91dBc Multitone SFDR at fIN1 = 10MHz
and fIN2 = 15MHz
♦ Less than 0.25ps Sampling Jitter
♦ Fully Differential Analog Input Voltage Range of
2.56VP-P
♦ CMOS-Compatible Two’s-Complement Data Output
♦ Separate Data Valid Clock and Overrange Outputs
♦ Flexible-Input Clock Buffer
♦ EV Kit Available for the MAX1419
(Order MAX1427EVKIT)
Ordering Information
PART
MAX1419ETN
*EP
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
56 QFN-EP*
= Exposed paddle.
Pin-Compatible Higher/Lower
Speed Versions Selection
Applications
Cellular Base-Station Transceiver Systems (BTS)
PART
Wireless Local Loop (WLL)
SPEED GRADE
(Msps)
TARGET
APPLICATION
Single- and Multicarrier Receivers
MAX1418
65
IF
Multistandard Receivers
MAX1419
65
Baseband
E911 Location Receivers
MAX1427
80
Baseband
Power Amplifier Linearity Correction
MAX1428*
80
IF
Antenna Array Processing
MAX1429*
100
Baseband
MAX1430*
100
IF
Pin Configuration appears at end of data sheet.
*Future
product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1419
General Description
The MAX1419 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 15-bit converter core. The MAX1419 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -79.3dBFS, the MAX1427 allows for the
design of receivers with superior sensitivity.
The MAX1419 achieves two-tone, spurious-free dynamic
range (SFDR) of -91dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 76.2dB
and single-tone SFDR performance (SFDR1/SFDR2) of
93.1dBc/95.5dBc at fIN = 15MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1419 operates from an analog 5V and a digital
3V supply, features a 2.56VP-P full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
200MHz.
The MAX1419 features parallel, CMOS-compatible outputs in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1419 is manufactured in an 8mm x 8mm,
56-pin QFN package with exposed paddle (EP) for low
thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see the Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequencies greater than fCLK/3. The MAX1419 is optimized for
input frequencies of less than fCLK/3.
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC, DRVCC to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AVCC + 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRVCC + 0.3V)
Continuous Power Dissipation (TA = +70°C)
56-Pin QFN (derate 47.6mW/°C above +70°C) ......3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance θJA ...................................................21°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
15
Bits
Integral Nonlinearity
INL
fIN = 15MHz
±1.5
LSB
Differential Nonlinearity
DNL
fIN = 15MHz, no missing codes guaranteed
±0.4
LSB
Offset Error
-12
+12
mV
Gain Error
-4
+4
%FS
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
VDIFF
Fully differential inputs drive, VDIFF = VINP - VINN
2.56
VP-P
Common-Mode Input Voltage
VCM
Self-biased
3.38
V
Differential Input Resistance
RIN
1
±15%
kΩ
Differential Input Capacitance
CIN
Full-Power Analog Bandwidth
FPBW-1dB
-1dB rolloff for a full-scale input
1
pF
200
MHz
CONVERSION RATE
Maximum Clock Frequency
fCLK
Minimum Clock Frequency
fCLK
20
MHz
tAJ
0.21
psRMS
0.5 to
3.0
V
2.4
V
kΩ
Aperture Jitter
65
MHz
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Common-Mode Input Voltage
VDIFFCLK
VCM
Fully differential input drive, VCLKP - VCLKN
Self-biased
Differential Input Resistance
RINCLK
2
±15%
Differential Input Capacitance
CINCLK
1
pF
-79.3
dBFS
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF
Analog input <-35dBFS
fIN = 5MHz at -1dBFS
Signal-to-Noise Ratio (Note 1)
SNR
fIN = 15MHz at -1dBFS
fIN = 25MHz at -1dBFS
2
76.5
73.5
76.1
76
_______________________________________________________________________________________
dB
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.)
PARAMETER
SYMBOL
fIN = 15MHz at -1dBFS
SFDR1
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 1)
SFDR2
Two-Tone Intermodulation
Distortion
TTIMD
Two-Tone Spurious-Free
Dynamic Range
MIN
TYP
73
75.9
fIN = 5MHz at -1dBFS
Signal-to-Noise and Distortion
(Note 1)
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 1)
CONDITIONS
SFDRTT
74.3
fIN = 5MHz at -1dBFS
96.5
84
80.5
fIN = 5MHz at -1dBFS
94.5
85.5
dB
dBc
93.5
fIN = 25MHz at -1dBFS
fIN = 15MHz at -1dBFS
UNITS
76.3
fIN = 25MHz at -1dBFS
fIN = 15MHz at -1dBFS
MAX
dBc
94.5
fIN = 25MHz at -1dBFS
93.2
fIN1 = 10MHz at -7dBFS;
fIN2 = 15MHz at -7dBFS
-91
dBc
fIN1 = 10MHz at -10dBFS < fIN1 < -100dBFS;
fIN2 = 15MHz at -10dBFS < fIN2 < -100dBFS
-105
dBFS
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
Digital Output Voltage Low
VOL
Digital Output Voltage High
VOH
0.5
DVCC 0.5
V
V
TIMING CHARACTERISTICS (DVCC = DRVCC = 2.5V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
Duty cycle
%
Effective Aperture Delay
tAD
Output Data Delay
tDAT
(Note 3)
3
4.5
7.5
Data Valid Delay
tDAV
(Note 3)
5.3
6.5
8.7
Pipeline Latency
230
tLATENCY
ps
ns
ns
Clock
cycles
3
CLKP Rising Edge to DATA
Not Valid
tDNV
(Note 3)
2.6
3.8
5.7
ns
CLKP Rising Edge to DATA
Valid (Guaranteed)
tDGV
(Note 3)
3.4
5.2
8.6
ns
DATA Setup Time
(Before DAV Rising Edge)
tSETUP
(Note 3)
tCLKP 0.5
tCLKP
+ 1.3
tCLKP
+ 2.4
ns
DATA Hold Time
(After DAV Rising Edge)
tHOLD
(Note 3)
tCLKN - tCLKN - tCLKN 3.6
2.8
2.0
ns
_______________________________________________________________________________________
3
MAX1419
ELECTRICAL CHARACTERISTICS (continued)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (DVCC = DRVCC = 3.3V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
Duty cycle
%
Effective Aperture Delay
tAD
Output Data Delay
tDAT
(Note 3)
2.8
4.1
6.5
Data Valid Delay
tDAV
(Note 3)
5.3
6.3
8.6
Pipeline Latency
230
tLATENCY
ps
ns
ns
Clock
cycles
3
CLKP Rising Edge to
DATA Not Valid
tDNV
(Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to
DATA Valid (Guaranteed)
tDGV
(Note 3)
3.2
4.4
7.4
ns
DATA Setup Time
(Before DAV Rising Edge)
tSETUP
(Note 3)
tCLKP
+ 0.2
tCLKP
+ 1.7
tCLKP
+ 2.8
ns
DATA Hold Time
(After DAV Rising Edge)
tHOLD
(Note 3)
tCLKN - tCLKN - tCLKN 3.5
2.7
2.0
ns
5
±3%
V
POWER REQUIREMENTS
Analog Supply Voltage Range
AVCC
Digital Supply Voltage Range
DVCC
(Note 2)
2.3 to 3.5
V
Output Supply Voltage Range
DRVCC
(Note 2)
2.3 to 3.5
V
Analog Supply Current
IAVCC
IDVCC +
fCLK = 65MHz, CLOAD = 5pF
Digital + Output Supply Current
Analog Power Dissipation
PDISS
377
440
mA
35.5
42
mA
1974
mW
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of fSAMPLE = 65.0117120MHz, an
input frequency of fIN = fSAMPLE x (7561/32768) = 15.001024MHz, and a frequency bin size of 1984Hz. Close-in (fIN
±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DVCC and DRVCC.
Note 3: Guaranteed by design and characterization.
4
_______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
-80
-60
5
10
15
20
25
0
30
MAX1419 toc03
-80
5
10
15
20
0
30
25
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fCLK = 65.0117MHz, AIN = -1dBFS)
100
MAX1419 toc04
78
77
95
SFDR2
75
74
73
90
85
SFDR1
80
-75
HD2/HD3 (dBc)
SFDR1/SFDR2 (dBc)
76
-70
MAX1419 toc06
0
-60
-120
-120
-120
-40
-100
-100
-100
SNR (dBc)
MAX1419 toc02
-80
fCLK = 65.0117MHz
fIN = 25.0004MHz
AIN = -06dBFS
SNR = 76.3dB
SFDR1 = 77.9dBc
SFDR2 = 92.3dBc
HD2 = 85.6dBc
HD3 = 77.9dBc
-20
AMPLITUDE (dBFS)
-60
-40
0
MAX1419 toc05
AMPLITUDE (dBFS)
-40
fCLK = 65.0117MHz
fIN = 15.0010MHz
AIN = -0.98dBFS
SNR = 76.5dB
SFDR1 = 89.1dBc
SFDR2 = 98.1dBc
HD2 = 94.8dBc
HD3 = 89dBc
-20
AMPLITUDE (dBFS)
fCLK = 65.0117MHz
fIN = 10.0013MHz
AIN = -1.02dBFS
SNR = 76.8dB
SFDR1 = 87.7dBc
SFDR2 = 98.3dBc
HD2 = 87.7dBc
HD3 = 91.5dBc
-20
0
MAX1419 toc01
0
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
HD3
-80
-85
HD2
-90
72
75
70
-95
70
15
25
35
45
55
65
-100
5
15
25
fIN (MHz)
FULL-SCALE-TO-NOISE RATIO vs.
ANALOG INPUT AMPLITUDE
(fCLK = 65.011712MHz, fIN = 15.0010MHz)
77
76
75
74
73
65
5
15
25
SFDR1
SFDR2
-70
-80
HD3
-90
110
100
90
-100
-110
-120
-50
-40
-30
-20
-10
ANALOG INPUT AMPLITUDE (dBFS)
0
HD2
-140
-150
70
-60
65
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fCLK = 65.0117MHz, fIN = 15.0010MHz)
71
-70
55
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE
(fCLK = 65.0117MHz, fIN = 15.0010MHz)
80
70
45
fIN (MHz)
-130
72
35
fIN (MHz)
120
SFDR1/SFDR2 (dBFS)
78
55
HD2/HD3 (dBFS)
79
45
130
MAX1419 toc07
FULL-SCALE-TO-NOISE RATIO (dBFS)
80
35
MAX1419 toc08
5
MAX1419 toc09
71
-70
-60
-50
-40
-30
-20
-10
ANALOG INPUT AMPLITUDE (dBFS)
0
-70
-60
-50
-40
-30
-20
-10
0
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________
5
MAX1419
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
Typical Operating Characteristics (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
HD2/HD3 vs. SAMPLING FREQUENCY
(fIN = 15.2MHz, AIN = -1dBFS)
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(fIN = 15.2MHz, AIN = -1dBFS)
77
-70
MAX1419 toc11
100
MAX1419 toc10
78
SFDR2
95
-75
73
-85
90
85
HD2/HD3 (dBc)
SFDR1/SFDR2 (dBc)
74
SFDR1
80
-95
-100
HD2
-110
75
-115
70
70
20
25
30
35
40
45
50
55
60
65
-120
20
fCLK (MHz)
25
30
35
40
35
50
55
60
65
25
30
35
45
50
SINAD vs. TEMPERATURE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
76
75
74
MAX1419 toc14
78
77
SINAD (dB)
77
40
fCLK (MHz)
MAX1419 toc13
78
SNR (dB)
20
fCLK (MHz)
SNR vs. TEMPERATURE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
76
75
74
73
73
-40
-15
10
35
TEMPERATURE (°C)
6
-90
-105
72
71
HD3
-80
76
75
MAX1419 toc12
SNR vs. SAMPLING FREQUENCY
(fIN = 15.2MHz, AIN = -1dBFS)
SNR (dBc)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
_______________________________________________________________________________________
85
55
60
65
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
1975
POWER DISSIPATION (mW)
HD2
HD2/HD3 (dBc)
-90
92
SFDR1
88
HD3
-95
-100
84
1974
1973
1972
1971
-105
-15
10
35
60
85
1970
-40
TEMPERATURE (°C)
-15
10
35
85
60
2150
-15
10
0
-20
AMPLITUDE (dBFS)
2000
1950
60
85
TWO-TONE IMD PLOT (32,768-POINT
DATA RECORD, COHERENT SAMPLING)
fCLK = 65.0117MHz
fIN1 = 10.0010MHz
fIN2 = 15.0010MHz
AIN1 = AIN2 = -7dBFS
fIN1
2100
2050
35
TEMPERATURE (°C)
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
2200
-40
TEMPERATURE (°C)
MAX1419 toc18
-40
MAX1419 toc19
80
POWER DISSIPATION (mW)
SFDR1/SFDR2 (dBc)
1976
MAX1419 toc16
SFDR2
96
POWER DISSIPATION vs. TEMPERATURE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
-85
MAX1419 toc15
100
HD2/HD3 vs. TEMPERATURE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc17
SFDR1/SFDR2 vs. TEMPERATURE
(fCLK = 65.0117MHz,
fIN = 15.0010MHz, AIN = -1dBFS)
-40
fIN2
-60
2fIN1 - fIN2
-80
2fIN2 - fIN1
1900
-100
1850
1800
-120
4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX1419
Typical Operating Characteristics (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
MAX1419
Pin Description
8
PIN
NAME
FUNCTION
1, 2, 3, 6, 9, 12, 14–17,
20, 23, 26, 27, 30, 52–56, EP
GND
Converter Ground. Analog, digital, and output driver grounds are internally
connected to the same potential. Connect the converter’s EP to GND.
4
CLKP
Differential Clock, Positive Input Terminal
5
CLKN
Differential Clock, Negative Input Terminal
7, 8, 18, 19, 21, 22, 24, 25, 28
AVCC
Analog Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
10
INP
11
INN
Differential Analog Input, Negative/Complementary Terminal
13
CM
Common-Mode Reference Terminal
29
DVCC
31, 41, 42, 51
DRVCC
32
DOR
33
D0
Digital CMOS Output Bit 0 (LSB)
34
D1
Digital CMOS Output Bit 1
35
D2
Digital CMOS Output Bit 2
36
D3
Digital CMOS Output Bit 3
37
D4
Digital CMOS Output Bit 4
38
D5
Digital CMOS Output Bit 5
39
D6
Digital CMOS Output Bit 6
40
D7
Digital CMOS Output Bit 7
43
D8
Digital CMOS Output Bit 8
44
D9
Digital CMOS Output Bit 9
45
D10
Digital CMOS Output Bit 10
46
D11
Digital CMOS Output Bit 11
47
D12
Digital CMOS Output Bit 12
48
D13
Digital CMOS Output Bit 13
49
D14
Digital CMOS Output Bit 14 (MSB)
50
DAV
Data Valid Output. This output can be used as a clock control line to drive an
external buffer or data-acquisition system. The typical delay time between the
falling edge of the converter clock and the rising edge of DAV is 6.5ns.
Differential Analog Input, Positive Terminal
Digital Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
Digital Output Driver Supply Voltage. Provide local bypassing to ground with
0.1µF to 0.22µF capacitors.
Data Overrange Bit. This control line flags an overrange condition in the ADC.
If DOR transitions high, an overrange condition was detected. If DOR remains low,
the ADC operates within the allowable full-scale range.
_______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
Analog Inputs and
Common Mode (INP, INN, CM)
The signal inputs to the MAX1419 (INP and INN) are
balanced differential inputs. This differential configuration provides immunity to common-mode noise coupling
and rejection of even-order harmonic terms. The differential signal inputs to the MAX1419 should be AC-coupled and carefully balanced in order to achieve the best
dynamic performance (see the Applications Information
section for more detail). AC-coupling of the input signal
is easily accomplished because the MAX1419 inputs
are self-biasing as illustrated in Figure 2. Although the
T/H inputs are high impedance, the actual differential
input impedance is nominally 1kΩ because of the two
500Ω bias resistors connected from each input to the
common-mode reference.
AVCC
GND
DVCC
MAX1419
Detailed Description
Figure 1 provides an overview of the MAX1419 architecture. The MAX1419 employs an input T/H amplifier,
which has been optimized for low thermal noise and
low distortion. The high-impedance differential inputs to
the T/H amplifier (INP and INN) are self-biased at
3.38V, and support a full-scale differential input voltage
of 2.56VP-P. The output of the T/H amplifier is fed to a
multistage pipelined ADC core, which has also been
optimized to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock waveform and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The differential clock inputs (CLKP and CLKN) are highimpedance inputs, are self-biased at 2.4V, and support
differential clock waveforms from 0.5VP-P to 3.0VP-P.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logicwhich in turn, deliver the 15-bit output code in two’scomplement format to digital output drivers. The output
drivers provide CMOS-compatible outputs with levels
programmable over a 2.3V to 3.5V range.
DRVCC
INP
T/H
MAX1419
MULTISTAGE
PIPELINE ADC CORE
INN
CM
INTERNAL
REFERENCE
CLKP
INTERNAL
TIMING
CLOCK
BUFFER
CLKN
CORRECTION
LOGIC + OUTPUT
BUFFERS
15
DAV
DATA BITS D0 THROUGH D14
Figure 1. Simplified MAX1419 Block Diagram
T/H AMPLIFIER
INP
TO 1. QUANTIZER STAGE
500Ω BUFFER
1kΩ
INTERNAL REFERENCE
AND BIASING CIRCUIT
CM
500Ω
INN
T/H AMPLIFIER
TO 1. QUANTIZER STAGE
Figure 2. Simplified Analog and Common-Mode Input Architecture
The CM pin provides a monitor of the input commonmode self-bias potential. In most applications, in which
the input signal is AC-coupled, this pin is not connected. If DC-coupling of the input signal is required, this
pin may be used to construct a DC servo loop to control the input common-mode potential. See the
Applications Information section for more details.
_______________________________________________________________________________________
9
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
On-Chip Reference Circuit
Clock Inputs (CLKP, CLKN)
The MAX1419 incorporates an on-chip 2.5V, low-drift
bandgap reference. This reference potential establishes the full-scale range for the converter, which is nominally 2.56V P-P differential. The internal reference
potential is not accessible to the user, so the full-scale
range for the MAX1419 cannot be externally adjusted.
The differential clock buffer for the MAX1419 has been
designed to accept an AC-coupled clock waveform.
Like the signal inputs, the clock inputs are self-biasing.
In this case, the common-mode bias potential is 2.4V
and each input is connected to the reference potential
through a 1kΩ resistor. Consequently, the differential
input resistance associated with the clock inputs is
2kΩ. While differential clock signals as low as 0.5VP-P
may be used to drive the clock inputs, best dynamic
performance is achieved with clock input voltage levels
of 2VP-P to 3VP-P. Jitter on the clock signal translates
directly to jitter (noise) on the sampled signal.
Therefore, the clock source should be a low-jitter (lowphase noise) source. See the Applications Information
section for additional details on driving the clock inputs.
Figure 3 shows how the reference is used to generate
the common-mode bias potential for the analog inputs.
The common-mode input bias is set to one diode
potential above the bandgap reference potential, and
so varies over temperature.
500Ω
2.5V
INP/INN
COMMON-MODE
REFERENCE
System Timing Requirements
500Ω
1mA
1kΩ
Figure 4 depicts the timing relationships for the signal
input, clock input, data output, and DAV output. The
variables shown in the figure correspond to the various
timing specifications in the Electrical Characteristics
section. These include:
• tDAT: Delay from the rising edge of the clock until the
50% point of the output data transition
• tDAV: Delay from the falling edge of the clock until the
50% point of the DAV rising edge
2mA
• tDNV: Time from the rising edge of the clock until data
is no longer valid
Figure 3. Simplified Reference Architecture
INP
INN
tCLKP
tAD
tCLKN
CLKN
N
N+1
N+2
CLKP
tDAT
tDGV
tDNV
D0–D14
DOR
N-3
tDAV
N+3
N-2
N-1
tS
N
tH
DAV
Figure 4. System and Output Timing Diagram
10
______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220Ω or less) between
the MAX1419 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in controlling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illustrated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV may be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condition. If the input signal exceeds the positive or negative
full-scale range for the MAX1419, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an overrange indication on a sample-by-sample basis.
Digital Outputs (D0–D14, DAV, DOR)
The logic “high” level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) may be set in the
range of 2.3V to 3.5V. This is accomplished by setting
the voltage at the DVCC and DRVCC pins to the desired
logic-high level. Note that the DVCC and DRVCC voltages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1419 should be kept as low as possible
Table 1. MAX1419 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
D14–D0
TWO’S COMPLEMENT CODE
VREF + 0.64V
VREF - 0.64V
011111111111111
(positive full scale)
VREF
VREF
000000000000000
(midscale + δ)
111111111111111
(midscale - δ)
VREF - 0.64V
VREF + 0.64V
100000000000000
(negative full scale)
______________________________________________________________________________________
11
MAX1419
• tDGV: Time from the rising edge of the clock until data
is guaranteed to be valid
• tSETUP: Time from data guaranteed valid until the rising edge of DAV
• tHOLD: Time from the rising edge of DAV until data is
no longer valid
• tCLKP: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
• tCLKN: Time from 50% point of the falling edge to the
50% point of the rising edge of the clock signal
The MAX1419 samples the input signal on the rising
edge of the input clock. Output data is valid on the rising edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
BACK-TO-BACK DIODE
AVCC DVCC DRVCC
0.1µF
T2-1T–KK81
50Ω
INP
D0–D14
50Ω
MAX1419
15
INN
0.1µF
0.01µF 0.1µF
0.01µF
CLKP
CLKN
GND
Figure 5. Transformer-Coupled Clock Input Configuration
Applications Information
Differential, AC-Coupled Clock Input
The clock inputs to the MAX1419 are designed to be
driven with an AC-coupled differential signal, and best
performance is achieved under these conditions.
However, it is often the case that the available clock
source is single ended. Figure 5 demonstrates one
method for converting a single-ended clock signal into
a differential signal through a transformer. In this example, the transformer turns ratio from the primary to secondary side is 1:1.414. The impedance ratio from
primary to secondary is the square of the turns ratio, or
1:2, so that terminating the secondary side with a 100Ω
differential resistance results in a 50Ω load looking into
the primary side of the transformer. The termination
resistor in this example comprises the series combination of two 50Ω resistors with their common node ACcoupled to ground. Alternatively, a single 100Ω resistor
across the two inputs with no common-mode connection could be employed.
In the example of Figure 5, the secondary side of the
transformer is coupled directly to the clock inputs.
Since the clock inputs are self-biasing, the center tap of
the transformer must be AC-coupled to ground or left
floating. If the center tap of the secondary were DCcoupled to ground, then it would be necessary to add
blocking capacitors in series with the clock inputs.
Clock jitter is generally improved if the clock signal has
a high slew rate at the time of its zero crossing.
Therefore, if a sinusoidal source is used to drive the
clock inputs, it is desirable that the clock amplitude be
as large as possible to maximize the zero-crossing
slew rate. The back-to-back Schottky diodes shown in
Figure 5 are not required as long as the input signal is
12
held to 3VP-P differential or less. If a larger amplitude
signal is provided (to maximize the zero-crossing slew
rate), then the diodes serve to limit the differential signal swing at the clock inputs.
Any differential mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR performance of the MAX1419. Any differential mode coupling
of the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that
the clock lines be well isolated from the analog signal
input and from the digital outputs. See the PC Board
Layout Considerations sections for more discussion on
noise coupling.
Differential, AC-Coupled Analog Input
The analog inputs (INP and INN) are designed to be driven with a differential AC-coupled signal. It is extremely
important that these inputs be accurately balanced. Any
common-mode signal applied to these inputs degrade
even-order distortion terms. Therefore, any attempt at
driving these inputs in a single-ended fashion results in
significant even-order distortion terms.
Figure 6 presents one method for converting a singleended signal to a balanced differential signal using a
transformer. The primary-to-secondary turns ratio in this
example is 1:1.414. The impedance ratio is the square
of the turns ratio, so in this example, the impedance
ratio is 1:2. In order to achieve a 50Ω input impedance
at the primary side of the transformer, the secondary
side is terminated with a 112Ω differential load. This
load, in shunt with the differential input resistance of the
MAX1419, results in a 100Ω differential load on the secondary side. It is reasonable to use a larger transformer
turns ratio in order to achieve a larger signal step-up,
and this may be desirable in order to relax the drive
requirements for the circuitry driving the MAX1419.
______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
MAX1419
AVCC DVCC DRVCC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
T2-1T–KK81
INP
D0–D14
56Ω
MAX1419
15
INN
56Ω
0.1µF
GND
0.01µF
CLKP
CLKN
Figure 6. Transformer-Coupled Analog Input Configuration
AVCC DVCC DRVCC
POSITIVE
TERMINAL 0.1µF
T2-1T–KK81
T2-1T–KK81
INP
D0–D14
56Ω
MAX1419
56Ω
0.1µF
15
INN
GND
0.1µF
CLKP
CLKN
Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Transformer
However, the larger the turns ratio, the larger the effect
of the differential input resistance of the MAX1419 on
the primary referred input resistance. At a turns ratio of
1:4.47, the 1kΩ differential input resistance of the
MAX1419 by itself results in a primary referred input
resistance of 50Ω.
Although the center tap of the transformer in Figure 6 is
shown floating, it may be AC-coupled to ground.
However experience has shown that better balance is
achieved if the center tap is left floating.
As stated previously, the signal inputs to the MAX1419
must be accurately balanced to achieve the best even-
order distortion performance. Figure 7 provides
improved balance over the circuit of Figure 6 by adding
a balun on the primary side of the transformer, and can
yield substantial improvement in even-order distortion
terms over the circuit of Figure 6.
One note of caution in relation to transformers is important. Any DC current passed through the primary or
secondary windings of a transformer may magnetically
bias the transformer core. When this happens, the
transformer is no longer accurately balanced and a
degradation in the distortion of the MAX1419 may be
observed. The core must be demagnetized in order to
return to balanced operation.
______________________________________________________________________________________
13
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
POSITIVE
INPUT
TO INP
OA1
The MAX1427 evaluation board (MAX1427 EV kit) provides an excellent frame of reference for board layout,
and the discussion that follows is consistent with the
practices incorporated on the evaluation board.
Layer Assignments
RC1
RF1
RG1
OA3
FROM CM
RG2
RF1
RC2
OA2
TO INN
NEGATIVE
INPUT
Figure 8. DC-Coupled Analog Input Configuration
DC-Coupled Analog Input
While AC-coupling of the input signal is the proper
means for achieving the best dynamic performance, it
is possible to DC-couple the inputs by making use of
the CM potential. Figure 8 shows one method for
accomplishing DC-coupling. The common-mode
potentials at the outputs of amplifiers OA1 and OA2 are
“servoed” by the action of amplifier OA3 to be equal to
the CM potential of the MAX1419. Care must be taken
to ensure that the common-mode loop is stable, and
the R F /R G ratios of both half circuits must be well
matched to ensure balance.
PC Board Layout Considerations
The performance of any high-dynamic range, high
sample-rate converter may be compromised by poor
PC board layout practices. The MAX1419 is no exception to the rule, and careful layout techniques must be
observed in order to achieve the specified performance. Layout issues are addressed in the following
four categories:
1) Layer assignments
2) Signal routing
3) Grounding
4) Supply routing and bypassing
14
The MAX1427 EV kit is a six-layer board, and the
assignment of layers is discussed in this context. It is
recommended that the ground plane be on a layer
between the signal routing layer and the supply routing
layer(s). This practice prevents coupling from the supply lines into the signal lines. The MAX1427 EV kit PC
board places the signal lines on the top (component)
layer and the ground plane on layer 2. Any region on
the top layer not devoted to signal routing is filled with
ground plane with vias to layer 2. Layers 3 and 4 are
devoted to supply routing, layer 5 is another ground
plane, and layer 6 is used for the placement of additional components and for additional signal routing.
A four-layer implementation is also feasible using layer
1 for signal lines, layer 2 as a ground plane, layer 3 for
supply routing, and layer 4 for additional signal routing.
However, care must be taken to make sure that the
clock and signal lines are isolated from each other and
from the supply lines.
Signal Routing
In order to preserve good even-order distortion, the signal lines (those traces feeding the INP and INN inputs)
must be carefully balanced. To accomplish this, the signal traces should be made as symmetric as possible,
meaning that each of the two signal traces should be the
same length and should see the same parasitic environment. As mentioned previously, the signal lines must be
isolated from the supply lines to prevent coupling from
the supplies to the inputs. This is accomplished by making the necessary layer assignments as described in the
previous section. Additionally, it is crucial that the clock
lines be isolated from the signal lines. On the MAX1427
EV kit, this is done by routing the clock lines on the bottom layer (layer 6). The clock lines then connect to the
ADC through vias placed in close proximity to the
device. The clock lines are isolated from the supply lines,
as well as by virtue of the ground plane on layer 5.
The digital output traces should be kept as short as
possible to minimize capacitive loading. The ground
plane on layer 2 beneath these traces should not be
removed so that the digital ground return currents have
an uninterrupted path back to the bypass capacitors.
______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
Supply Bypassing
The MAX1427 EV kit uses 220µF capacitors on each
supply line (AVCC, DVCC, and DRVCC) to provide lowfrequency bypassing. The loss (series resistance)
associated with these capacitors is actually of some
benefit in eliminating high-Q supply resonances. Ferrite
BYPASSING—ADC LEVEL
beads are also used on each of the supply lines to
enhance supply bypassing (Figure 9).
Small value (0.01µF to 0.1µF) surface-mount capacitors
should be placed at each supply pin or each grouping
of supply pins to attenuate high-frequency supply noise
(Figure 9). It is recommended to place these capacitors
on the topside of the board and as close to the device
as possible with short connections to the ground plane.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1419 are measured using the histogram method with an input frequency of 15MHz.
BYPASSING—BOARD LEVEL
AVCC
FERRITE BEAD
DVCC
AVCC
0.1µF
0.1µF
GND
10µF
47µF
220µF
ANALOG
POWER-SUPPLY SOURCE
220µF
DIGITAL
POWER-SUPPLY SOURCE
220µF
OUTPUT DRIVER
POWER-SUPPLY SOURCE
GND
DVCC
FERRITE BEAD
D0–D14
MAX1419
15
10µF
0.1µF
47µF
DRVCC
FERRITE BEAD
GND
DRVCC
10µF
47µF
Figure 9. Grounding, Bypassing, and Decoupling Recommendations for MAX1419
______________________________________________________________________________________
15
MAX1419
Grounding
The practice of providing a split ground plane in an
attempt to confine digital ground return currents has
often been recommended in ADC application literature.
However, for converters such as the MAX1419, it is
strongly recommended to employ a single, uninterrupted ground plane. The MAX1427 EV kit achieves excellent dynamic performance with such a ground plane.
The EP of the MAX1419 should be soldered directly to
a ground pad on layer 1 with vias to the ground plane
on layer 2. This provides excellent electrical and thermal connections to the printed circuit
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1419’s DNL specification is measured with the histogram method based on a 15MHz input tone.
Dynamic Parameter Definitions
Single-Tone Spurious-Free
Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Spurious-Free
Dynamic Range (SFDRTT)
Aperture Delay
GND
GND
GND
GND
DRVCC
DAV
D14
D13
D12
D11
D10
D9
D8
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
GND 1
42 DRVCC
GND 2
41 DRVCC
GND 3
40 D7
CLKP 4
39 D6
CLKN 5
38 D5
GND 6
37 D4
36 D3
AVCC 7
MAX1419
AVCC 8
35 D2
GND 9
34 D1
INP 10
33 D0
32 DOR
INN 11
31 DRVCC
GND 12
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
AVCC
AVCC
GND
AVCC
AVCC
GND
GND
AVCC
30 GND
29 DVCC
AVCC
CM 13
GND 14
AVCC
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR in ADC. For a near-full-scale analog input signal
(-0.5dBFS to -1dBFS), thermal and quantization noise
are uniformly distributed across the frequency bins.
Error energy caused by transfer function nonlinearities
on the other hand is not distributed uniformly, but confined to the first few hundred odd-order harmonics.
BTS applications, which are the main target application
for the MAX1419 usually do not care about excess
noise and error energy in close proximity to the carrier
frequency or to DC. These low-frequency and sideband
errors are test system artifacts and are of no consequence to the BTS channel sensitivity. They are therefore excluded from the SNR calculation.
Pin Configuration
GND
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -7dB full scale.
GND
Aperture Jitter
The aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay.
SFDRTT represents the ratio of the RMS value of either
input tone to the RMS value of the peak spurious component in the power spectrum. This peak spur can be
an intermodulation product of the two input test tones.
GND
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
GND
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
QFN
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset.
16
______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
56L THIN QFN.EPS
______________________________________________________________________________________
17
MAX1419
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.