SIMTEK STK14EC16

STK14EC16
256Kx16 AutoStore nvSRAM
Preliminary
FEATURES
DESCRIPTION
• 15, 25, 45 ns Read Access and R/W Cycle Time
The Simtek STK14EC16 is a 4MB fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• Unlimited RECALL Cycles
• 200K STORE Endurance
• 20-Year Non-volatile Data Retention
• Single 3.0V +20%, -10% Operation
• Commercial, Industrial Temperatures
• 44-pin or 54-pin 400-mil TSOPII Packages (RoHSCompliant)
The Simtek nvSRAM is the highest performance,
most reliable non-volatile memory available.
• 48-ball Fine Pitch Ball Grid Array (FBGA)
BLOCK DIAGRAM
EEPROM Array
2048 x 2048
Row Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
STORE
SRAM
Array
RECALL
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Store/
Recall
Control
Input Buffers
DQ7
VCC
VCAP
2048 x 2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Power
Control
Software
Detect
HSB
A0 - A17
Column I/O
Column Decoder
A9
A10 A11 A12 A13 A14 A15 A16
G
W
E
UB
Pachuco Boys
LB
This is a product in development that has fixed target specifications that are subject to change pending characterization results.
SIMTEK Confidential & Proprietary
1
Document Control #ML0061 Rev 1.1
Jan, 2008
STK14EC16
Preliminary
Truth Table for SRAM Operations
Operating Mode
E
HSB
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Standby/not selected
H
H
X
X
X
X
High-Z
High-Z
L
H
H
H
X
X
High-Z
High-Z
L
H
X
X
H
H
High-Z
High-Z
Lower Byte Read
L
H
H
L
L
H
Data Outputs Low-Z
High-Z
Upper Byte Read
L
H
H
L
H
L
High-Z
Data Outputs Low-Z
Word Read
L
H
H
L
L
L
Data Outputs Low-Z
Data Outputs Low-Z
Lower Byte Write
L
H
L
X
L
H
Data Inputs High-Z
High-Z
Upper Byte Write
L
H
L
X
H
L
High-Z
Data Inputs High-Z
Word Write
L
H
L
X
L
L
Data Inputs High-Z
Data Inputs High-Z
Internal Read
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Jan, 2008
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STK14EC16
Preliminary
A0
1
44
A17
NC
1
54
A1
A2
2
43
A16
2
53
3
52
3
42
A15
NC
A0
A1
4
51
HSB
NC
A17
A16
A3
4
41
G
A2
A3
5
50
A15
6
49
A4
7
48
E
8
47
DQ0
9
46
G
UB
LB
DQ15
DQ1
DQ2
10
45
DQ14
44
DQ13
DQ3
VCC
VSS
12
DQ4
DQ5
DQ6
DQ7
W
A5
A6
A7
A8
23
A9
24
31
A10
NC
NC
NC
25
30
NC
26
29
NC
27
28
NC
A4
5
40
UB
E
DQ0
6
39
7
38
LB
DQ15
DQ1
8
37
DQ2
9
(TOP)
36
DQ14
DQ13
DQ12
DQ3
10
VCC
VSS
DQ4
11
34
12
33
VSS
VCC
13
32
DQ11
35
DQ5
DQ6
DQ7
14
31
DQ10
15
30
16
29
DQ9
DQ8
W
A5
A6
17
28
VCAP
18
27
A14
19
26
A7
20
25
A13
A12
A8
21
24
A11
A9
22
23
A10
44-Pin TSOP-II
11
(TOP)
43
DQ12
13
42
VSS
14
41
VCC
15
40
DQ11
16
39
17
38
DQ10
DQ9
18
37
DQ8
19
36
20
35
21
34
22
33
VCAP
A14
A13
A12
32
A11
1
2
3
4
5
6
LB
G
A0
A1
A2
NC
A
DQ 8
UB
A3
A4
E
DQ 0
B
DQ 9 DQ10
A5
A6
DQ1 DQ 2
C
VSS
A17
A7
DQ3
VCC
D
VCC DQ12 VCAP
A16
DQ4
VSS
E
DQ14 DQ13
A14
A15
DQ5 DQ 6
F
DQ15 HSB
A12
A13
W
DQ7
G
A9
A10
A11
NC
H
NC
DQ11
A8
(TOP)
48-Ball FBGA
54-Pin TSOP-II
(See full mechanical drawings on pages 18 – 20)
PIN DESCRIPTIONS
Pin Name
I/O
Description
A17-A0
Input
DQ15-DQ0
I/O
Address: The 18 address inputs select one of 262,144 words in the nvSRAM array
Data: Bi-directional 16-bit data bus for accessing the nvSRAM
E
Input
Chip Enable: The active low E input selects the device
LB
Input
Byte Write Select Input: Controls DQ7-DQ0 (unselected byte will not write or read).
UB
Input
Byte Write Select Input: Controls DQ15-DQ8 (unselected byte will not write or read).
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins
to tri-state.
VCC
Power Supply
Power: 3.0V +20%, -10%
HSB
I/O
Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.
(Connection Optional).
VCAP
Power Supply
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage elements.
VSS
Power Supply
Ground
NC
No Connect
This pin is not connected to the die. (Do not connect in design; reserved for future use)
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V
Voltage on Input Relative to VSS . . . . . . . . . .–0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TF (TSOP-II 44) PACKAGE THERMAL CHARACTERISTICS
θjc tbd; θja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
UF (TSOP-II 54) PACKAGE THERMAL CHARACTERISTICS
θjc tbd; θja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
BF (FBGA48) PACKAGE THERMAL CHARACTERISTICS
θjc tbd C/W; θja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
DC CHARACTERISTICS
(VCC = 2.7V-3.6V)
COMMERCIAL
SYMBOL
UNITS
MIN
ICC1
ICC2
ICC3
ICC4
ISB
INDUSTRIAL
PARAMETER
MAX
MIN
NOTES
MAX
Average VCC Current
tAVAV = 15ns
tAVAV = 25ns
tAVAV = 45ns
Dependent on output loading and cycle
rate. Values obtained without output
loads.
70
65
50
75
70
52
mA
mA
mA
6
6
mA
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE)
Average VCC Current during STORE
26
26
mA
W ≥ (V CC – 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output
loads.
Average VCAP Current during Auto Store
Cycle
6
6
mA
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE)
VCC Standby Current
(Standby, Stable CMOS Levels)
3
3
mA
Average VCC Current at tAVAV = 200ns
3V, 25°C, Typical
E ≥ (VCC -0.2V)
All Others VIN≤ 0.2V or ≥ (VCC-0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.0
VCC + 0.5
2.0
VCC + 0.5
V
All Inputs
VIL
Input Logic “0” Voltage
VSS –0.5
0.8
VSS –0.5
0.8
V
All Inputs
VOH
Output Logic “1” Voltage
V
IOUT = – 2mA (except HSB)
VOL
Output Logic “0” Voltage
0.4
V
IOUT = 4mA
TA
Operating Temperature
0
70
– 40
85
°C
VCC
Operating Voltage
2.7
3.6
2.7
3.6
V
3.3V nominal
VCAP
Storage Capacitance
61
134
61
180
μF
Between VCAP pin and VSS, 5V rated
(Nom. 68 μF to 150 μF +20%, - 10%)
NVC
Nonvolatile STORE operations
200
200
K
DATAR
Data Retention
20
20
Years
2.4
2.4
0.4
Note: The HSB pin has IOUT=-10 uA for VOH of 2.4 V. This parameter is characterized but not tested.
Document Control #ML0061 Rev 1.1
Jan, 2008
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@ 55 deg C
STK14EC16
Preliminary
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
CAPACITANCEb
SYMBOL
(TA = 25°C, f = 1.0MHz)
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
7
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms
OUTPUT
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
Figure 1: AC Output Loading
3.0V
577 Ohms
OUTPUT
789 Ohms
5 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
1
tAVAVc
tAVQVd
2
3
4
5
MIN
STK14EC16-25
MAX
MIN
15
STK14EC16-45
MAX
MIN
25
MAX
tACS
Chip Enable Access Time
tELEHc
tAVQVd
tRC
Read Cycle Time
tAA
Address Access Time
15
25
45
ns
tGLQV
tOE
Output Enable to Data Valid
10
12
20
ns
20
ns
15
Byte Enable to Data Valid
45
UNITS
tELQV
tBLQV
tAXQXd
STK14EC16-15
PARAMETER
Alt.
25
10
45
12
ns
ns
tAXQXd
tOH
Output Hold after Address Change
3
3
3
ns
7
tELQX
tLZ
Address Change or Chip Enable to
Output Active
3
3
3
ns
8
tEHQZe
tHZ
Address Change or Chip Disable to
Output Inactive
6
7
15
ns
tBLQX
tGLQX
tOLZ
Output Enable to Output Active
11
tGHQZe
tOHZ
Output Disable to Output Inactive
7
10
15
ns
12
tBHQZe
Byte Enable to Output Inactive
7
10
15
ns
13
tELICCHb
tEHICCLb
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
10
ns
9
Note c:
Note d:
Note e:
Note f:
7
15
10
14
Byte Enable to Output Active
10
0
0
0
0
0
15
0
25
SRAM READ CYCLE #1: Address Controlledc,d,f
tAVAV (2)
Address Valid
tAVQV
Data Output
(3)
Previous Data Valid
tAXQX (6)
Output Data Valid
SRAM READ CYCLE #2: E and G Controlledc,f
ADDR ESS
2
E
t E LE H
1
tEL Q V
6
29
t EHAX
11
t EHI CC L
t ELQ X
27
7
t EHQ Z
3
t AV QV
G
8
tG L Q X
9
t GH Q Z
4
t G L QV
DQ (D ATA OUT)
DAT A VAL ID
10
t ELI CC H
AC T IVE
I CC
ST AND BY
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
ns
45
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low, LB and UB select bytes read.
Measured ± 200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
Address
ns
ns
STK14EC16
Preliminary
SRAM WRITE CYCLES #1, #2, and #3
SYMBOLS
STK14EC16-15
NO.
STK14EC16-25
STK14EC16-45
PARAMETER
UNITS
#1
#2
#3
Alt.
15
tAVAV
tAVAV
tAVAV
tWC
Write Cycle Time
15
25
45
ns
16
tWLWH
tWLEH
tWLBH
tWP
Write Pulse Width
10
20
30
ns
17
tELWH
tELEH
tELBH
tCW
Chip Enable to End of Write
15
20
30
ns
18
tBLWH
tBLEH
tBLBH
Byte Enable to End of Write
15
20
30
ns
19
tDVWH
tDVEH
tDVBH
tDW
Data Set-up to End of Write
5
10
15
ns
20
tWHDX
tEHDX
tBHDX
tDH
Data Hold after End of Write
0
0
0
ns
21
tAVWH
tAVEH
tAVBH
tAW
Address Set-up to End of Write
10
20
30
ns
22
tAVWL
tAVEL
tAVBL
tAS
Address Set-up to Start of Write
0
0
0
ns
23
tWHAX
tEHAX
tBHAX
tWR
Address Hold after End of Write
0
0
0
ns
tWZ
Write Enable to Output Disable
tOW
Output Active after End of Write
24
25
t WLQZ
e, g
tWHQX
MIN
3
SRAM WRITE CYCLE #1: W Controlledg,h
tAVAV (15)
Address Valid
tWHAX (23)
tELWH (17)
E
tBLWH (18)
LB, UB
tAVWH (21)
tWLWH (16)
W
tAVWL
(22)
Input Data Valid
Data Input
tWLQZ (24)
Data Output
tWHDX (20)
tDVWH (19)
Previous Data
tWHQX (25)
High Impedance
SRAM WRITE CYCLE #2: E Controlledg,h
tAVAV (15)
Address Valid
Address
tAVWL (22)
tEHAX (23)
tELEH (17)
E
tBLEH (18)
LB , UB
tWLEH (16)
W
Data Input
tDVEH (19)
tEHDX (20)
Input Data Valid
High Impedance
Data Output
Document Control #ML0061 Rev 1.1
Jan, 2008
MIN
7
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be ≥ VIH during address transitions.
Address
MAX
7
Simtek Confidential
MAX
MIN
10
3
MAX
15
3
ns
ns
STK14EC16
Preliminary
SRAM WRITE CYCLE #3: LB, UB Controlledg,h
t AVAV (15)
Address
Address Valid
t ELBH (17)
E
t
AVBL
(22)
t
BLBH
t
(18)
BHAX
(23)
LB , UB
t AVBH (21)
t WLBH (16)
W
t BHDX (20)
t DVBH (19)
Input Data Valid
Data Input
High Impedance
Data Output
AutoStore™/POWER-UP RECALL
SYMBOLS
STK14EC16
NO.
PARAMETER
Standard
Alternate
MIN
26
tHRECALL
27
tSTORE
28
VSWITCH
Low Voltage Trigger Level
29
VCCRISE
VCC Rise Time
Note i:
Note j:
Power-up RECALL Duration
tHLHZ
STORE Cycle Duration
UNITS
NOTES
20
ms
i
12.5
ms
j
MAX
2.65
V
μs
150
tHRECALL starts from the time VCC rises above VSWITCH
If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStore™/POWER-UP RECALL
VCC
VSWITCH
(28)
tVCCRISE (29)
**
tSTORE (27)
**
tSTORE (27)
AutoStore
POWER-UP
RECALL
tHRECALL (26)
tHRECALL (26)
Read & Write
Inhibited
POWER-UP
BROWN OUT POWER-UP Read & Write POWER DOWN
Read & Write
AutoStore
RECALL
RECALL
AutoStore
** AutoStore occures only if at least one SRAM Write has happened
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
SOFTWARE-CONTROLLED STORE/RECALL CYCLEk.l
Symbols
NO.
E
Contk
G
STK14EC16-15
STK14EC16-25
STK14EC16-45
PARAMETER
Contk
Alternate
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
30
tAVAV
tAVAV
tRC
STORE/RECALL Initiation Cycle Time
15
25
45
ns
31
tAVEL
tAVGL
tAS
Address Set-up Time
0
0
0
ns
32
tELEH
tGLGH
tCW
Clock Pulse Width
12
20
30
ns
33
tEHAX
tGHAX
Address Hold Time
1
1
1
ns
34
tRECALL
tRECALL
RECALL Duration
150
150
150
l
μs
Note k: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs
Note l: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during
all six consecutive E or G controlled cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDl
30
t AVAV
ADDRESS #1
ADDRESS
31
t AVEL
E
30
t AVAV
ADDRESS #6
32
t ELEH
33
tEHAX
G
Deby
27
t STORE
/t
34
RECALL
HIGH IMPEDENCE
DQ (DATA)
DATA VALID
DATA VALID
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDl
30
t AVAV
30
t AVAV
ADDRESS #1
ADDRESS
ADDRESS #6
E
Pachuco Boys
31
32
t AVGL
t GLGH
G
27
t STORE
33
/
34
t RECALL
tGHAX
DQ (DATA)
DATA VALID
Document Control #ML0061 Rev 1.1
Jan, 2008
DATA VALID
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Simtek Confidential
HIGH IMPEDENCE
STK14EC16
Preliminary
HARDWARE STORE CYCLE
SYMBOLS
STK14EC16
PARAMETER
Standard
Alternate
35
tDELAY
tHLQZ
36
tHLHX
Hardware STORE to SRAM Disabled
Hardware STORE Pulse Width
MIN
MAX
1
70
15
Note m: On a hardware STORE initiation, SRAM operation continues to be enabled for time
tDELAY
UNITS
NOTES
μs
m
ns
to allow read/write cycles to complete
HARDWARE STORE CYCLE
36
t HLHX
HSB (IN)
27
t STORE
HSB (OUT)
35
t DELAY
DQ (DATA OUT)
SRAM Enabled
SRAM Enabled
Soft Sequence Commands
NO.
SYMBOLS
PARAMETER
STK14EC16
Standard
37
MIN
tSS
UNITS
NOTES
μs
n,o
MAX
Soft Sequence Processing Time
70
Note n: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
Note o: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
33
tss
Soft Sequence Command
ADDRESS
ADDRESS #1
33
tss
Soft Sequence Command
ADDRESS #6
ADDRESS #1
Vcc
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Jan, 2008
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Simtek Confidential
ADDRESS #6
STK14EC16
Preliminary
MODE SELECTION
E
W
G, UB, LB
A17-A0
Mode
I/O
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x08B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
L
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
L
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x08FC0
Nonvolatile Store
Output High Z
ICC2
0x04E38
0x0B1C7
0x083E0
0x07C1F
0x0703F
0x04C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
L
L
L
L
H
H
H
H
L
Notes
p,q,r
p,q,r
p,q,r
p,q,r
Note p: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile
cycle.
Note q: While there are 18 addresses on the STK14EC16, only the lower 16 are used to control software modes
Note r: I/O state depends on the state of G, UB, and LB. The I/O table shown assumes G, UB, and LB low.
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
nvSRAM OPERATION
nvSRAM
The STK14EC16 nvSRAM is made up of two functional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14EC16 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 200K STORE operations.
SRAM READ
The STK14EC16 performs a READ cycle whenever
E and G are low while W and HSB are high. The
address specified on pins A0-17 determine which of
the 262,144 data words will be accessed. Byte
enables (UB, LB) determine which bytes are
enabled to the output. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ
is initiated by E and G, the outputs will be valid at
tELQV or at tGLQV, whichever is later (READ cycle
#2). The data outputs will repeatedly respond to
address changes within the tAVQV access time without the need for transitions on any control input pins,
and will remain valid until another address change
or until E or G is brought high, or W and HSB is
brought low.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes
low.
AutoStore OPERATION
The STK14EC16 stores data to nvSRAM using one
of three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
Quantum Trap technology that is enabled by default
on the STK14EC16.
During normal operation, the device will draw current from VCC to charge a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCC pin drops below VSWITCH, the
part will automatically disconnect the VCAP pin from
VCC. A STORE operation will be initiated with power
provided by the VCAP capacitor.
Figure 3 shows the proper connection of the storage
capacitor (VCAP) for automatic store operation.
Refer to the DC CHARACTERISTICS table for the
size of the capacitor. The voltage on the VCAP pin is
driven to 3.6V by a regulator on the chip. A pull up
should be placed on W to hold it inactive during
power up.This pull-up is only effective if the W signal
SRAM WRITE
vCC
vCAP
W
Figure 3. AutoStore Mode
vCAP
12
Simtek Confidential
10K Ohm
Document Control #ML0061 Rev 1.1
Jan, 2008
vCC
0.1µF
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-15 will be written into memory if it is valid
tDVWH before the end of a W controlled WRITE or
tDVEH before the end of an E controlled WRITE. The
Byte Enable inputs (UB, LB) determine which bytes
are written.
STK14EC16
Preliminary
is tri-state during power up. Many MPU’s will tri-state
their controls on power up. This should be verified
when using the pullup. When the nvSRAM comes
out on power-on-recall, the MPU must be active or
the W held inactive until the MPU comes out of
reset.
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
HARDWARE STORE (HSB) OPERATION
The STK14EC16 provides the HSB pin for controlling and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14EC8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14EC16 will
continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until
HSB returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(VCC<VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete.
Document Control #ML0061 Rev 1.1
Jan, 2008
SOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence.
The STK14EC16 software STORE cycle is initiated
by executing sequential E controlled or G controlled
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are disabled until the cycle is completed.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address
0x4E38
Valid READ
2 Read Address
0xB1C7 Valid READ
3 Read Address
0x83E0
4 Read Address
0x7C1F Valid READ
Valid READ
5 Read Address
0x703F
6 Read Address
0x8FC0 Initiate STORE Cycle
Valid READ
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence and that G, UB, and LB are active. After
the tSTORE cycle time has been fulfilled, the SRAM
will again be activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
1 Read Address
0x4E38
Valid READ
2 Read Address
0xB1C7 Valid READ
3 Read Address
0x83E0
4 Read Address
0x7C1F Valid READ
Valid READ
5 Read Address
0x703F
Valid READ
6 Read Address
0x4C63
Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells.
13
Simtek Confidential
STK14EC16
Preliminary
After the tRECALL cycle time, the SRAM will once
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.Care must be taken so
the controlling falling edge is glitch and ring free so
as not to double clock the read address.
DATA PROTECTION
The STK14EC16 protects data from corruption during low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC<VSWITCH.
If the STK14EC16 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
NOISE CONSIDERATIONS
The STK14EC16 is a high-speed memory and so
must have a high-frequency bypass capacitor of 0.1
µF connected between both VCC pins and VSS
ground plane with no plane break to chip VSS. Use
leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of
power, ground, and signals will reduce circuit noise.
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the
following suggestions as best practices:
• The non-volatile cells in this nvSRAM product are
delivered from Simtek with 0x00 written in all
cells. Incoming inspection routines at customer or
contract manufacturer’s sites will sometimes
reprogram these values. Final NV patterns are
typically complex 4-byte pattern of 46 E6 49 53
hex or more random bytes. End product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory
content values to determine first time system configuration, cold or warm boot status, etc. should
always program a unique NV pattern (i.e., repeating 4-byte pattern of 46 E6 49 53 hex) as part of
the final system manufacturing test to ensure
these system routines work consistently.
Document Control #ML0061 Rev 1.1
Jan, 2008
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently
(program bugs, incoming inspection routines,
etc.).
• The autostore enabled/disabled feature will reset
to “autostore enabled” on every power down
event captured by the nvSRAM. The application
firmware should disable autostore on each reset
sequence that this behavior is desired.
• The Vcap value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max Vcap value because the nvSRAM
internal algorithm calculates Vcap charge time
based on this max Vcap value. Customers that
want to use a larger Vcap value to make sure
there is extra store charge and store time should
discuss their Vcap size selection with Simtek to
understand any impact on the Vcap voltage level
at the end of a tRECALL period.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14EC16 with
the benefit of power supply current that scales with
cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4
shows the relationship between ICC and READ/
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
VCC=3.6V, and chip enable at maximum frequency.
Only standby current is drawn when the chip is disabled. The overall average current drawn by the
STK14EC16 depends on the following items:
14
Simtek Confidential
1
The duty cycle of chip enable
2
The overall cycle rate for operations
3
The ratio of READs to WRITEs
4
The operating temperature
5
The VCC Level
6
I/O Loading
STK14EC16
Preliminary
PREVENTING AUTOSTORE
The AutoStore function can be disabled by initiating
an AutoStore Disable sequence. A sequence of
READ operations is performed in a manner similar
to the software STORE initiation. To initiate the
AutoStore Disable sequence, the following
sequence of E controlled or G controlled READ
operations must be performed:
Figure 4 - Current vs Cycle Time
1 Read Address
0x4E38
Valid READ
2 Read Address
0xB1C7 Valid READ
3 Read Address
0x83E0
4 Read Address
0x7C1F Valid READ
Valid READ
5 Read Address
0x703F
Valid READ
6 Read Address
0x8B45
AutoStore Disable
The AutoStore can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of READ
operations is performed in a manner similar to the
software RECALL initiation. To initiate the
AutoStore Enable sequence, the following
sequence of E controlled or G controlled READ
operations must be performed:
1 Read Address
0x4E38
2 Read Address
0xB1C7 Valid READ
Valid READ
3 Read Address
0x83E0
4 Read Address
0x7C1F Valid READ
5 Read Address
0x703F
Valid READ
6 Read Address
0x4B46
AutoStore Enable
Valid READ
If the AutoStore function is disabled or re-enabled,
a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore
state through subsequent power down cycles. The
part comes from the factory with AutoStore
enabled, but best design practice is to set the
enable or disable state during each power-up
sequence and not depend on this factory default
condition. Simtek recommends users configure the
part completely for the specific application.
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
ORDERING INFORMATION
STK14EC16-T F 45 I TR
Packing Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to +70 C)
I = Industrial (-40 to +85 C)
Access Time
15 = 15 ns
25 = 25 ns
45 = 45 ns
Lead Finish
F = Nickel/Palladium/Gold (Ni/Pd/Au)
Package
T = Plastic 44-pin 400 mil TSOPII (32 mil pitch)
U = Plastic 54-pin 400 mil TSOPII (32 mil pitch)
B = Plastic 48-pin FBGA (Fine Pitch Ball Grid Array)
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential
STK14EC16
Preliminary
Ordering Codes
Access Times
15 ns access time
15 ns access time
25 ns access time
25 ns access time
45 ns access time
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
3V 4M-16b AutoStore nvSRAM TSOP54-400
45 ns access time
15 ns access time
15 ns access time
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
25 ns access time
25 ns access time
45 ns access time
45 ns access time
15 ns access time
15 ns access time
25 ns access time
25 ns access time
45 ns access time
45 ns access time
15 ns access time
15 ns access time
25 ns access time
25 ns access time
45 ns access time
45 ns access time
15 ns access time
15 ns access time
25 ns access time
25 ns access time
45 ns access time
45 ns access time
15 ns access time
15 ns access time
25 ns access time
25 ns access time
45 ns access time
45 ns access time
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Part Number
2TK14EC16-TF15
STK14EC16-TF15TR
STK14EC16-TF25
STK14EC16-TF25TR
STK14EC16-TF45
Description
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
3V 4M-16b AutoStore nvSRAM
STK14EC16-TF45TR
STK14EC16-UF15
3V 4M-16b AutoStore nvSRAM TSOP44-400
3V 4M-16b AutoStore nvSRAM TSOP54-400
STK14EC16-UF15TR
STK14EC16-UF25
STK14EC16-UF25TR
STK14EC16-UF45
STK14EC16-UF45TR
STK14EC16-BF15
STK14EC16-BF15TR
STK14EC16-BF25
STK14EC16-BF25TR
STK14EC16-BF45
STK14EC16-BF45TR
STK14EC16-TF15I
STK14EC16-TF15ITR
STK14EC16-TF25I
STK14EC16-TF25ITR
STK14EC16-TF45I
STK14EC16-TF45ITR
STK14EC16-UF15I
STK14EC16-UF15ITR
STK14EC16-UF25I
STK14EC16-UF25ITR
STK14EC16-UF45I
STK14EC16-UF45ITR
STK14EC16-BF15I
STK14EC16-BF15ITR
STK14EC16-BF25I
STK14EC16-BF25ITR
STK14EC16-BF45I
STK14EC16-BF45ITR
Document Control #ML0061 Rev 1.1
Jan, 2008
TSOP44-400
TSOP44-400
TSOP44-400
TSOP44-400
TSOP44-400
TSOP54-400
TSOP54-400
TSOP54-400
TSOP54-400
FBGA48
FBGA48
FBGA48
FBGA48
FBGA48
FBGA48
TSOP44-400
TSOP44-400
TSOP44-400
TSOP44-400
TSOP44-400
TSOP44-400
TSOP54-400
TSOP54-400
TSOP54-400
TSOP54-400
TSOP54-400
TSOP54-400
FBGA48
FBGA48
FBGA48
FBGA48
FBGA48
FBGA48
17
Simtek Confidential
Commercial
STK14EC16
Preliminary
PACKAGE DIAGRAMS
54-Pin TSOPII
Pin 1
Index
Top View
1
27
0.404
0.396
(
10.262
10.058
)
0.470
0.462
(
)
11.938
11.735
54
28
0.886
0.878
(
0.404 10.262
0.396 10.058
(
)
22.517
22.313
)
0°
5°
0.0235
0.0160
0.0315
(0.800)
0.047
0.039
1.194
0.991
(
( )
0.597
0.406
0.016
0.012
BSC
( 0.400
0.300 )
)
Base
Plane
0.729
0.721
(
Seating
Plane
)
18.517
18.313
0.150
0.050
DIM = INCHES
DIM = mm
MIN
MAX
( )
Document Control #ML0061 Rev 1.1
Jan, 2008
MIN
MAX
18
Simtek Confidential
(
0.0059
0.0020
)
0.004 (0.10)
STK14EC16
Preliminary
44-Pin TSOPII
Pin 1
Index
Top View
22
1
0.404
0.396
(
)
10.262
10.058
0.470
0.455
(
)
11.938
11.735
44
23
0.404
0.396
( )
10.262
10.058
0°
5°
0.0235
0.0160
0.0315
(0.800)
0.047
0.039
0.016
0.012
BSC
0.597
0.406
)
0.400
0.300
(
)
Base
Plane
1.194
0.991
(
( )
0.729
0.721
Seating
Plane
)
18.517
18.313
(
0.150
0.050
MIN
MAX
DIM = INCHES
DIM = mm
Document Control #ML0061 Rev 1.1
Jan, 2008
( )
MIN
MAX
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Simtek Confidential
(
)
0.0059
0.0020
0.004 (0.10)
STK14EC16
Preliminary
48-Ball FBGA
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M CA
A1 CORNER
1
2
A1 CORNER
00.30 ± 0.05(48X)
3
4
5
6
6
5
4
3
2
1
A
+
A
B
+
B
C
D
E
F
2.625
E
D
5.25
10.00 ± 0.10
0.75
C
10.00 ± 0.10
B
F
G
G
+
H
A
A
B
+
1.875
6.00 ± 0.10
0.75
3.75
B
0.15C
0.21 ± 0.05
0.53 ± 0.05
SEATING PLANE
C
Document Control #ML0061 Rev 1.1
Jan, 2008
120 MAX
0.36
//
0.25C
0.15(4x)
20
Simtek Confidential
6.00 ± 0.10
+
H
STK14EC16
Preliminary
Document Revision History
Rev
Date
Change
1.0
April 2007
Moved to Preliminary from Advance Information
1.1
January 2008
–
made clear that nominal supply is 3.3V, not 3.0V (range 2.7V to 3.6V)
–
modified language on pin description of HSB and NC.
–
changed ISB from 1mA to 2mA.
–
changed Icc3 from 8mA to 26mA
–
clarified description language of Figure 3
–
clarified description language of Software Recall
–
clarified description language of Preventing Autostore
–
corrected typo on Industrial temp range: -45 to -40
Made the following changes to the document
–
page 1: revised block diagram
–
page 3: added new 48 FBGA information, bock diagram, and package diagram; added
pin descriptions for pins E, LB, UB, and W.
–
page 4: added thermal characteristics. In the DC Characteristics table, revised values for
Icc2, Icc4, ISB, VIH, and VCAP;and changed Industrial Max Value of VCAP to 180 and
revised VCAP notes. Added “(except HSB)” to notes for Output Logic “1” Voltage.
–
page 6: in SRAM Read Cycles #1 & #2 table, revised description for tELQX and tEHQZ and
changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing
diagramand changed title to add G controlled.
–
page 7: in SRAM Write Cycles, added symbol #3.
–
page 8: added new SRAM Write Cycle #3. In AutoStore/Power-Up Recall table, changed
max value for #27 (tSTORE) to 12.5. Revised AutoStore/Power-Up Recall section.
–
page 9: in Software-Controlled Store/Recall Cycle table, revised values for tRECALL;
revised the notes below the Software-Controlled Store/Recall Cycle diagram.
–
page 11: in Mode Selection table, changed column to A17-A0. In the values in this column,
added a zero after each instance of “0x”; changed AutoStore Enable value to
0x04B46.
–
page 12: in Auto-Store Operation, deleted line about VCAP pin being driven to 5V by a
charge pump internal to the chip. Also, Added Stefan's revised text (italics show revision):
"Refer to the DC CHARACTERISTICS table for the size of the capacitor."
–
page 13: under Hardware Store (HSB) Operation, revised first paragraph to read “The
HSB pin has a very resistive pullup...”
–
page 14: added best practices section.
–
page 16: in Ordering Information, Lead Finish, replaced “Sn (Matte Tin) RoHS Compliant”
with “Nickel/Palladium/Gold (Ni/Pd/Au).” Also, added “B = Plastic 48-pin FBGA (Fine
Pitch Ball Grid Array)” to Finish.
–
page 17: in Ordering Codes, added ordering information for 48 FBGA and added access
times column.
Document Control #ML0061 Rev 1.1
Jan, 2008
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Simtek Confidential