SIMTEK STK14C88

STK14C88
32Kx8 AutoStore nvSRAM
FEATURES
DESCRIPTION
• 25, 35, 45 ns Read Access & R/W Cycle Time
The Simtek STK14C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
• Non-Volatile STORE Under Hardware or
Software Control
• Automatic RECALL to SRAM on Power Up
Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial, Industrial, Military Temperatures
The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
• 32-Pin 300 mil SOIC (RoHS-Compliant)
• 32-pin CDIP and LCC Packages
BLOCK DIAGRAM
VCCX
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INPUT BUFFERS
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
Quantum Trap
512 x 512
VCAP
POWER
CONTROL
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
COLUMN I/O
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0014 Rev 0.3
February 2007
STK14C88
PIN CONFIGURATIONS
VCAP
A14
A12
A7
A6
A5
A4
A3
1
32
2
31
30
NC
A2
A1
A0
DQ0
DQ1
DQ2
VSS
9
25
24
10
23
11
12
22
3
4
29
5
28
27
6
7
8
26
21
20
13
14
15
19
16
17
18
VCCX
HSB
W
A13
A8
A9
A11
G
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
32-Pin 450 mil LCC
32-Pin 300 mil SOIC
32-Pin 300 mil CDIP
PIN DESCRIPTIONS
Pin Name
I/O
Description
A14-A0
Input
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
DQ7-DQ0
I/O
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
E
Input
Chip Enable: The active low E input selects the device
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
VCCX
Power Supply
Power: 5.0V, ± 10%
HSB
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
VCAP
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
VSS
Power Supply
Ground
Document Control #ML0014 Rev 0.3
February, 2007
2
STK14C88
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(VCC = 5.0V ± 10%)e
DC CHARACTERISTICS
INDUSTRIAL/
Military
COMMERCIAL
SYMBOL
PARAMETER
MIN
MAX
MIN
UNITS
NOTES
MAX
ICC1b
Average VCC Current
97
80
70
100
85
70
mA
mA
mA
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
ICC2c
Average VCC Current during STORE
3
3
mA
All Inputs Don’t Care, VCC = max
Average VCC Current at tAVAV = 200ns
5V, 25°C, Typical
10
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS Levels
ICC4c
Average VCAP Current during AutoStore
Cycle
2
2
mA
ISB1d
Average VCC Current
(Standby, Cycling TTL Input Levels)
30
25
22
31
26
23
mA
mA
mA
tAVAV = 25ns, E ≥ VIH
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
ISB2d
VCC Standby Current
(Standby, Stable CMOS Input Levels)
1.5
1.5
mA
E ≥ (V CC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±5
±5
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.2
VCC + .5
2.2
VCC + .5
V
VIL
Input Logic “0” Voltage
VSS – .5
0.8
VSS – .5
0.8
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
VBL
Logic “0” Voltage on HSB Output
TA
Operating Temperature
ICC3
b
Note b:
Note c:
Note d:
Note e:
2.4
V
All Inputs
IOUT = – 4mA except HSB
V
IOUT = 8mA except HSB
0.4
V
IOUT = 3mA
85/125
°C
0.4
0.4
0
70
- 40/-55
ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) .
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground.
AC TEST CONDITIONS
5.0V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
f
CAPACITANCE
SYMBOL
PARAMETER
(TA = 25°C, f = 1.0MHz)
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
5
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
Note f:
All Inputs
V
2.4
0.4
All Inputs Don’t Care
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
These parameters are guaranteed but not tested.
Document Control #ML0014 Rev 0.3
February 2007
480 Ohms
3
STK14C88
(VCC = 5.0V ± 10%)e
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK14C88-25
STK14C88-35
STK14C88-45
MIN
MIN
MIN
PARAMETER
#1, #2
Alt.
tELQV
UNITS
MAX
MAX
tACS
Chip Enable Access Time
2
tAVAV
g
tRC
Read Cycle Time
3
tAVQVh
tAA
Address Access Time
25
35
45
ns
4
tGLQV
tOE
Output Enable to Data Valid
10
15
20
ns
5
tAXQXh
tOH
Output Hold after Address Change
5
5
5
ns
6
tELQX
tLZ
Chip Enable to Output Active
5
5
5
ns
7
tEHQZi
tHZ
Chip Disable to Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
1
9
tGHQZ
i
25
25
35
MAX
35
45
10
0
tOHZ
Output Disable to Output Inactive
10
tELICCH
f
tPA
Chip Enable to Power Active
11
tEHICCLf
tPS
Chip Disable to Power Standby
45
13
0
10
0
13
0
35
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2
tAVAV
ADDRESS
3
tAVQV
tAXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledg
2
tAVAV
ADDRESS
E
1
tELQV
6
11
tEHICCL
tELQX
7
tEHQZ
G
9
tGHQZ
4
8
tGLQX
tGLQV
DQ (DATA OUT)
DATA VALID
10
tELICCH
ACTIVE
ICC
STANDBY
Document Control #ML0014 Rev 0.3
February, 2007
4
ns
ns
15
ns
45
ns
0
25
5
ns
15
0
ns
ns
STK14C88
(VCC = 5.0V ± 10%)e
SRAM WRITE CYCLES #1 & #2
SYMBOLS
STK14C88-25
NO.
STK14C88-35
STK14C88-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
MAX
MIN
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
35
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
0
ns
20
t WLQZ i, j
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
10
5
MAX
13
5
SRAM WRITE CYCLE #1: W Controlledk, l
12
tAVAV
ADDRESS
19
tWHAX
E
17
tAVWH
18
tAVWL
13
tWLWH
W
15
tDVWH
DATA IN
16
tWHDX
DATA VALID
20
tWLQZ
DATA OUT
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
tAVAV
ADDRESS
18
tAVEL
14
tELEH
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
DATA IN
DATA OUT
Document Control #ML0014 Rev 0.3
February 2007
16
tEHDX
DATA VALID
HIGH IMPEDANCE
5
MAX
15
5
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
14
tELWH
MIN
ns
ns
STK14C88
HARDWARE MODE SELECTION
E
W
HSB
A13 - A0 (hex)
MODE
I/O
POWER
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile STORE
Output High Z
lCC2
NOTES
t
m
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
(VCC = 5.0V ± 10%)e
HARDWARE STORE CYCLE
SYMBOLS
STK14C88
NO.
PARAMETER
Standard
Alternate
MIN
22
tSTORE
tHLHZ
STORE Cycle Duration
23
tDELAY
tHLQZ
Time Allowed to Complete SRAM Cycle
24
tRECOVER
tHHQX
Hardware STORE High to Inhibit Off
25
tHLHX
Hardware STORE Pulse Width
26
tHLBL
Hardware STORE Low to STORE Busy
UNITS
NOTES
ms
i, n
μs
i, n
ns
n, o
MAX
10
1
700
15
ns
300
ns
Note n: E and G low and W high for output behavior.
Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
tHLHX
HSB (IN)
24
tRECOVER
22
tSTORE
26
tHLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
23
tDELAY
DQ (DATA OUT)
DATA VALID
DATA VALID
Document Control #ML0014 Rev 0.3
February, 2007
6
STK14C88
(VCC = 5.0V ± 10%)e
AutoStore/POWER-UP RECALL
SYMBOLS
STK14C88
NO.
PARAMETER
Standard
UNITS
NOTES
550
μs
p
STORE Cycle Duration
10
ms
n, q
Low Voltage Trigger (VSWITCH) to HSB Low
300
ns
l
μs
n
Alternate
MIN
Power-up RECALL Duration
27
tRESTORE
28
tSTORE
29
tVSBL
30
tDELAY
31
VSWITCH
Low Voltage Trigger Level
32
VRESET
Low Voltage Reset Level
tHLHZ
tBLQZ
Time Allowed to Complete SRAM Cycle
MAX
1
4.0
4.5
V
3.6
V
Note p: tRESTORE starts from the time VCC rises above VSWITCH.
Note q: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore/POWER-UP RECALL
VCC
31
VSWITCH
32
VRESET
AutoStore
POWER-UP RECALL
29
tVSBL
27
tRESTORE
28
tSTORE
HSB
30
tDELAY
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
AutoStore
BROWN OUT
AutoStore
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Document Control #ML0014 Rev 0.3
February 2007
7
STK14C88
SOFTWARE STORE/RECALL MODE SELECTION
E
L
L
W
A13 - A0 (hex)
MODE
I/O
POWER
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
SYMBOLS
r, s, t
lCC2
r, s, t
Active
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
(VCC = 5.0V ± 10%)e
STK14C88-25
NO.
NOTES
STK14C88-35
STK14C88-45
PARAMETER
UNITS NOTES
Standard
Alternate
33
tAVAV
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
n
34
tAVEL
tAS
Address Set-up Time
0
0
0
ns
u
35
tELEH
tCW
Clock Pulse Width
20
25
30
ns
u
36
tELAX
Address Hold Time
20
20
20
ns
u
37
tRECALL
RECALL Duration
Note r:
Note s:
Note t:
Note u:
Note v:
MIN
MAX
MIN
20
MAX
MIN
20
MAX
20
μs
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes.
I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
The software sequence is clocked with E controlled READs.
The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a
STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv
33
33
tAVAV
ADDRESS
tAVAV
ADDRESS #1
34
tAVEL
ADDRESS #6
35
tELEH
E
36
tELAX
28
tSTORE
DQ (DATA
DATA VALID
DATA VALID
Document Control #ML0014 Rev 0.3
February, 2007
8
37
/ tRECALL
HIGH IMPEDANCE
STK14C88
nvSRAM OPERATION
The STK14C88 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to nonvolatile elements (the STORE
operation) or from nonvolatile elements to SRAM
(the RECALL operation). In this mode SRAM functions are disabled.
NOISE CONSIDERATIONS
The STK14C88 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1μF connected between VCAP and
VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A0-14 determines which of
the 32,768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the tAVQV access time without the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
Document Control #ML0014 Rev 0.3
February 2007
9
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK14C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK14C88 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
STK14C88
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the nonvolatile
elements. The nonvolatile data can be recalled an
unlimited number of times.
AutoStore OPERATION
The STK14C88 can be powered in one of three
modes.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
If the power supply drops faster than 20 μs/volt
before VCCX reaches VSWITCH, then a 2.2 ohm resistor
should be inserted between VCCX and the system
supply to avoid momentary excess of current
between Vccx and Vcap.
10kΩ∗
During normal AutoStore operation, the STK14C88
will draw current from VCCX to charge a capacitor
connected to the VCAP pin. This stored charge will be
used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part will automatically
disconnect the VCAP pin from VCCX and initiate a
STORE operation.
If an automatic STORE on power loss is not required,
then VCCX can be tied to ground and + 5V applied to
VCAP (Figure 4). This is the AutoStore Inhibit mode,
in which the AutoStore function is disabled. If the
STK14C88 is operated in this configuration, references to VCCX should be changed to VCAP throughout
this data sheet. In this mode, STORE operations may
be triggered through software control or the HSB
pin. It is not permissable to change between these
three options “on the fly”.
1
32
10kΩ
10kΩ∗
1
32
31
1
32
31
31
30
30
0.1μF
Bypass
+
0.1μF
Bypass
68μF
6v, ±20%
30
16
16
17
16
17
17
Figure 2: AutoStore Mode
Figure 3: System Power Mode
*If HSB is not used, it should be left unconnected.
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February, 2007
10
Figure 4: AutoStore
Inhibit Mode
10kΩ
Read address
Read address
Read address
Read address
Read address
Read address
10kΩ∗
1.
2.
3.
4.
5.
6.
In system power mode (Figure 3), both VCCX and
VCAP are connected to the + 5V power supply without
the 68μF capacitor. In this mode the AutoStore function of the STK14C88 will operate on the stored system charge as power goes down. The user must,
however, guarantee that VCCX does not drop below
3.6V during the 10ms STORE cycle.
0.1μF
Bypass
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ operations must be performed:
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68μF and
220μF (± 20%) rated at 6V should be provided.
10kΩ
SOFTWARE NONVOLATILE RECALL
STK14C88
HSB OPERATION
PREVENTING STORES
The STK14C88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK14C88 will
conditionally initiate a STORE operation after tDELAY;
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a
driver.
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20μs at the onset of a STORE. When
the STK14C88 is connected for AutoStore operation
(system VCC connected to VCCX and a 68μF capacitor
on VCAP) and VCC crosses VSWITCH on the way down,
the STK14C88 will attempt to pull HSB low; if HSB
doesn’t actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt.
SRAM READ and WRITE operations that are in
The STK14C88 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs will be inhibited.
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14C88 will
continue SRAM operations for tDELAY. During tDELAY,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
STK14C88s while using a single larger capacitor. To
operate in this mode the HSB pin should be connected together to the HSB pins from the other
STK14C88s. An external pull-up resistor to + 5V is
required since HSB acts as an open drain pull down.
The VCAP pins from the other STK14C88 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK14C88s detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request
a STORE cycle (a STORE will take place in those
STK14C88s that have been written since the last
nonvolatile cycle).
During any STORE operation, regardless of how it
was initiated, the STK14C88 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK14C88 will remain disabled until the HSB
pin returns high.
If HSB is not used, it should be left unconnected.
Document Control #ML0014 Rev 0.3
February 2007
11
HARDWARE PROTECT
AutoStore can be completely disabled by tying VCCX
to ground and applying + 5V to VCAP. This is the
AutoStore Inhibit mode; in this mode STOREs are only
initiated by explicit request using either the software
sequence or the HSB pin.
LOW AVERAGE ACTIVE POWER
The STK14C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK14C88 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
STK14C88
100
Average Active Current (mA)
Average Active Current (mA)
100
80
60
40
TTL
20
80
60
TTL
40
CMOS
20
CMOS
0
0
50
100
150
Cycle Time (ns)
200
50
Figure 5: Icc (max) Reads
Document Control #ML0014 Rev 0.3
February, 2007
100
150
Cycle Time (ns)
Figure 6: Icc (max) Writes
12
200
STK14C88
Commercial and Industrial Ordering Information
STK14C88 - N F 45 I TR
Packaging Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
N = Plastic 32-pin 300 mil SOIC
C = Ceramic 32-pin 300 mil CDIP
L = Ceramic 32-pad LCC
Document Control #ML0014 Rev 0.3
February 2007
13
STK14C88
Military Ordering Information
STK14C88 - 5 C 45 M
Temperature Range
M = Military (-55 to 125°C)
Access Time
35 = 35ns
45 = 45ns
Package
L=Ceramic 32-pad LCC
C=Ceramic 32-pin 300 mil CDIP
K=Ceramic 32-pin 300 mil CDIP
with solder dip finish
Retention / Endurance
5 = Military (10 years or 105cycles)
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February, 2007
14
STK14C88
Ordering Information
Part Number
STK14C88-NF25
Description
5V 32Kx8 AutoStore nvSRAM SOP32-300
Commercial
STK14C88-NF35
STK14C88-NF45
5V 32Kx8 AutoStore nvSRAM SOP32-300
5V 32Kx8 AutoStore nvSRAM SOP32-300
Commercial
Commercial
STK14C88-NF25TR
STK14C88-NF35TR
5V 32Kx8 AutoStore nvSRAM SOP32-300
5V 32Kx8 AutoStore nvSRAM SOP32-300
Commercial
Commercial
STK14C88-NF45TR
STK14C88-NF25I
STK14C88-NF35I
STK14C88-NF45I
STK14C88-NF25ITR
STK14C88-NF35ITR
STK14C88-NF45ITR
STK14C88-C45I
STK14C88-L45I
STK14C88-5L35M
STK14C88-5L45M
STK14C88-5C35M
STK14C88-5C45M
STK14C88-5K35M
STK14C88-5K45M
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Military
Military
Military
Military
Military
Military
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
Document Control #ML0014 Rev 0.3
February 2007
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
AutoStore
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
nvSRAM
15
Temperature
SOP32-300
SOP32-300
SOP32-300
SOP32-300
SOP32-300
SOP32-300
SOP32-300
CDIP32-300
LCC32-450
LCC32-450
LCC32-450
CDIP32-300
CDIP32-300
CDIP32-300
CDIP32-300
STK14C88
Package Diagrams
32 Lead 300 mil SOIC Gull Wing
0.292 7.42
0.300 7.60
(
)
0.405 10.29
0.419 10.64
(
)
Pin 1
Index
.050 (1.27)
0.810 20.57
0.822 20.88
(
0.026 0.66
0.032 0.81
(
BSC
)
)
0.090 2.29
0.100 2.54
( )
0.086
0.090
0.12
0.22
( )
0.004 0.10
0.010 0.25
( )
0.014 0.36
0.020 0.51
0.006
0.013
0
0.15
0.32
( )
8
0.021
0.041
DIM = INCHES
DIM = mm
Document Control #ML0014 Rev 0.3
February, 2007
16
MIN
MAX
MIN
( MAX
)
0.53
( 1.04
)
o
o
2.18
( 2.29
)
STK14C88
32 Lead 300 mil Side Braze DIL
1.585
1.615
(40.25
41.02)
.280
.310
( 7.36
7.87 )
Pin 1
Index
PIN
16
( )
----.060 1.52
( )
.124 3.15
.162 4.12
.125 (3.18)
MIN
.016
.020
.048
.052
( )
0.41
0.51
.290
.310
( )
( 7.37
7.87 )
.009
.012
.300
.320
( 7.62
8.13 )
DIM = INCHES
DIM = mm
Document Control #ML0014 Rev 0.3
February 2007
.090
.110
1.22
1.32
MIN
MAX
MIN
( MAX
)
17
( 0.23
0.30 )
)
( 2.29
2.79
.040
.060
1.02
1.52
( )
STK14C88
32 Lead 450 mil Ceramic LCC
.080±.008
.060±.006
.550±.005
.020±.002
.020±.002
(.040)
Pad 1
.310±.006
.450±.005
Pad 32
.360±.006
(.020X2)
C.040±.010
C.020±.010
.002
TYP
.050±.005
.450-.010 +.005
M
15
.0
(R.009)
IN
.050
.300
[P=.050X6]
Pad 1 Index
Pad 32
.085±.008
.350-.010 +.005
(C.004)
.050
.400
[P=.050X8]
Document Control #ML0014 Rev 0.3
February, 2007
TYP
.050±.005
.025±.003
18
NOTES:
1. GOLD PLATE 85~220‚ INCHES OVER 50~350 INCHES NICKEL.
2. PADS "A" AND "B" ELECTRICALLY CONNECTED TO THE DIE ATTACH PAD.
3. SEAL RING TO BE ELECTRICALLY ISOLATED FROM ALL LEADS.
4. LEAD RESISTANCE : 800mƒ MAX.
5. LEAD TO LEAD CAPACITANCE NOT TO EXCEED 3pf (1MHz).
6. BLACK ALUMINA CERAMIC.
STK14C88
Document Revision History
Revision
Date
Summary
0.0
December 2002
Removed 20 nsec device; Combined commercial, industrial and military; current limit resistor
added for extreme power-off slew rate.
0.1
September 2003
Added lead-free lead finish
0.2
March 2003
Removed Commercial/Industrial Leaded Lead Finish, Removed “W” DIP package
0.3
February 2007
Add Tape Reel Ordering Options
Add Product Ordering Code Listing
Add Package Drawings
Reformat Entire Document
SIMTEK STK14C88 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Document Control #ML0014 Rev 0.3
February 2007
19