HOLTEK HT46R71D

HT46R71D
A/D with LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0007E Using the MCU Look Up Table Instructions
- HA0049E Read and Write Control of the HT1380
Features
· Operating voltage:
· RC oscillator
fSYS=4MHz: 2.2V~5.5V
· HALT function and wake-up feature reduce power
· 10 bidirectional I/O lines and two ADC input
consumption
· One external interrupt input shard with an I/O lines
· Voltage regulator (3.3V) and charge pump
· One 8-bit and one 16-bit programmable timer/event
· Embeded voltage reference generator (1.5V)
counter with overflow interrupt a 7-stage pre-scalar
· 4-level subroutine nesting
· LCD driver with 10´3 segments
· Bit manipulation instruction
· 2K´14 program memory
· 14-bit table read instruction
· 32´8 data memory RAM
· Up to 1ms instruction cycle with 4MHz system clock
· Single differential input channel dual slope Analog to
· 63 powerful instructions
Digital Converter with Operational Amplifier.
· All instructions in 1 or 2 machine cycles
· Watchdog Timer
· Low voltage reset/detector function
· Buzzer output
· 48-pin SSOP package
· Internal 12kHz RC oscillator
General Description
in addition to a flexible and configurable LCD interface
enhance the versatility of these devices to control a
wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement
tools, motor driving, etc., for both industrial and home
appliance application areas.
The HT46R71D is an 8-bit, high performance, RISC architecture microcontroller device specifically designed
for A/D product applications that interface directly to analog signals and which require an LCD Interface.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D
Converter, LCD display, HALT and wake-up functions,
Rev. 1.00
1
January 9, 2006
HT46R71D
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
R O M
S T A C K
P ro g ra m
C o u n te r
In s tr u c tio n
R e g is te r
IN T C
M
M P
U
T M R 0 C
T M R 0
M
T M R 1 C
T M R 1
M
M U X
P B C
P o rt B
S T A T U S
T im in g
G e n e r a tio n
S h ifte r
P A C
P o rt A
P A
B P
O S C 2
V D D
O S
R E
V D
V S
S
D
S
C 1
A C C
H A L T
L C D
M e m o ry
C h a rg e
P u m p
Rev. 1.00
R e g u la to r
fS
X
Y S
In t. R C
O S C
P A 5 /T M R 1
U
X
P r e s c a le r
M
U
X
Y S
M
U
fS
Y S
/4
In t. R C O S C
X
/4
In t. R C O S C
P B 0 ~ P B 1
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
/B Z
/B Z
/T M R 0
/T M R 1
/IN T 0
E N /D IS
L V D /L V R
L C D D r iv e r
V O C H P
V O R E G
U
P A 4 /T M R 0
W D T
P B
A L U
X
fS
W D T
P r e s c a le r
In s tr u c tio n
D e c o d e r
U
D A T A
M e m o ry
X
M
P r e s c a le r
C O M 0 ~ C O M 2
1 -C h a n n e l
D u a l- S lo p e
C o n v e rte r
w ith O P
S E G 0 ~ S E G 9
2
D O
D O
D O
D C
D S
D S
D S
P A P
P A N
P A O
H O P
R R
R C
C C
January 9, 2006
HT46R71D
Pin Assignment
P A 0 /B Z
1
4 8
R E S
P A 1 /B Z
2
4 7
O S C 1
P A 2
3
4 6
O S C 2
P A 3
4
4 5
V D D
P A 4 /T M R 0
5
4 4
N C
P A 5 /T M R 1
6
4 3
S E G 0
P A 6 /IN T
7
4 2
S E G 1
P A 7
8
4 1
S E G 2
V S S
9
4 0
S E G 3
V O B G P
1 0
3 9
S E G 4
C H P C 2
1 1
3 8
S E G 5
C H P C 1
1 2
3 7
S E G 6
V O C H P
1 3
3 6
S E G 7
V O R E G
1 4
3 5
S E G 8
A V S S
1 5
3 4
S E G 9
N C
1 6
3 3
C O M 2
N C
1 7
3 2
C O M 1
N C
1 8
3 1
C O M 0
D O P A P
1 9
3 0
V L C D
D O P A N
2 0
2 9
P B 1
D O P A O
2 1
2 8
P B 0
D C H O P
2 2
2 7
N C
D S R R
2 3
2 6
N C
D S R C
2 4
2 5
D S C C
H T 4 6 R 7 1 D
4 8 S S O P -A
Pin Description
Pin Name
I/O
Options
Description
PA0/BZ
PA1/BZ
PA2
PA3
PA4/TMR0
PA5/TMR1
PA6/INT
PA7
I/O
Wake-up
Pull-high
Buzzer
Bidirectional 8-bit input/output port. Each individual bit on this port can
be configured to have a wake-up function using a configuration option.
Software instructions determine the CMOS output or Schmitt trigger input. Configuration options determine which pin on this port has
pull-high resistors. The BZ, BZ, TMR0, TMR1 and INT are pin-shared
with PA0, PA1, PA4, PA5 and PA6 respectively.
PB0~PB1
I/O
Pull-high
Bidirectional 2-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on this port have pull-high resistors.
VLCD
I
¾
COM0~COM2
O
1/2 or 1/3 Duty
SEG0~SEG9
O
Segment
Output
VOBGP
AO
¾
Bandgap voltage output pin. (for external use)
VOREG
O
¾
Regulator output 3.3V
VOCHP
O
¾
Charge pump output (a capacitor is required to be connected)
CHPC1
¾
¾
Charge pump capacitor, positive
CHPC2
¾
¾
Charge pump capacitor, negative
Rev. 1.00
LCD power supply
COM0~COM2 are the common outputs for the LCD panel plate.
LCD driver outputs for the LCD panel segments.
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January 9, 2006
HT46R71D
Pin Name
I/O
Options
Description
DOPAN,
DOPAP,
DOPAO,
DCHOP
AI/AO
¾
Dual Slope converter pre-stage OPA related pins. DOPAN is OPA
Negative input pin, DOPAP is OPA Positive input pin, DOPAO is OPA
output pin and the DCHOP is OPA Chopper pins.
DSRR,
DSRC,
DSCC
AI/AO
¾
Dual slope AD converter main function RC circuit. DSRR is the input or
reference signal, DSRC is the Integrator negative input, and DSCC is
the comparator negative input.
OSC1
OSC2
I
O
External RC
OSC1, OSC2 are connected to an external RC network for the internal
system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock.
RES
I
¾
Schmitt trigger reset input, active low
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
AVSS
¾
¾
Analog negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
VDD
VDD
Operating Voltage
¾
fSYS=4MHz
2.2
¾
5.5
V
IDD1
Operating Current
(External RC OSC)
3V
No load, ADC off,
fSYS=2MHz
¾
0.5
1
mA
¾
1.5
3
mA
Operating Current
(External RC OSC)
3V
No load, ADC off,
fSYS=4MHz
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
3
5
mA
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
¾
8
15
mA
¾
2
5
mA
¾
6
10
mA
¾
17
30
mA
¾
34
60
mA
IDD2
5V
5V
IDD3
Operating Current
(External RC OSC)
ISTB1
Standby Current
(WDT Disable)
3V
Standby Current
(WDT Enable)
3V
ISTB2
ISTB3
ISTB4
Rev. 1.00
5V
5V
No load, ADC on,
fSYS=4MHz,
ADCCLK=125kHz
No load, system HALT,
LCD off at HALT
5V
No load, system HALT,
LCD off at HALT, ADC off
Standby Current (WDT Disable 3V
Internal RC 12kHz OSC ON)
5V
No load, system HALT,
LCD off at HALT, ADC off
Standby Current (WDT Disable 3V
Internal RC 12kHz OSC ON)
5V
No load, system HALT,
LCD on at HALT, 1/2 bias,
VLCD=VDD
4
January 9, 2006
HT46R71D
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
No load, system HALT
LCD on at HALT, 1/3 bias,
VLCD=VDD
¾
13
25
mA
¾
28
50
mA
Conditions
VDD
ISTB5
Standby Current (WDT Disable 3V
Internal RC 12kHz OSC ON)
5V
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2
2.1
2.2
V
VLVD
Low Voltage Detector
¾
¾
2.2
2.3
2.4
V
IOL1
I/O Port Segment Logic Output
Sink Current
3V
4
8
¾
mA
10
20
¾
mA
I/O Port Segment Logic Output
Source Current
3V
-2
-4
¾
mA
-5
-10
¾
mA
LCD Common and Segment
Current
3V
210
420
¾
mA
350
700
¾
mA
LCD Common and Segment
Current
3V
-80
-160
¾
mA
-180
-360
¾
mA
Pull-high Resistance of I/O Ports
and INT
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Charge pump on
2.2
¾
3.6
V
Charge pump off
3.7
¾
5.5
V
IOH1
IOL2
IOH2
RPH
VOL=0.1VDD
5V
VOH=0.9VDD
5V
VOL=0.1VDD
5V
VOH=0.9VDD
5V
Charge Pump and Regulator
VCHPI
VREGO
Input Voltage
Output Voltage
VREGDP1
¾
¾
No load
3
3.3
3.6
V
¾
VDD=3.7V~5.5V
Charge pump off
Current£10mA
¾
¾
100
mV
¾
VDD=2.4V~3.6V
Charge pump on
Current£6mA
¾
¾
100
mV
Regulator Output Voltage Drop
(Compare with No Load)
VREGDP2
Dual Slope AD, Amplifier and Band Gap
VRFGO
Reference Generator Output
¾
@3.3V
1.45
1.5
1.55
V
VRFGTC
Reference Generator
Temperature Coefficient
¾
@3.3V
¾
50
¾
Ppm/C
VADOFF
Input Offset Range
¾
¾
500
800
mV
Rev. 1.00
¾
5
January 9, 2006
HT46R71D
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
System Clock
fINRC
Internal RC OSC
¾
2.2V~5.5V
3V
¾
5V
Timer I/P Frequency
(TMR0/TMR1)
fTIMER
tWDTOSC Watchdog Oscillator Period
¾
Min.
Typ.
Max.
Unit
400
¾
4000
kHz
¾
12
¾
kHz
¾
15
¾
kHz
0
¾
4000
kHz
Conditions
VDD
2.2V~5.5V
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up from
HALT
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note:
tSYS= 1/fSYS
Rev. 1.00
6
January 9, 2006
HT46R71D
Functional Description
The PC then points to the memory word containing the
next instruction code.
Execution Flow
The system clock is derived from an RC oscillator. It is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
The program counter (PC) is 11 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 2048 addresses.
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
1
1
0
0
ADC Interrupt
0
0
0
0
0
0
1
0
0
0
0
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.00
S10~S0: Stack register bits
@7~@0: PCL bits
7
January 9, 2006
HT46R71D
· Location 010H
Program Memory - EPROM
Location 010H is reserved for the ADC interrupt service program. If an ADC interrupt occurs, and if the interrupt is enabled and the stack is not full, the program
begins execution at this location.
The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 2048´14 bits which are addressed by the program
counter and table pointer.
· Table location
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH. The TBLH is read only, and the table pointer
(TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location
should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation.
These areas may function as a normal ROM depending upon the user¢s requirements.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 4 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
· Location 00CH
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
0 0 8 H
0 0 C H
E x te r n a l in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
0 1 0 H
P ro g ra m
M e m o ry
A D C in te r r u p t s u b r o u tin e
n 0 0 H
1 F F H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 4 return addresses are stored).
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
F F F H
1 4 b its
N o te : n ra n g e s fro m
1 to 6
Program Memory
Instruction(s)
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.00
P10~P8: Current program counter bits
8
January 9, 2006
HT46R71D
Data Memory - RAM
(TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1
control register (TMR1C;11H), I/O registers (PA;12H,
PB;14H) and I/O control registers (PAC;13H,
PBC;15H), an ADC control register (ADCR;18H), an
ADC chopper divider register (ADCD;1AH), an Interrupt
control register 1 (INTC1;1EH) and Charge Pump &
Regulator Control Register (CHPRC;1FH).
The data memory (RAM) is designed with 57´8 bits, and
is divided into two functional groups, namely; special
function registers 25´8 bit and general purpose data
memory, 32´8 bit most of which are readable/writable,
although some are read only. The special function register are overlapped in any banks.
The remaining space before the 20H is reserved for future expanded usage and reading these locations will
get ²00H². The general purpose data memory, addressed from 20H to 3FH , is used for data and control
information under instruction commands. All of the data
memory areas can handle arithmetic, logic, increment,
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through memory pointer registers (MP0;01H or MP1:03H).
Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1
0 0 H
After first setting up BP to the value of ²01H² to access
Bank 1 , these banks must then be accessed indirectly
using the Memory Pointer MP1. With BP set to a value
of ²01H², using MP1 to indirectly read or write to the
data memory areas with addresses from 20H~3FH will
result in operations to Bank 1. Directly addressing the
Data Memory will always result in Bank 0 being accessed irrespective of the value of BP.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
M O D E
0 A H
S T A T U S
0 B H
IN T C 0
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
memory pointer register (MP0, MP1) are 7-bit registers.
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
S p e c ia l P u r p o s e
D a ta M e m o ry
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
1 6 H
1 7 H
1 8 H
A D C R
1 9 H
R e s e rv e d
1 A H
A D C D
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
1 B H
1 C H
1 D H
1 E H
IN T C 1
1 F H
C H P R C
2 0 H
3 F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.00
9
January 9, 2006
HT46R71D
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
The device provides one external interrupts, two internal
timer/event counter interrupts and the ADC interrupt.
The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/
disable status and interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, other interrupts are all blocked, by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becoming full.
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Bit No.
External interrupts is triggered by an edge transition of
INT (Configuration option: high to low, low to high, both
low to high and high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0) is set as well. After the
interrupt is enabled, the stack is not full, and the external
interrupt is active, a subroutine call to location 04H occurs. The interrupt request flag (EIF0) and EMI bits are
all cleared to disable other maskable interrupts.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
10
January 9, 2006
HT46R71D
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
Interrupt Source
Vector
External interrupt 0
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
ADC interrupt
4
10H
The Timer/Event Counter 0 interrupt request flag (T0F),
external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter
0 interrupt bit (ET0I), enable external interrupt 1 bit
(EEI1), enable external interrupt 0 bit (EEI0) and enable
master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the
RAM. The ADC interrupt request flag (ADF).
Timer/Event Counter 1 interrupt request flag (T1F), enable ADC interrupt bit (ADI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the
Interrupt Control register 1 (INTC1) which is located at
1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I and EADI
are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags (ADF,
T0F, T1F, EIF1, EIF0) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.
The A/D Converter interrupt is initialized by setting the
A/D Converter clock interrupt request flag (ADF; bit 4 of
INTC1), that is caused by an A/D conversion done signal. After the interrupt is enabled, and the stack is not
full, and the ADF bit is set, a subroutine call to location
10H occurs. The related interrupt request flag (ADF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Bit No.
Priority
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI0
Controls the external interrupt 0 (1=enabled; 0=disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC 0 (0BH) Register
Bit No.
Label
0
EADI
1~3, 5~7
¾
4
ADF
Function
Controls the ADC interrupt (1=enabled; 0:disabled)
Unused bit, read as ²0²
ADC request flag (1=active; 0=inactive)
INTC 1 (1EH) Register
Rev. 1.00
11
January 9, 2006
HT46R71D
Oscillator Configuration
Watchdog Timer - WDT
The device provides two oscillator circuits, an external
RC oscillator and an internal RC 12kHz oscillator
(Int.RCOSC). The external RC oscillator signal is used
for the system clock while the Internal 12kHz RC oscillator is designated for timing purposes.
The WDT is implemented either using a dedicated internal RC oscillator (Int.RCOSC) or the instruction clock
(system clock/4). The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by a configuration option, however if the
WDT is disabled, all executions related to the WDT will
result in no operation.
In the IDLE mode, the system oscillator will stop running, but if bit IRCC = 1,to enable the IRC clock source,
the internal RC oscillator (Int.RCOSC) will continue to
free run. In the HALT mode, if the IRC clock source is
disabled, with bit IRCC=0, both the system oscillator
and the internal RC oscillator will stop running. However, if the WDT is enabled, the internal RC oscillator will
continuously free run. The system can be woken-up
from either the IDLE or HALT mode by the occurrence of
an interrupt, a high to low transition on any of the Port A
pins, a WDT overflow or a timer overflow and request
flag is set (0®1). If an external RC oscillator is used, an
external resistor between OSC1 and VSS is required to
achieve oscillation, the value of which must be between
100kW to 2.4MW. The system clock, divided by 4, is
available for external logic synchronization purposes on
pin OSC2.
Once the internal RC oscillator, which has a nominal period of 65ms, is selected, it is then divided by a value
which ranges from 212~215 the exact value of which is
determined by a configuration option, to obtain the actual WDT time-out period. The minimum period of the
WDT time-out period is about 300ms~600ms. This
time-out period may vary with temperature, VDD and
process variations. By using the related WDT configuration option, longer time-out periods can be realized. If
the WDT time-out is selected to be 215, the maximum
time-out period is divided by 215~216which will give a
time-out period of about 2.3s~4.7s.
The WDT clock source may also come from the instruction clock, in which case the WDT will operate in the
same manner except that in the HALT mode the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, using the on-chip RC oscillator (Int.RC OSC) is strongly
recommended, since the HALT instruction will stop the
system clock.
The Internal RC oscillator (Int.RCOSC) is a free running
on-chip RC oscillator, requiring no external components. Even if the system enters the Power Down Mode,
and the system clock is stopped, the internal RC oscillator continues to run with a period of approximately 65ms
at 5V if either the WDT or IRC clock is enabled. The internal RC oscillator can be disabled by a configuration
option and by clearing the IRCC bit to ²0² to conserve
power.
V
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT or
IDLE mode, the overflow initializes a ²warm reset², and
only the PC and SP are reset to zero. There are three
methods to clear the contents of the WDT, an external
reset (a low level on RES), a software instruction or a
²HALT² instruction. There are two types of software instructions; the single ²CLR WDT² instruction, or the pair
of instructions ¾ ²CLR WDT1² and ²CLR WDT2².
D D
4 7 0 p F
O S C 1
N M O S O p e n D r a in
Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option ¾ ²CLR WDT² times selection option.
If the ²CLR WDT² is selected (i.e., CLR WDT times
equal one), any execution of the ²CLR WDT² instruction
clears the WDT. If the ²CLR WDT1² and ²CLR WDT2²
option is chosen (i.e., CLR WDT times equal two), these
two instructions have to be executed to clear the WDT,
otherwise the WDT may reset the chip due to a time-out.
O S C 2
R C
O s c illa to r
System Oscillator
Rev. 1.00
12
January 9, 2006
HT46R71D
S y s te m
C lo c k /4
In t.R C O S C
R O M
C o d e
O p tio n
fW
D T
W D T P r e s c a le r
D iv id e r
C K
M a s k O p tio n
R
T
C K
R
W D T C le a r
T
T im
fW D
fW D
fW D
fW D
e -o u t R e s e t
/2 15~ fW D T /2 1
T /2 1 4 ~ fW D T /2 1
T /2 1 3 ~ fW D T /2 1
T /2 1 2 ~ fW D T /2 1
6
T
5
4
3
Watchdog Timer
Buzzer Output
essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must
also be set high to enable the buzzer outputs, if set low,
both pins PA0 and PA1 will remain low. In this way the
single bit PA0 of the PA register can be used as an
on/off control for both the BZ and BZ buzzer pin outputs.
Note that the PA1 data bit in the PA register has no control over the BZ buzzer pin PA1.
The Buzzer function provides a means of producing a
variable frequency output, suitable for applications such
as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ
pins form a complimentary pair, and are pin-shared with
I/O pins, PA0 and PA1. A configuration option is used to
select from one of three buzzer options. The first option
is for both pins PA0 and PA1 to be used as normal I/Os,
the second option is for both pins to be configured as BZ
and BZ buzzer pins, the third option selects only the PA0
pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is
the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers.
If configuration options have selected that only the PA0
pin is to function as a BZ buzzer pin, then the PA1 pin
can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output
by setting bit PAC0 of the PAC port control register to
zero. The PA0 data bit in the PA data register must also
be set high to enable the buzzer output, if set low pin
PA0 will remain low. In this way the PA0 bit can be used
as an on/off control for the BZ buzzer pin PA0. If the
PAC0 bit of the PAC port control register is set high, then
pin PA0 can still be used as an input even though the
configuration option has configured it as a BZ buzzer
output.
The buzzer is driven by the internal clock source, fS,
which then passes through a divider, the division ratio of
which is selected by configuration options to provide a
range of buzzer frequencies from fS/22 to fS/29. The
clock source that generates fS, which in turn controls the
buzzer frequency, can originate from two different
sources, the Int.RCOSC (Internal RC oscillator) or the
System oscillator/4, the choice of which is determined
by the fS clock source configuration option. Note that the
buzzer frequency is controlled by configuration options,
which select both the source clock for the internal clock
fS and the internal division ratio. There are no internal
registers associated with the buzzer frequency.
Note that no matter what configuration option is chosen
for the buzzer, if the port control register has setup the
pin to function as an input, then this will override the configuration option selection and force the pin to always
behave as an input pin. This arrangement enables the
pin to be used as both a buzzer pin and as an input pin,
so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by
the application program by programming the appropriate port control register bit.
If the configuration options have selected both pins PA0
and PA1 to function as a BZ and BZ complementary pair
of buzzer outputs, then for correct buzzer operation it is
PAC Register
PAC.0
PAC Register
PAC.1
PA data Register
PA.0
PA data Register
PA.1
0
0
0
X
PA0=0, PA1=0
0
0
1
X
PA0=BZ, PA1=BZ
0
1
0
X
PA0=0, PA1=Input
0
1
1
X
PA0=BZ, PA1=Input
1
0
0
X
PA0=Input, PA1=0
1
1
X
X
PA0=Input, PA1=Input
Output Function
PA0/PA1 Pin Function Control
Note:
²X² stands for don¢t care
Rev. 1.00
13
January 9, 2006
HT46R71D
In te r n a l C lo c k S o u r c e
P A 0 D a ta
B Z O u tp u t a t P A 0
P A 1 D a ta
B Z O u tp u t a t P A 1
Buzzer Output Pin Control
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place.
Note:The above drawing shows the situation where
both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup
as outputs. The data setup on pin PA1 has no effect on
the buzzer outputs.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
· The system oscillator turns off but the Internal oscilla-
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awakened using
that interrupt.
tor (Int.RCOSC) keeps running (if the Internal oscillator is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
If a wake-up events occur, it takes 1024 tSYS (system
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
· The WDT is cleared and start recounting (if the WDT
clock source is from the Internal RC oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
· LCD driver keeps running (if the IRC clock is enabled;
IRCC=1).
The system quits the HALT or IDLE mode by means of
an external reset, an interrupt, an external falling edge
signal on port A, or a WDT overflow. An external reset
causes device initialisation, and the WDT overflow performs a ²warm reset². After examining the TO and PDF
flags, the reason for chip reset can be determined. The
PDF flag is cleared by system power-up or by executing
the ²CLR WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO flag is set if
WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, and leaves the others
at their original state.
Rev. 1.00
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
14
January 9, 2006
HT46R71D
Reset
V
D D
0 .0 1 m F *
There are three ways in which a reset may occur.
· RES is reset during normal operation
1 0 0 k W
· RES is reset during HALT
R E S
· WDT time-out is reset during normal operation
1 0 k W
The WDT time-out during HALT or IDLE differs from
other chip reset conditions, for it can perform a ²warm
reset² that resets only the program counter and SP and
leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition²
once the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
0 .1 m F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
V D D
0
1
RES Wake-up HALT
R E S
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
tS
C h ip
R e s e t
Note: ²u² stands for unchanged
Reset Timing Chart
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power-up.
Awaking from the HALT state or system power-up, the
SST delay is added.
H A L T
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT
Cleared. After master reset,
WDT starts counting
Timer/Event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
R e s e t
E x te rn a l
R E S
The functional unit chip reset status is shown below.
000H
W a rm
W D T
An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the
SST delay.
Program Counter
S T
S S T T im e - o u t
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
Rev. 1.00
15
January 9, 2006
HT46R71D
The register states are summarized below:
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
MODE
--0- 00--
--0- 00--
--0- 00--
--0- 00--
--u- uu--
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
Program
Counter
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- --11
---- --11
---- --11
---- --11
---- --uu
PBC
---- --11
---- --11
---- --11
---- --11
---- --uu
ADCR
00-- x000
00-- x000
00-- x000
00-- x000
00-- x000
ADCD
---- -111
---- -111
---- -111
---- -111
---- -uuu
INTC1
CHPRC
Note:
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
0000 0-00
0000 0-00
0000 0-00
0000 0-00
uuuu u-uu
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.00
16
January 9, 2006
HT46R71D
buffer, respectively. Reading TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the
Timer/Event Counter 1 control register, which defines
the operating mode, counting enable or disable and an
active edge.
Timer/Event Counter
Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains a 8-bit programmable count-up counter and
the clock may come from an external source or an internal clock source. An internal clock source comes from
fSYS or Internal RC. The Timer/Event Counter 1 contains
a 16-bit programmable count-up counter and the clock
may come from an external source or an internal clock
source. An internal clock source comes from fSYS/4 or
Internal RC selected by special function register option.
The external clock input allows the user to count external events, measure time intervals or pulse widths, or to
generate an accurate time base.
The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)
bits define the operation mode. The event count mode is
used to count external events, which means that the
clock source must come from an external (TMR0,
TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count a high or low level duration
of an external signal on TMR0 or TMR1, with the timing
based on the internal selected clock source.
There are two registers related to the Timer/Event
Counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing
to TMR0 puts the starting value in the Timer/Event
Counter 0 register and reading TMR0 reads out the contents of Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which defines some
options. There are three registers related to the
Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H)
and TMR1C (11H). Writing to TMR1L will only put the
written data into an internal lower-order byte buffer
(8-bit) while writing to TMR1H will transfer the specified
data and the contents of the lower-order byte buffer to
both the TMR1H and TMR1L registers, respectively.
In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the
Timer/Event Counter 0 (1) and ends at FFH (FFFFH).
Once an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and generates
an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit6
of INTC0). In the pulse width measurement mode with
the values of the T0ON/T1ON and T0E/T1E bits equal
to 1, after the TMR0 (TMR1) has received a transient
from low to high (or high to low if the TE bit is ²0²), it will
start counting until the TMR0 (TMR1) pin returns to the
original level and resets the T0ON/T1ON bit. The measured result remains in the timer/event counter even if
the activated transient occurs again. In other words,
only a 1-cycle measurement can be made until the
T0ON/T1ON is set. The cycle measurement will
The Timer/Event Counter 1 preload register is changed
every time there is a write operation to TRM1H. Reading
TMR1H will latch the contents of TMR1H and TMR1L
counters to the destination and the lower-order byte
fS
Y S
In t. R C O S C
M
U
fT
0
8 - s ta g e P r e s c a le r
X
T 0 S
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
f IN
D a ta B u s
T 0
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r
(T M R 0 )
O v e r flo w
to In te rru p t
Timer/Event Counter 0
fS
In t. R C
Y S
/4
O S C
T 1 S
M
U
X
fT
D a ta B u s
1
8 - s ta g e P r e s c a le r
8 -1 M U X
T 1 P S C 2 ~ T 1 P S C 0
f IN
L o w B y te
B u ffe r
T 1
T 1 M 1
T 1 M 0
T M R 1
1 6 - B it
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
B y te
1 6 - B it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.00
17
January 9, 2006
HT46R71D
Bit No.
Label
Function
T0PSC0
T0PSC1
T0PSC2
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT0=fT0
001: fINT0=fT0/2
010: fINT0=fT0/4
011: fINT0=fT0/8
100: fINT0=fT0/16
101: fINT0=fT0/32
110: fINT0=fT0/64
111: fINT0=fT0/128
3
T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T0ON
5
T0S
0
1
2
6
7
T0M0
T0M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR0 internal clock source (0=fSYS; 1=Int.RCOSC (Internal RC OSC))
Defines the operating mode T0M1, T0M0=
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR0C (0EH) Register
Bit No.
Label
Function
T1PSC0
T1PSC1
T1PSC2
To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0=
000: fINT1=fT1
001: fINT1=fT1/2
010: fINT1=fT1/4
011: fINT1=fT1/8
100: fINT1=fT1/16
101: fINT1=fT1/32
110: fINT1=fT1/64
111: fINT1=fT1/128
3
T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T1ON
5
T1S
0
1
2
6
7
T1M0
T1M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR1 internal clock source (0=fSYS/4; 1=Int.RCOSC (Internal RC OSC))
Defines the operating mode T1M1, T1M0=
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR1C (11H) Register
Rev. 1.00
18
January 9, 2006
HT46R71D
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an
input, the corresponding latch of the control register
must write ²1². The input source also depends on the
control register. If the control register bit is ²1², the input
will read the pad state. If the control register bit is ²0²,
the contents of the latches will move to the internal bus.
The latter is possible in the ²read-modify-write² instruction.
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and
issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(T0ON; bit 4 of TMR0C or T1ON bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON (T1ON) is automatically cleared after the measurement cycle is completed. But in the other two
modes, the T0ON (T1ON) can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
and 15H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H or 14H)
instructions.
In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register also
reloads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, however this
may results in a counting error, something that should
be taken into account by the programmer. It is strongly
recommended to load a desired value into the
TMR0/TMR1 register first, before turning on the related
timer/event counter, for proper operation since the initial
value of TMR0/TMR1 is unknown. Due to the timer/
event counter scheme, the programmer should pay special attention to the instructions which enables then disables the timer for the first time, whenever there is a
need to use the timer/event counter function, to avoid
unpredictable results. After this procedure, the
timer/event function can be operated normally.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high I/O
port operating in input mode will cause a floating state.
The PA0, PA1, PA4, PA5 and PA6 are pin-shared with
BZ, BZ, TMR0, TMR1 and INT pins respectively.
PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output
signals in the output mode of PA0/PA1 will be the buzzer
signal generated by multi-function timer. The input
mode always remains in its original function. Once the
BZ/BZ option is selected, the buzzer output signals are
controlled by the PA0, PA1 data register only.
The bit0~bit2 of the TMR1C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 1.
The I/O function of PA0/PA1 are shown below.
PA0 I/O
Input/Output Ports
There are 10 bidirectional input/output lines in the
microcontroller, labeled as PA and PB, which are
mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H or 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
I
O O O O O O O O
PA1 I/O
I
O
I
PA0 Mode
X X C B B C B B B B
PA1 Mode
X C X X X C C C B B
PA0 Data
X X D 0
PA1 Data
X D X X X D1 D D X X
PA0 Pad Status
I
I
D 0
B D0 0
0
B
PA1 Pad Status
I
D
I
I D1 D D 0
B
Note:
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS outputs or Schmitt trigger inputs with or
Rev. 1.00
I
19
I
I
I
O O O O O
1 D0 0
1
B
0
1
²I² input; ²O² output
²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care
January 9, 2006
HT46R71D
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
W r ite D a ta R e g is te r
Q
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P U
Q
D
D D
D a ta B it
Q
D
Q
C K
/B Z
/B Z
/T M R 0
/T M R 1
/IN T
~ P B 1
S
M
P A 0 /P A 1
B Z /B Z
M
R e a d D a ta R e g is te r
S y s te m
U
U
X
E N
X
W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
T M R 0 fo r P A 4 o n ly
T M R 1 fo r P A 5 o n ly
IN T fo r P A 6 o n ly
Input/Output Ports
²C² CMOS output
ulator generates the required 3.3V voltage output. The
block diagram of this module is shown below.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instructions to avoid consuming power when in an input state.
C H P C 2
C H P C 1
V O R E G
V O C H P
Charge Pump and Voltage Regulator
There is one charge pump and one voltage regulator implement in this device.
V D D
The charge pump can be enabled/disabled by the application program. The charge pump uses VDD as its input, and has the function of doubling the VDD voltage.
The output voltage of the charge pump will be VDD´2.
The regulator can generate a stable voltage of 3.3V, for
ADC and also can provide an external bridge sensor excitation voltage or supply a reference voltage for other
applications. The user needs to guarantee the charge
pump output voltage is over 3.6V to ensure that the reg-
Bit No.
Label
0
REGCEN
1
CHPEN
2
¾
3~7
C h a rg e P u m p
( V o lta g e D o u b le r )
fS
D iv id e r
C H P C K D
C H P E N
V D D
V D D x 2
R e g u la to r
(3 .3 V )
3 .3 V
A D C
R E G C E N
There is a single register associated with this module
named CHPRC. The CHPRC is the Charge Pump/Regulator Control register, which controls the charge pump
on/off, regulator on/off functions as well as setting the
clock divider value to generate the clock for the charge
pump.
Function
Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable)
Charge Pump Enable/disable setting. (1=enable; 0=disable)
Note: this bit will be ignore if the REGCEN is disable
Reserved
The Charge pump clock divider. This 5 bits can form the clock divide by 1~31.
CHPCKD0~
Following the below equation:
CHPCKD4
Charge Pump clock = (fSYS/16) / (CHPCKD+1)
CHPRC (1FH) Register
Rev. 1.00
20
January 9, 2006
HT46R71D
REGCEN CHPEN
Charge
Pump
VOCHP
Regulator
Pin
VOREG Pin OPA ADC
Description
The whole module is disable,
OPA/ADC will lose the Power
0
X
OFF
VDD
OFF
Hi-Impedance
Disable
1
0
OFF
VDD
ON
3.3V
Active
Use for VDD is greater than 3.6V
(VDD>3.6V)
1
1
ON
2´VDD
ON
3.3V
Active
Use for VDD is less than 3.6V
(VDD=2.2V~3.6V)
Users need to take care of the VDD voltage, if the voltage
is under 3.6V, then CHPEN should be set to 1 to enable
the charge pump, otherwise CHPEN should be set to
zero. If the Charge pump is disabled and VDD is under
3.6V then the output voltage of the regulator will not be
guaranteed.
The CHPCKD4~0 bits are use to set the clock divider to
generate the desired clock frequency to provide the
charge pump working. The actual frequency is decide
by the following formula.
T h e A c t u a l C har g e P um p C l o c k = ( f S Y S / 1 6 ) /
(CHPCKD+1).
ADC - Dual Slope
The suggestion clock frequency of the charge pump is
20kHz. Application need to set the correct value to get
the desired clock frequency. e.g. for the 4MHz application, the CHPCKD should be set to 12, and for 2MHz application, the correct CHPCKD is 6.
A Dual Slope A/D converter is implemented in this
microcontroller. The dual slope module includes an Operational Amplifier and a buffer for the amplification of
differential signals, an Integrator and a comparator for
the main dual slope AD converter.
The REGCEN bit in the CHPRC is the Regulator/
Charge-pump module enable/disable control bit. If this
bit is disabled, then the regulator will be disabled and the
charge pump will be also be disabled to save power.
When REGCEN = 0, the module will enter a Power
Down Mode ignoring the CHPEN setting. The ADC and
OPA will also be disabled to reduce power.
In addition, there is also an integrated band gap voltage
generator for the 1.5V low temperature sensitive reference voltage. This reference voltage is used as the zero
adjustment and for a single end type reference voltage.
There are 2 special function registers related to this
block including: ADCR and ADCD. The ADCR register
is the A/D control register, which controls the ADC block
power on/off, the chopper clock on/off, the charge/discharge control and is also used to read out the comparator output status. The ADCD is the A/D Chopper clock
divider register, which define the chopper clock to the
ADC module.
If REGCEN is set to logic ²1², the regulator will be enabled. If CHPEN is enabled, the charge pump will be active and will use VDD as its input to generate the double
voltage output. This double voltage will be used as the
input of the regulator. If CHPEN is set to logic ²0², the
charge pump is disabled and the charge pump output
will be equal to the charge pump input (VDD).
V D S O
P W R
C o n tro l
V O R E G
R v f1
V
D O P A P
D O P A N
R v f2
M
V
+
+
-
U
-
A m p lifie r
A D P W R E N
IN T
X
+
B u ffe r
-
C M P
+
In te g ra to r
R
A D D IS C H 0
A D D IS C H 1
O n C h ip
O ff C h ip
A D C M P O
C o m p a ra to r
D O P A O
D C H O P
D S R R
D S R C
D S C C
Note: VINT, VCMP signal can come from different R groups which are selected by software registers.
Rev. 1.00
21
January 9, 2006
HT46R71D
R 4
2 7 n F
1 0 0 k W
D O P A O
D C H O P
R 3
B u ffe r
D O P A N
V B
C h o p p e r
A m p lifie r
R 1
V A
B r id g e
S e n s o r
D O P A P
V D O P A O = V Z + (V A -V B )x (R 2 /R 1 )
if R 1 = R 3 a n d R 2 = R 4
R 2
V Z
O ff C h ip
O n C h ip
A D C M P O
formula 1: VA= (1/3)´VDSO´(2-Tc/Ti).
(Base on ADRR0=0)
D S C C
D S R C
V
A
R
D S
C
th e
In general applications, the application program will
switch the ADC to charging mode for a fixed time called
Ti (integrating time), and then switch to the dis-charging
mode, wait for the VC drop under the 1/6VDSO (the
comparator will change state), keep the time Tc (
de-integrating time). And then follow the formula 1 to get
the input voltage VA.
D S R R
.
e o n ly
, V B
The ²comparator² will switch the state from high to low
when the VC (the DSCC pin voltage ) drop under the 1/6
VDSO.
In te g r a to r
V
re a re fo r re fe re n c
v o lta g e fo r th e V A
s h o w s th e d e ta ils )
B G P p in is o n e o f
V O B G P p r o v id e a
The ²Integrator² integrates the output voltage increments or decrements controlled by the ²Switch Circuit²
(refer to the block diagram). The integrated and de-integrated curves are illustrated by the following.
C o m p a ra to r
+
v a lu e s h e
re fe re n c e
e fo r m u la
to th e V O
lic a tio n s (
1 .5 V ).
The ²Integrator² integrates the output voltage increase
or decrease controlled by ²Switch Circuit² (refer to the
block diagram). The integrated and de-integrated
curves are illustrated in the following:
The following descriptions are base on the ADRR0=0
4 /6 V D S O
ll " R " a n d " C "
h e r e V Z is a
iffe r e n tia ls ( th
o n n e c tin g V Z
u g g e s tin g a p p
o lta g e a r o u n d
The combinations of the Integrator, the Comparator and
the resistor between DSRR and ADRC(Rds) and the capacity between DSRC and DSCC (Cds) form the main
body of the Dual slope ADC.
The ADPWREN bit defined in ADCR register is used to
control the on/off function of the ADC module. The
ADCCKEN bit defined in the ADCR register is used to
control the chopper clock on/off. When ADCCKEN is set
to logic ²1² it will enable the Chopper clock, with the
clock frequency defined by the ADCD registers. The
ADC module includes the OPA, buffer, integrator and
Comparator, however the Band gap voltage generator is
independent of this module. It will be automatically enabled when the regulator is enabled, and also be disabled when the regulator is disabled. The application
program should enable the related power to permit them
to function and disable them when idle to conserve
p o w e r. Th e c har g e / d i s c har g e c ont r o l b i t s
(ADDISCH1~0) are used to control the Dual slope circuit charging and discharging behavior. The ADCMPO
bit is read only for the comparator output, and the
ADCMPO changing falling edge will trigger a dual slope
ADC interrupt.
1 /6 V D S O
N o te : A
W
d
C
s
v
Application hints: Application users need to choose the
correctly RDS, CDS and the Ti let the VC work between
6/5VDSO and 1/6VDSO. (e.g. Vfull can’t be over the
5/6VDSO and Vzero can¢t be under 1/6VDSO)
C
D S
The combination of the amplifier and buffer forms a differential input pre-amplifier which amplifies signals from
the sensor. The amplification is controlled by the ratio of
R1~R4 as shown in the block diagram:
Rev. 1.00
22
January 9, 2006
HT46R71D
V
C
V fu ll
V
V z e ro
1 /6 V D S O
T i
T c (z e ro )
T c
T c ( fu ll)
In te g r a te tim e
D e - In te g r a te tim e
Bit No.
Label
Function
0
ADPWREN
Dual slope block (including input OP) power on/off switching.
0: disable Power
1: Power source comes from the regulator.
1
2
ADDISCH0
ADDISCH1
Defines the ADC discharge/charge. (ADDISCH1:0)
00: reserved
01: charging. (Integrator input connect to buffer output)
10: discharging. (Integrator input connect to VDSO)
11: reserved
3
ADCMPO
4~5
¾
6
ADCCKEN
7
ADRR0
Dual Slope ADC - last stage comparator output.
Read only bit, write data instructions will be ignored.
During the discharging state, when the integrator output is less than the reference voltage,
the ADCMPO will change from high to low.
Reserved
ADC OP chopper clock source on/off switching.
0: disable
1: enable (clock value is defined by ADCD register)
ADC resisters selection
0: (VINT, VCMP)= (4/6 VOREG, 1/6 VOREG)
1: (VINT, VCMP)= (4.4/6 VOREG, 1/6 VOREG)
ADCR (18H) Register
Bit No.
Label
Function
0
1
2
ADCD0
ADCD1
ADCD2
Define the chopper clock (ADCCKEN should be enable), the suggestion clock is around
10kHz.
The chopper clock define :
0: clock= (fSYS/32)/1
1: clock= (fSYS/32)/2
2: clock= (fSYS/32)/4
3: clock= (fSYS/32)/8
4: clock= (fSYS/32)/16
5: clock= (fSYS/32)/32
6: clock= (fSYS/32)/64
7: clock= (fSYS/32)/128
3~7
¾
Reserved
ADCD (1AH) Register
Rev. 1.00
23
January 9, 2006
HT46R71D
LCD frequencies from Int.RCOSC/3 to Int.RCOSC/4.
Note that the LCD frequency is controlled by configuration options, which select the internal division ratio.
There are no internal registers associated with the
buzzer frequency.
LCD Display Memory
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 49H of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as ²1², any data
written into 40H~49H will effect the LCD display. When
the BP is cleared to ²0² or ²1², any data written into
40H~49H means to access the general purpose data
memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1.
When data is written into the display data area, it is automatically read by the LCD driver which then generates
the corresponding LCD driving signals. To turn the display on or off, a ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The figure
illustrates the mapping between the display memory
and LCD pattern for the device.
4 0 H
C O M
4 1 H
4 2 H
4 3 H
4 7 H
4 8 H
4 9 H
0
B it
0
1
1
2
2
0
S E G M E N T
1
2
3
7
8
9
Display Memory
LCD Driver Output
The output number of the device LCD driver can be
10´3 by configuration option (i.e., 1/ 2 duty or 1/3 duty).
The bias type LCD driver is R type only. The LCD driver
bias voltage can be 1/ 2 bias or 1/3 bias by option.
The LCD clock is driven by the IRC clock, which then
passes through a divider, the division ratio of which is
selected by configuration options to provide a range of
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
C O M 0 , C O M 1 , C O M 2
A ll lc d d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
V L C D
S
C D
V L C D
S
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
C D
S
C D
S
V L C D
V L C D
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Duty, R Type)
Rev. 1.00
24
January 9, 2006
HT46R71D
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the MODE.3 to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from MODE.5; otherwise, the LVD function is
disabled.
The MODE register definitions are listed below.
Bit No.
Label
0~1
¾
Function
Unused bit, read as ²0²
2
IRCC
3
LVDC
4
¾
5
LVDO
6~7
¾
In HALT mode, IRC clock enable or disable selection bit.
0: IRC clock enable and Int.RCOSC on. 1: IRC clock disabled.
LVD enable/disable (1/0)
Unused bit, read as ²0²
LVD detection output (1/0)
1: low voltage detected, read only. 0: low voltage not detected.
Unused bit, read as ²0²
MODE (09H) Register
The relationship between VDD and VLVR is shown below.
The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT
state, LVR is disabled both LVR and LVD are disabled.
V D D
5 .5 V
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
V
O P R
5 .5 V
V
L V R
2 .1 V
2 .2 V
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.00
25
January 9, 2006
HT46R71D
Options
The following shows the options in the device. All these options should be defined in order to ensure proper functioning
system.
Options
fS clock source.
There are two types of selections: Int.RCOSC or fSYS/4
WDT clock source selection.
There are two types of selections: system clock/4 or Int.RCOSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS,
215/fS~216/fS,
CLR WDT times selection.
This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the
WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be
cleared.
Buzzer output frequency selection.
There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS² means the clock source selected by options.
Wake-up selection.
This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip
from a HALT by a falling edge (bit option).
Pull-high selection.
This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA and PB
can be independently selected (bit option).
I/O pins share with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
LCD common selection.
There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty).
LCD bias selection.
This option is to determine what kind of bias is selected, 1/2 bias or 1/3 bias.
LCD driver clock frequency selection.
There are two types of frequency signals for the LCD driver circuits: Int.RCOSC/3~Int.RCOSC/4.
LCD ON/OFF at HALT selection
LVR selection.
LVR has enable or disable options
LVD selection.
LVD has enable or disable options
INT trigger edge selection: disable; high to low; low to high; low to high or high to low
Partial-lock selection: Page0~3, Page4~6, Page7.
Rev. 1.00
26
January 9, 2006
HT46R71D
Application Circuits
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
C O M 0 ~ C O M 2
S E G 0 ~ S E G 9
L C D
P A N E L
R E S
0 .1 m F
1 0 k W
0 .1 m F *
V L C D
V S S
O S C 1
O S C
C ir c u it
L C D
P o w e r S u p p ly
P A 0 /B Z
O S C 2
S e e r ig h t s id e
P A 1 /B Z
V O B G P
V R E G
P A 2
D O P A P
S e n s o r
P A 3
D O P A N
D O P A O
D C H O P
P A 4 /T M R 0
P A 5 /T M R 1
D S R R
P A 6 /IN T
D S R C
P A 7
D S C C
V S S
V R E G
V O R E G
4 7 m F
1 0 m F
V O B G P
1 0 m F
1 0 m F
P B 0 ~ P B 1
V O C H P
V
V O B G P
R C S y s te m
1 0 0 k W < R O
4 7 0 p F
C H P C 1
R
C H P C 2
H T 4 6 R 7 1 D
Note:
D D
O S C
S C
O s c illa to r
< 2 .4 M W
O S C 1
fS
Y S
/4
O S C 2
O S C
C ir c u it
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that VDD is stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.00
27
January 9, 2006
HT46R71D
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
28
January 9, 2006
HT46R71D
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter Power Down Mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
29
January 9, 2006
HT46R71D
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
30
January 9, 2006
HT46R71D
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
January 9, 2006
HT46R71D
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
January 9, 2006
HT46R71D
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
33
January 9, 2006
HT46R71D
HALT
Enter Power Down Mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
January 9, 2006
HT46R71D
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
35
January 9, 2006
HT46R71D
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
January 9, 2006
HT46R71D
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
37
January 9, 2006
HT46R71D
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
January 9, 2006
HT46R71D
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
January 9, 2006
HT46R71D
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
January 9, 2006
HT46R71D
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
January 9, 2006
HT46R71D
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
42
January 9, 2006
HT46R71D
Package Information
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
Symbol
Rev. 1.00
a
F
E
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
43
January 9, 2006
HT46R71D
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.00
44
January 9, 2006
HT46R71D
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32±0.3
P
Cavity Pitch
16±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
12±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.00
0.35±0.05
25.5
45
January 9, 2006
HT46R71D
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
46
January 9, 2006