HOLTEK HT45R38

HT45R38
C/R to F Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· 12 capacitor/resistor sensor input
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 4096´15 program memory
· 192´8 data memory RAM
· 29 bidirectional I/O lines
· Power Down and Wake-up function reduce power
· Two external interrupt inputs shared with I/O lines
consumption
· Single 8-bit programmable timer/event counter with
· Up to 0.5ms instruction cycle with 8MHz system clock
overflow interrupt and 7-stage prescaler
at VDD=5V
· One 8-bit programmable timer/event counter with
· All instructions executed in one or two machine cy-
overflow interrupt
cles
· 5 channels 12-bit resolution A/D converter
· 15-bit table read instruction
· 2-channels 8-bit PWM output shared with 2 I/O lines
· Six-level subroutine nesting
· One OPA
· Bit manipulation instruction
· External RC oscillation converter
· 63 powerful instructions
· On-chip crystal and RC oscillator
· Low voltage reset function
· Watchdog Timer
· 52-pin QFP package
General Description
The HT45R38 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for
cost-effective multiple I/O control product applications.
wake-up functions, Watchdog Timer, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer
products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power Down and
Rev. 1.00
1
December 13, 2006
HT45R38
Block Diagram
P A 3 /IN T 0
P A 4 /IN T 1
S T A C K 0
P ro g ra m
R O M
In te rru p t
C ir c u it
S T A C K 1
P ro g ra m
C o u n te r
T M R 0 C
IN T C
M
T M R 0
U
S y s te m
P r e s c a le r
C lo c k
P A 5 /T M R 0
X
T M R 1 C
In s tr u c tio n
R e g is te r
M
M P
U
X
D a ta
M e m o ry
M
T M R 1
U
S y s te m
W D T S
M U X
In s tr u c tio n
D e c o d e r
A L U
P A C
P O R T A
P A
S h ifte r
T im in g
G e n e ra to r
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P W M
S ta tu s
P B C
P O R T B
O S
R E
V D
V D
V S
V S
S
C 1
S y s te m
/P W
/P W
/IN
/IN
/T
/T
C lo c k /4
X
R C O S C
M 0
M 1
T 0
T 1
M R 0
M R 1
A C C
P C C
D
P O R T C
P C 0 ~ P C 7
P C
D B
S
U
P B 0 ~ P B 7
P B
O S C 2
M
W D T
W D T P r e s c a le r
C lo c k /4
P A 6 /T M R 1
X
S C
5 -C h a n n e l
A /D C o n v e rte r
P E C
P O R T E
P E 0 /A N 0 /O P O
P E 1 /A N 1 ~ P E 4 /A N 4
P E
T im e r A
T im e r B
A n a lo g
S w itc h
R C
O s c illa tio n
M
U
S y s te m
S y s te m
X
C lo c k
C lo c k /4
R C O s c illa tio n O u tp u t
R C 1 ~ R C 1 2
R C O U T
IN
R R E F
C R E F
P E 0 /A N 0 /O P O
O P N
O P P
Rev. 1.00
2
December 13, 2006
HT45R38
Pin Assignment
P E 0 /A N 0 /O
O
O
V
V
O S
O S
R
P A 0 /P W
P A 1 /P W
P
P A 3 /IN
P A 4 /IN
P O
P N
P P
S S
D D
C 2
C 1
E S
M 0
M 1
A 2
T 0
T 1
P A 5 /T M R
P A 6 /T M R
P A
P B
P B
P B
P B
V D D
P B
P B
P B
P B
P C
3
B
0
7
6
5
2
1
0
7
1
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
0
4
1
3 9
2
3 8
3
3 7
3 6
4
5
3 5
6
H T 4 5 R 3 8
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
P E
P E
P E
P E
R C
R C
R C
R C
R C
R C
R C
R C
R C
1 /A
2 /A
3 /A
4 /A
1 2
1 1
1 0
9
8
7
6
5
4
N 1
N 2
N 3
N 4
R C 3
R C 2
R C 1
R C O
IN
R R E
C R E
P C 5
P C 4
V S S
P C 3
P C 2
P C 1
C
F
F
U T
Pin Description
Pin Name
I/O
Options
Description
PA0/PWM0
PA1/PWM1
PA2
PA3/INT0
PA4/INT1
PA5/TMR0
PA6/TMR1
PA7
I/O
Pull-high
Wake-up
Interrupt Enable
Interrupt Active
Edge Type
PWM
Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input
by configuration code options. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Pull-high resistors can be connected
to each pin via configuration options.
Pins PA3 and PA4 are pin-shared with external interrupt input pins INT0
and INT1, respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger type. Pins PA5 and PA6 are
pin-shared with the external timer input pins TMR0 and TMR1. The
PWM0/PWM1 output functions are pin-shared with PA0/PA1, respectively.
PB0~PB7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be
added to the whole port via a configuration option.
PC0~PC7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be
added to the whole port via a configuration option.
I
¾
OPN
OPP
PE0/AN0/OPO
PE1/AN1
I/O
PE2/AN2
PE3/AN3
PE4/AN4
Pull-high
OPN is the OPA inverting input pin
OPP is the OPA non-inverting input pin
Bidirectional 5-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. Pull-high resistors can be
connected to each pin via configuration options.
PE0~PE4 are pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O
function and pull-high resistor are disabled automatically.
The OPO is the OPA output pin and pin-shared with PE0/AN0.
RC1~RC12
I
¾
Capacitor or resistor connection pins
RCOUT
I
¾
Capacitor or resistor connection pin to RC OSC
IN
I
¾
Oscillation input pin
RREF
O
¾
Reference resistor connection pin
CREF
O
¾
Reference capacitor connection pin
RES
I
¾
Schmitt trigger reset input. Active low
Rev. 1.00
3
December 13, 2006
HT45R38
Pin Name
I/O
Options
VSS
¾
¾
Negative power supply, ground
VSSC
¾
¾
Negative power supply for PC, ground
VDD
¾
¾
Positive power supply
VDDB
¾
¾
Positive power supply PB
OSC1
OSC2
I
O
Crystal or RC
Description
OSC1, OSC2 are connected to an RC network or Crystal determined by a
configuration option, for the internal system clock. In the case of the RC oscillator, OSC2 can be used to monitor the system clock. Its frequency is 1/4
system clock.
Note: *All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................300mA
IOH Total............................................................-200mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Ta=25°C
Test Conditions
Operating Voltage
¾
Operating Current
(Crystal OSC, RC OSC)
3V
IDD2
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current (WDT Enabled)
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
1
2
mA
¾
3
5
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
Conditions
VDD
No load, fSYS=4MHz
5V
5V
No load, fSYS=8MHz
3V
No load, system HALT
5V
ISTB2
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
LVR enabled
2.7
3.0
3.3
V
IOL1
PA, PB, PE, RREF and CREF
Sink Current
3V
4
8
¾
mA
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
IOH1
Rev. 1.00
PA, PC, PE, RREF and CREF
Source Current
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
4
December 13, 2006
HT45R38
Symbol
IOL2
Parameter
Test Conditions
VDD
3V
PC Sink Current
Conditions
VOL=0.1VDD
5V
IOH2
3V
PB Source Current
VOH=0.9VDD
5V
RPH
Min.
Typ.
Max.
Unit
8
16
¾
mA
20
40
¾
mA
-4
-8
¾
mA
-10
-20
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
VAD
A/D Input Voltage
¾
ADC input reference
voltage is VDD
0
¾
VDD
V
DNL
ADC Differential Non-Linear
¾
¾
¾
¾
±2
LSB
INL
ADC Integral Non-Linear
¾
¾
¾
±2.5
±4
LSB
¾
¾
¾
¾
12
Bits
Additional Power Consumption if A/D 3V
Converter is Used
5V
¾
¾
0.5
1
mA
¾
¾
1.5
3
mA
RESOLU Resolution
IADC
A.C. Characteristics
Symbol
fSYS
fTIMER
Parameter
System Clock
(Crystal OSC, RC OSC)
Timer I/P Frequency
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
ms
3V
¾
45
90
180
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
3V
tWDT1
Watchdog Time-out Period
(WDT RC OSC)
5V
tWDT2
Watchdog Time-out Period
(System Clock/4)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
¾
1024
¾
tSYS
Without WDT prescaler
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Reset Time
¾
¾
0.25
1
2
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Rev. 1.00
Wake-up from HALT
5
December 13, 2006
HT45R38
OP Amplifier Electrical Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
3
¾
5.5
V
-2
¾
+2
mV
D.C. Electrical Characteristic
VDD
Operating Voltage
¾
VOS
Input Offset Voltage
5V
VCM
Common Mode Voltage Range
¾
¾
VSS
¾
VDD-1.4
V
PSRR
Power Supply Rejection Ratio
¾
¾
60
¾
¾
dB
CMRR
Common Mode Rejection Ratio
¾
60
¾
¾
dB
60
80
¾
dB
By calibration
VDD=5V
VCM=0~VDD-1.4V
D.C. Electrical Characteristic
AOL
Open Loop Gain
¾
SR
Slew Rate+, Rate-
¾
No load
¾
1
¾
V/ms
GBW
Gain Band Width
¾
RL=1MW, CL=100pF
¾
¾
100
kHz
Rev. 1.00
¾
6
December 13, 2006
HT45R38
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, a conditional skip
execution, loading the PCL register, a subroutine call,
an initial reset, an internal interrupt, an external interrupt
or return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to
each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the program will proceed with the next instruction.
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are executed and its contents specify full range of program
memory.
The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the
PCL performs a short jump. The destination must be
within the current Program Memory Page.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
External RC Oscillation Converter Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
1
0
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note: *11~*0: Program Counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.00
@7~@0: PCL bits
7
December 13, 2006
HT45R38
· Location 00CH
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
This location is reserved for the Timer/Event Counter
0 interrupt service program. If a Timer 0 interrupt results from a Timer/Event Counter 0 overflow, and the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 010H
Certain locations in the program memory are reserved
for special usage:
This location is reserved for the external RC oscillation converter interrupt service program. If an external
RC oscillation converter interrupt results from an external RC oscillation converter interrupt is activated,
and the interrupt is enabled and the stack is not full,
the program begins execution at this location.
· Location 000H
This area is reserved for program initialisation. After a
device reset, the program always begins execution at
location 000H.
· Location 004H
· Location 014H
This location is reserved for the external interrupt 0
service program. If the INT0 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a Timer 1 interrupt results from a Timer/Event Counter 1 overflow, and the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 008H
This location is reserved for the external interrupt 1
service program. If the INT1 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te rn a l In te rru p t 0
0 0 8 H
E x te rn a l In te rru p t 1
0 0 C H
T im e r /E v e n t C o u n te r 0 O v e r flo w
· Location 018H
This location is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Table location
Any location in the program memory can be used as a
look-up table. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH (08H). Only the destination of the lower-order
byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH,
and the remaining 1 bit is read as ²0². The table
higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR. Errors may
0 1 0 H E x te r n a l R C O s c illa tio n C o n v e r te r In te r r u p t
0 1 4 H
P ro g ra m
M e m o ry
T im e r /E v e n t C o u n te r 1 O v e r flo w
0 1 8 H
A /D
C o n v e rte r In te rru p t
n 0 0 H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F 0 0 H
F F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 5 - B its
N o te : n ra n g e s fro m 0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.00
8
December 13, 2006
HT45R38
therefore occur. In other words, using the table read
instruction in the main routine and also in the ISR
should be avoided. However, if the table read instruction has to be used in both the main routine and in the
ISR, the interrupt should be disabled prior to the table
read instruction execution. The interrupt should not be
re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
0 0 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
Stack Register - STACK
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
This is a special part of the memory which is used to save
the contents of the program counter only. The stack is
organised into 6-levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return instruction, RET or RETI, the program counter
is restored to its previous value from the stack. After a device reset, the SP will point to the top of the stack.
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 6 return addresses are stored.
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P E
1 9 H
P E C
1 A H
P W M 0
1 B H
P W M 1
1 C H
A S C R
S p e c ia l P u r p o s e
D a ta M e m o ry
1 D H
1 E H
IN T C 1
1 F H
2 0 H
Data Memory - RAM
The data memory has a capacity of 230´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(192´8). Most are read/write, but some are read only.
T M R A H
2 1 H
T M R A L
2 2 H
R C O C C R
2 3 H
T M R B H
2 4 H
T M R B L
2 5 H
R C O C R
2 6 H
O P A C
2 7 H
The special function registers include the Indirect addressing registers (00H, 02H), Timer/Event Counter 0
(TMR;0DH), Timer/Event Counter 0 control register
(TMR0C;0EH), Timer/Event Counter 1 (TMR1;10H),
Timer/Event Counter 1 control register (TMR1C;11H),
Program counter lower-order byte register (PCL;06H),
Memory pointer registers (MP0;01H, MP1;03H), Accumulator (ACC;05H), Table pointer (TBLP;07H), Table
higher-order byte register (TBLH;08H), Watchdog Timer
option setting register (WDTS;09H), Status register
(STATUS;0AH), Interrupt control register 0 (INTC0;
0BH), Interrupt control register 1 (INTC1;1EH), Analog
switch control register (ASCR;1CH), PWM data register
(PWM0;1AH, PWM1;1BH), the Timer/Event Counter A
higher-order byte register (TMRAH;20H), the
Timer/Event Counter A lower-order byte register
Rev. 1.00
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
2 8 H
A D R L
2 9 H
A D R H
2 A H
A D C R
2 B H
2 C H
A C S R
3 F H
4 0 H
F F H
G e n e ra l P u rp o s e D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d ,
re a d a s "0 0 "
RAM Mapping
(TMRAL;21H), the RC oscillation converter control register (RCOCCR;22H), the Timer/Event Counter B
higher-order byte register (TMRBH;23H), the
Timer/Event Counter B lower-order byte register
(TMRBL;24H), and the RC oscillator control register
(RCOCR;25H), the A/D result lower-order byte register
(ADRL;28H), the A/D result higher-order byte register
(ADRH;29H), the A/D control register (ADCR;2AH), the
9
December 13, 2006
HT45R38
registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Program Memory by combining corresponding
indirect addressing registers.
A/D clock setting register (ACSR;2BH), the Operation
Amplifier control register (OPAC;26H), I/O registers
(PA;12H, PB;14H, PC;16H, PE;18H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PEC;19H).
The general purpose data memory, addressed from 40H
to FFH, is used for data and control information under instruction commands.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location ²05H² of the data memory
and can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the ²SET [m].i²
and ²CLR [m].i² bit manipulation instructions. They are
also indirectly accessible through the memory pointer
registers (MP0;01H, MP1;02H).
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
Indirect Addressing Register
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipulated in the same way as normal registers providing a
convenient way with which to address and track data.
When any operation to the relevant indirect addressing
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction.
Direct data transfer between two indirect addressing
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
10
December 13, 2006
HT45R38
generated when the timer overflows. After the interrupt
is enabled, and the stack is not full, and the T0F bit is
set, a subroutine call to location ²0CH² will occur. The
related interrupt request flag, T0F, is reset, and the EMI
bit is cleared to disable other interrupts.
The PDF flag can be affected only by executing a
²HALT² or ²CLR WDT² instruction or a system
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F; bit 5 of INTC1), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T1F bit is set, a
subroutine call to location ²14H² occurs. The related interrupt request flag (T1F) is reset, and the EMI bit is
cleared to disable other interrupts.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Interrupt
The external RC Oscillation Converter interrupt is initialized by setting the external RC Oscillation Converter interrupt request flag, RCOCF; bit 4 of INTC1. This is
caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the RCOCF
bit is set, a subroutine call to location ²10H² will occur.
The related interrupt request flag, RCOCF , will be reset
and the EMI bit cleared to disable further interrupts.
The devices provides two external interrupts, two internal 8-bit timer/event counter interrupt, one external RC
oscillation converter interrupt and the A/D converter interrupt. The interrupt control register 0 (INTC0;0BH) and
interrupt control register 1 (INTC1;1EH) both contain the
interrupt control bits that are used to set the enable/disable and interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This
scheme may prevent further interrupt nesting. Other interrupt requests may happen during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 and
INTC1 registers may be set to allow interrupt nesting. If
the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
The A/D converter interrupt is initialised by setting the
A/D converter request flag (ADF; bit 6 of the INTC1),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 18H will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a
subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the accumulator or status register are
altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents should be saved in advance.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
External interrupts are triggered by an edge transition
on pins INT0 or INT1. A configuration option enables
these pins as interrupts and selects if they are active on
high to low or low to high transitions. If active their related interrupt request flag, EIF0; bit 4 in INTC0, and
EIF1; bit 5 in INTC0, will be set. After the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location ²04H² or ²08H² will
occur. The interrupt request flags, EIF0 or EIF1, and the
EMI bit will all be cleared to disable other interrupts.
Interrupt Source
The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag,T0F; bit 6 in INTC0. A timer interrupt will be
Rev. 1.00
Priority
Vector
External Interrupt 0
1
04H
External Interrupt 1
2
08H
Timer/Event Counter 0 Overflow
3
0CH
External RC Oscillation Converter
Interrupt
4
10H
Timer/Event Counter 1 Overflow
5
14H
A/D Converter Interrupt
6
18H
Interrupt Priority
11
December 13, 2006
HT45R38
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI0
Controls the external interrupt 0 (1= enabled; 0= disabled)
2
EEI1
Controls the external interrupt 1 (1= enabled; 0= disabled)
3
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
4
EIF0
External interrupt 0 request flag (1= active; 0= inactive)
5
EIF1
External interrupt 1 request flag (1= active; 0= inactive)
6
T0F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
0
Label
Function
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)
1
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
2
EADI
Control the A/D converter interrupt (1= enabled; 0= disabled)
3, 7
4
¾
Unused bit, read as ²0²
RCOCF External RC oscillation converter request flag (1= active; 0= inactive)
5
T1F
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
6
ADF
A/D converter request flag (1= active; 0= inactive)
INTC1 (1EH) Register
Oscillator Configuration
The Timer/Event Counter 0 interrupt request flag, T0F,
external interrupt 1 request flag, EIF1, external interrupt
0 request flag, EIF0, enable Timer/Event Counter 0 interrupt bit, ET0I, enable external interrupt 1 bit, EEI1,
enable external interrupt 0 bit, EEI0, and enable master
interrupt bit, EMI, form the interrupt control register 0,
INTC0, which is located at ²0BH² in the RAM.
There are two oscillator circuits in the microcontroller.
V
O S C 1
The Timer/Event Counter 1 interrupt request flag (T1F),
external RC Oscillation Converter interrupt request flag
(RCOCF), A/D converter request flag (ADF), enable
Timer/Event Counter 1 interrupt bit (ET1I), enable external RC Oscillation Converter interrupt bit (ERCOCI) and
enable A/D converter interrupt bit (EADI), form the interrupt control register 1 (INTC1) which is located at ²1EH²
in the RAM.
O S C 1
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, the choice of which is
determined by a configuration option. When the device
enters the Power Down Mode, the system oscillator will
stop running and will ignore external signals to conserve
power.
EMI, EEI0, EEI1, ET0I, ET1I, ERCOCI and EADI, are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags, EIF0, EIF1,
T0F, T1F, RCOCF and ADF, are all set, they remain in
the INTC1 or INTC0 registers respectively until the interrupts are serviced or cleared by a software instruction.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required to produce oscillation. The
resistance must range from 24kW to 1MW. The system
clock, divided by 4, is available on OSC2, which can be
used to synchronize external logic. The RC oscillator
provides the most cost effective solution, however, the
frequency of oscillation may vary with VDD, temperatures and the device itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence may be damaged
once the ²CALL² is executed in the interrupt subroutine.
Rev. 1.00
D D
12
December 13, 2006
HT45R38
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are required,
if the oscillator frequency is less than 1MHz.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
The WDT oscillator is a free running on-chip RC oscillator which requires no external components. Even if the
system enters the Power Down Mode, where the system clock is stopped, the WDT oscillator will continue to
operate with a period of approximately 65ms at 5V. The
WDT oscillator can be disabled by a configuration option
to conserve power.
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
The WDT overflow under normal operation will generate
a ²chip reset² and set the status bit ²TO². But in the
Power Down mode, the overflow will generate a ²warm
reset², where only the Program Counter and SP are reset to zero. To clear the contents of the WDT, including
the WDT prescaler, three methods can be used; an external reset (a low level to RES), a software instruction
and a ²HALT² instruction. The software instruction includes ²CLR WDT² instruction and the instruction pair ²CLR WDT1² and ²CLR WDT2². Of these two types of
instruction, only one can be active depending on the
configuration option - ²CLR WDT times selection op tion². If the ²CLR WDT² is selected, i.e. CLRWDT times
equal one, any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen, i.e. CLRWDT times equal
two, these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of a time-out.
Watchdog Timer - WDT
The WDT clock can be sourced from its own dedicated
internal oscillator (WDT oscillator), or from the or instruction clock, which is the system clock divided by 4.
The choice is determined via a configuration option. The
WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by a configuration option. If the Watchdog
Timer is disabled, any executions related to the WDT result in no operation.
The WDT clock source is first divided by 256. If the internal WDT oscillator is used ,this gives a nominal time-out
period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By using the WDT prescaler, longer time-out
periods can be realised. Writing data to the WS2, WS1,
WS0 bits in the WDTS register, can give different
time-out periods. If WS2, WS1, and WS0 are all equal to
1, the division ratio will be 1:128, and the maximum
time-out period will be 2.1s at 5V. If the internal WDT oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the Power Down state the WDT will stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS can be used for user
defined flags.
Power Down Operation - HALT
The Power Down mode is initialized by the ²HALT² instruction and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
· The contents of the on chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
· All of the I/O ports will maintain their original status.
If the device operates in a noisy environment, using the
internal WDT oscillator is the recommended choice,
since the HALT instruction will stop the system clock.
S y s te m
The system can leave the Power Down Mode by means
of an external reset, an interrupt, an external falling
W D T P r e s c a le r
C lo c k /4
W D T
O S C
· The PDF flag is set and the TO flag is cleared.
O p tio n
S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.00
13
December 13, 2006
HT45R38
that it can perform a ²warm reset² that resets only the
Program Counter and the SP, leaving the other circuits
in their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to
their ²initial condition² when the reset conditions are
met. By examining the PDF and TO flags, the program
can distinguish between the different device reset types.
edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the other registers
maintain their their original status.
TO PDF
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configuration options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If
the wake-up results in the next instruction execution,
this will be executed immediately after the dummy period is finished.
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilised, the SST or System Start-up Timer, provides
an extra-delay of 1024 system clock pulses when the
system is reset (power-up, WDT time-out or RES reset)
or when the system awakens from a Power Down state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit device reset status are shown below.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
Mode.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Reset
Input/Output Ports
Input mode
There are three ways in which a reset can occur:
Stack Pointer
Points to the top of the stack
· RES reset during normal operation
· RES reset during HALT
V D D
· WDT time-out reset during normal operation
R E S
A WDT time-out, when the device is in the Power Down
mode, is different from other device reset conditions, in
V
tS
S T
S S T T im e - o u t
C h ip
R e s e t
D D
Reset Timing Chart
0 .0 1 m F *
H A L T
1 0 0 k W
W a rm
R E S
1 0 k W
R E S
C o ld
R e s e t
0 .1 m F *
O S C 1
Reset Circuit
Note: ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
Rev. 1.00
R e s e t
W D T
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
14
December 13, 2006
HT45R38
The states of the registers is summarized in the table.
Reset
(Power-on)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
Register
Program
Counter
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PEC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ASCR
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
OPAC
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Note: ²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
15
December 13, 2006
HT45R38
In the event count or timer mode, the timer/event counter 0/1 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag, which is the T0F; bit 6 of INTC0, or the T1F;
bit 5 of INTC1.
Timer/Event Counter 0/1
Two timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 is an 8-bit programmable count-up counter whose clock may come
from an external source or from an internal clock source.
This internal clock source is the system clock.
Timer/Event Counter 1 is also an 8-bit programmable
count-up counter whose clock may come from an external source or from an internal clock source. This internal
clock source is the system clock/4. Using an external
clock input allows the user to count external events,
measure time intervals or pulse widths. Using the internal clock allows an accurate time base to be generated.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to ²1², after the
TMR0 or TMR1 pin has received a low to high transient,
or high to low if the T0E/T1E bit is ²0², it will start counting until the TMR0 or TMR1 pin returns to its original
level at which point it will reset the T0ON/T1ON bit.
There are two registers related to Timer/Event Counter
0; TMR0 (0DH), TMR0C (0EH), and two registers related to Timer/Event Counter 1; TMR1(10H), TMR1C
(11H). Writing to either Timer/Event Counter places a
start value in the Timer/Event Counter 0/1 preload register while reading the Timer/Event Counter retrieves the
contents of the Timer/Event Counter 0/1. The TMR0C
and TMR1C registers are the Timer/Event Counter control register 0/1, which define the operating mode, the
count enable or disable and the active edge type.
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only a single shot measurement can be made.
Not until the T0ON/T1ON bit is set again, by the program, can another measurement be made. In this operation mode, the timer/event counter begins counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes,
i.e., event counter and timer modes.
The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source will come
from the external timer pin, TMR0 or TMR1. The timer
mode functions as a normal timer with the clock source
coming from the internal system clock. The pulse width
measurement mode can be used to measure the duration of a high or low level external signal on pin TMR0 or
TMR1. The counting will be based on the internally selected clock source.
fS
Y S
To enable the counting operation, the Timer ON bit,
T0ON; bit 4 of the TMR0C register or T1ON; bit 4 of the
TMR1C register, should be set to 1. In the pulse width
measurement mode, the T0ON/T1ON bit is automatically cleared after the measurement cycle is completed.
But in the other two modes, the T0ON/T1ON bit can only
be reset by instructions. The overflow of the
Timer/Event Counter 0/1 is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I or ET1I disables the related interrupt servicing.
7 - S ta g e P r e s c a le r
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
D a ta B u s
T
T 0 M 1
T 0 M 0
T M R 0
8 - B it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
8 - B it T im e r /E v e n t
C o u n te r (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 0
fS Y S /4
T 1 M 1
T 1 M 0
T M R 1
D a ta B u s
8 - b it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.00
16
December 13, 2006
HT45R38
When the timer/event counter is read, the clock is
blocked to avoid errors, and as this may results in a
counting error, it should be taken into account by the
programmer.
If the timer/event counter is not running, writing data to
the timer/event counter preload register also reloads
that data into the timer/event counter. But if the
timer/event counter is already running, data written to
the timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter will
continue running until an overflow occurs and only then
will the data be loaded into the timer/event counter.
Bit No.
0~2
Bit0~bit2 of the TMR0C register can be used to define
the timer/event counter clock division ratio. The definitions are as shown.
Label
Function
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
T0PSC0~T0PSC2 011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T0E
To define the TMR0 active edge of the timer/event counter
In event counter mode (T0M1, T0M0)= (0, 1)
0: count on rising edge;
1: count on falling edge
In pulse width measurement mode (T0M1, T0M0)= (1, 1)
0: start counting on the falling edge, stop on the rising edge;
1: start counting on the rising edge, stop on the falling edge
4
T0ON
To enable or disable timer counting (0=disabled; 1=enabled)
5
¾
6
7
T0M0
T0M1
Unused bit, read as ²0²
To define the operating mode, T0M1, T0M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
Label
0~2, 5
¾
Function
Unused bit, read as ²0²
To define the TMR0 active edge of the timer/event counter
In event counter mode (T1M1, T1M0)= (0, 1)
0: count on rising edge;
1: count on falling edge
In pulse width measurement mode (T1M1, T1M0)= (1, 1)
0: start counting on the falling edge, stop on the rising edge;
1: start counting on the rising edge, stop on the falling edge
3
T1E
4
T1ON
To enable or disable timer counting (0=disabled; 1=enabled)
T1M0
T1M1
To define the operating mode, T0M1, T0M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
TMR1C (11H) Register
Rev. 1.00
17
December 13, 2006
HT45R38
There are six registers related to the RC oscillation converter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH,
TMRBL and RCOCR. The internal timer clock is the input to TMRAH and TMRAL, the external RC oscillation
is the input to TMRBH and TMRBL. The OVB bit, bit 0 of
RCOCR register, decides whether Timer A overflows or
Timer B overflows, then the RCOCF bit is set and an external RC oscillation converter interrupt occurs. When
the RC oscillation converter mode Timer A or Timer B
overflows, the RCOCON bit is reset to ²0² and stops
counting. Writing to TMRAH/TMRBH places the start
value in Timer A/Timer B while reading TMRAH/TMRBH
obtains the contents of Timer A/Timer B. Writing to
TMRAL/TMRBL only writes the data into a low byte
buffer. However writing to TMRAH/TMRBH will write the
External RC Oscillation Converter
An external RC oscillation mode is implemented in the
device. The RC oscillation converter contains two 16-bit
programmable count-up counters and the Timer A clock
source may come from the system clock or system
clock/4. The timer B clock source may come from the
external RC oscillator.
The RC oscillation converter is comprised of the
TMRAL, TMRAH, TMRBL, TMRBH registers when the
RCO bit, bit 1 of RCOCR register, is ²1². The RC oscillation converter Timer B clock source may come from an
external RC oscillator. The Timer A clock source comes
from the system clock or from the system clock/4, determined by the RCOCCR register.
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
3
¾
Undefined bit, this bit can read/write
4
5
6
7
Function
RCOCON To enable or disable external RC oscillation converter counting (0= disabled; 1= enabled)
To define the Timer A clock source, RCOM2, RCOM1, RCOM0=
000= System clock
001= System clock/4
RCOM0 010= Unused
RCOM1 011= Unused
RCOM2 100= Unused
101= Unused
110= Unused
111= Unused
RCOCCR (22H) Register
Bit No.
Label
Function
0
OVB
In the RC oscillation converter mode, this bit is used to define the timer/event counter interrupt,
which comes from Timer A overflow or Timer B overflow.
(0= Timer A overflow; 1= Timer B overflow)
1
RCO
Define 16 timer/event counter mode or RC oscillation converter mode.
(0= Disable RC oscillation converter mode; 1= Enable RC oscillation converter mode)
2~3
¾
4~7
RW
Unused bit, read as ²0²
4-bit read/write registers for user defined.
RCOCR (25H) Register
S y s te m
S y s te m
C lo c k
C lo c k /4
S 1
O V B = 0
S 2
T im e r A
E x te rn a l R C
O s c illa tio n C o n v e r te r In te r r u p t
R C O C O N
O V B = 1
T im e r B
R C
O S C
R e s e t R C O C O N
O u tp u t
External RC Oscillation Converter
Rev. 1.00
18
December 13, 2006
HT45R38
data and the contents of the low byte buffer into the
Timer A/Timer B (16-bit) simultaneously. Timer A/Timer
B is changed by writing to TMRAH/TMRBH but writing to
TMRAL/TMRBL will keep the Timer A/Timer B unchanged.
The resistor and capacitor form an oscillation circuit and
input to TMRBH and TMRBL. The RCOM0, RCOM1
and RCOM2 bits of RCOCCR define the clock source of
Timer A. It is recommended that the clock source of
Timer A uses the system clock or the instruction clock.
R e a d in g TM R A H / TM R B H w i l l al s o l at ch t h e
TMRAL/TMRBL into the low byte buffer to avoid the
false timing problem. Reading TMRAL/TMRBL returns
the contents of the low byte buffer. In other word, the low
byte of Timer A/Timer B can not be read directly. It must
read the TMRAH/TMRBH first to ensure that the low
byte contents of Timer A/Timer B are latched into the
buffer.
If the RCOCON bit, bit 4 of RCOCCR, is set to ²1², Timer
A and Timer B will start counting until Timer A or Timer B
overflows, the timer/event counter will then generate an
interrupt request flag which is RCOCF; bit 4 of INTC1.
The Timer A and Timer B will stop counting and will reset
the RCOCON bit to ²0² at the same time. If the
RCOCON bit is ²1², TMRAH, TMRAL, TMRBH and
TMRBL cannot be read or written.
External RC oscillation converter mode example program - Timer A overflow:
clr RCOCCR
mov a, 00000010b
; Enable External RC oscillation mode and set Timer A overflow
mov RCOCR,a
clr intc1.4
; Clear External RC Oscillation Converter interrupt request flag
mov a, low (65536-1000)
; Give timer A initial value
mov tmral, a
; Timer A count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrah, a
mov a, 00h
; Give timer B initial value
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
; Timer A clock source=fSYS/4 and timer on
mov RCOCCR, a
p10:
clr wdt
snz intc1.4
; Polling External RC Oscillation Converter interrupt request flag
jmp p10
clr intc1.4
; Clear External RC Oscillation Converter interrupt request flag
; Program continue
Rev. 1.00
19
December 13, 2006
HT45R38
Analog Switch
There are 12 analog switch lines in the microcontroller for RC1~RC12, and a corresponding Analog Switch control register, which is mapped to the data memory of ²1CH².
Bit No.
Label
0~4
ASON
5~7
¾
Function
Defines the analog switch for RC1~RC12 which is on. ASON=
00000b= Analog switch 1 on, other analog switch off
00001b= Analog switch 2 on, other analog switch off
00010b= Analog switch 3 on, other analog switch off
00011b= Analog switch 4 on, other analog switch off
00100b= Analog switch 5 on, other analog switch off
00101b= Analog switch 6 on, other analog switch off
00110b= Analog switch 7 on, other analog switch off
00111b= Analog switch 8 on, other analog switch off
01000b= Analog switch 9 on, other analog switch off
01001b= Analog switch 10 on, other analog switch off
01010b= Analog switch 11 on, other analog switch off
01011b= Analog switch 12 on, other analog switch off
01100b= All analog switch off
01101b= All analog switch off
01110b= All analog switch off
01111b= All analog switch off
1xxxxb= All analog switch off and RC OSC always off
Unused bit, read as ²0²
ASCR (1CH) Register
A S O N
R C 1
T .G .1
R C 2
T .G .2
R C 3
T .G .3
R C 4
T .G .4
R C 5
T .G .5
R C 6
T .G .6
R C 7
T .G .7
R C 8
T .G .8
R C 9
T .G .9
R C 1 0
T .G .1 0
R C 1 1
T .G .1 1
R C 1 2
T .G .1 2
R C O U T
IN
R R E F
C R E F
T im e r B
Analog Switch
Rev. 1.00
20
December 13, 2006
HT45R38
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 29 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PE, which
are mapped to the data memory at [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each line of port A has the capability of waking-up the
device. The highest bits, 5,6 and 7, of port E are not
physically implemented; on reading them a ²0² is returned whereas writing to them results in no operation.
Each I/O line has a pull-high configuration option. It
should be noted that an input line without a connected
pull-high resistor will be in a floating state.
Each I/O line has its own control register, known as
PAC, PBC, PCC and PEC, to control the input/output
configuration. With this control register, a CMOS output
or schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically, i.e.
on-the-fly, under software control. To function as an input, the corresponding latch of the control register must
written with a ²1². The input source also depends on the
control register. If the control register bit is ²1², the input
will read the pad state. If the control register bit is ²0²,
the contents of the latches will move to the internal bus.
The latter is possible in the ²read-modify-write² instruction.
PA0, PA1, PA3, PA4, PA5 and PA6 are pin-shared with
PWM0, PWM1, INT0, INT1, TMR0 and TMR1 pins, respectively.
The PE port can also be used as A/D converter inputs.
The A/D function will be described later.
The PWM outputs are shared with pins PA0/PA1. If the
PWM function is enabled, the PWM0/PWM1 signals will
appear on PA0/PA1. Note that PA0/PA1 must be setup
as outputs for the PWM output to function. The I/O functions of PA0/PA1 are as shown.
For an output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H. After a chip reset, the port control
registers will default to a high state, which is an input
condition. They may be floating or be pulled high if
pull-high resistors are connected. Each bit of these input/output latches can be set or cleared by ²SET [m].i²
and ²CLR [m].i² (m=12H, 14H, 16H or 18H) instructions.
I/O Mode
PA0
PA1
I/P
O/P
(Normal) (Normal)
Logical
Input
W r ite C o n tr o l R e g is te r
C o n tr o l B it
P u ll- h ig h
Q
D
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
P A 0 /P A 1
P W M 0 /P W M 1
M
R e a d D a ta R e g is te r
S y s te m
U
T 0
T 0
R 0
R 1
fo
fo
fo
fo
r P
r P
r P
r P
A 3
A 4
A 5
A 6
O n
O n
O n
O n
PWM0
PWM1
E N
U
/P W M 0
/P W M 1
/IN
/IN
/T
/T
T 0
T 1
M R 0
M R 1
~ P B 7
~ P C 7
/A N 0 ~ P E 4 /A N 4
X
(P W M x )
X
W a k e - u p ( P A o n ly )
IN
IN
T M
T M
Logical
Input
D D
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
P C 0
P E 0
Q
C K
O/P
(PWM)
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
D a ta B u s
Logical
Output
I/P
(PWM)
O P 0 ~ O P 7
ly
ly
ly
ly
Input/Output Ports
Rev. 1.00
21
December 13, 2006
HT45R38
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
Pulse Width Modulator
Each device contains a dual channel internal PWM
function. Useful for such applications such as motor
speed control, the PWM function provides outputs with
a fixed frequency but with a duty cycle that can be varied
by placing particular values into the corresponding
PWM register.
A single register, located in the Data Memory is assigned to each of the two PWM outputs. These registers
assume the names PWM0 and PWM1. It is here that the
8-bit value, which represents the overall duty cycle of
one modulation cycle of the output waveform, should be
placed. To increase the PWM modulation frequency,
each modulation cycle is modulated into two or four individual modulation sub-sections, known as the 7+1
mode or 6+2 mode respectively. Each device can
choose which mode to use by selecting the appropriate
configuration option. When a mode configuration option
is chosen, it applies to both of the PWM outputs on the
device. Note that when using the PWM it is only necessary to write the required value into the appropriate
PWM register and select the required mode configuration option, the subdivision of the waveform into its
sub-modulation cycles is done automatically within the
microcontroller hardware.
PWM Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
Output Pin
PWM Register
Name
6+2 or 7+1
PA0
PWM0
6+2 or 7+1
PA1
PWM1
[PWM]/256
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
6+2 PWM Mode, each PWM cycle is subdivided into
four individual sub-cycles known as modulation cycle
0 ~ modulation cycle 3, denoted as ²i² in the table.
Each one of these four sub-cycles contains 64 clock
cycles. In this mode, a modulation frequency increase
by a factor of four is achieved. The 8-bit PWM register
value, which represents the overall duty cycle of the
PWM waveform, is divided into two groups. The first
group which consists of bit2~bit7 is denoted here as
the DC value. The second group which consists of
bit0~bit1 is known as the AC value. In the 6+2 PWM
mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table.
Parameter
PWM Function Table
This method of dividing the original modulation cycle
into a further 2 or 4 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
Rev. 1.00
fSYS/256
· 6+2 PWM Mode
The PWM clock source is the system clock fSYS.
PWM Mode
PWM Cycle PWM Cycle
Frequency
Duty
AC (0~3)
DC
(Duty Cycle)
i<AC
DC 1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
6+2 Mode Modulation Cycle Values
22
December 13, 2006
HT45R38
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to
note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC
value is related to the PWM value.
fS
Y S
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
6+2 PWM Mode
b 7
b 0
P W M
A C
R e g is te r
(6 + 2 ) M o d e
v a lu e
D C v a lu e
PWM Register for 6+2 Mode
· 7+1 PWM Mode
the DC value. The second group which consists of bit0
is known as the AC value. In the 7+1 PWM mode, the
duty cycle value of each of the two modulation
sub-cycles is shown in the following table.
Each full PWM cycle, as it is controlled by an 8-bit
PWM register has 256 clock periods. However, in the
7+1 PWM mode, each PWM cycle is subdivided into
two individual sub-cycles, known as modulation cycle
0 and modulation cycle 1, denoted as ²i² in the table.
Each one of these two sub-cycles contains 128 clock
cycles. In this mode, a modulation frequency increase
by a factor of two is achieved. The 8-bit PWM register
value, which represents the overall duty cycle of the
PWM waveform, is divided into two groups. The first
group which consists of bit1~bit7 is denoted here as
Rev. 1.00
Parameter
AC (0~1)
DC
(Duty Cycle)
Modulation cycle
i
(i=0~1)
i<AC
DC 1
128
i³AC
DC
128
7+1 Mode Modulation Cycle Values
23
December 13, 2006
HT45R38
The following diagram illustrates the waveforms associated with the 7+1 mode of PWM operation. It is important to
note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the AC
value is related to the PWM value.
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
7+1 PWM Mode
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(7 + 1 ) M o d e
PWM Register for 7+1 Mode
· PWM Output Control
the PWM data to appear on the pin. Writing a ²0² to
the corresponding bit in the PA output data register will
disable the PWM output function and force the output
low. In this way, the Port A data output register can be
used as an on/off control for the PWM function. Note
that if the configuration options have selected the
PWM function, but a ²1² has been written to its corresponding bit in the PAC control register to configure
the pin as an input, then the pin can still function as a
normal input line, with pull-high resistor configuration
options.
The PWM outputs are pin-shared with the Port A I/O
pins. To operate as PWM outputs and not as I/O pins,
the correct PWM configuration options must be selected. A ²0² must also be written to the corresponding
bits in the I/O port control register PAC to ensure that
the required PWM output pins are setup as outputs.
After these two initial steps have been carried out, and
of course after the required PWM value has been written into the PWM register, writing a ²1² to the corresponding bit in the PA output data register will enable
clr PAC.0
; set pin PA0 as output
clr PAC.1
; set pin PA1 as output
set pa.0
; PA.0=1; enable pin ²PA0/PWM0² to be the PWM channel 0
mov a,64h
; PWM0=100D=64H
mov pwm0,a
set pa.1
; PA.1=1; enable pin ²PA1/PWM1² to be the PWM channel 1
mov a,65h
; PWM1=101D=65H
mov pwm1,a
clr pa.0
; disable PWM0 output - PA.0 will remain low
clr pa.1
; disable PWM1 output - PA.1 will remain low
Rev. 1.00
24
December 13, 2006
HT45R38
lected as an analog input, the I/O functions and pull-high
resistor of this I/O line are disabled and the A/D converter circuit is powered on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when the A/D conversion is completed.
A/D Converter
The 5 channels 12-bit resolution A/D converter are implemented in this microcontroller.
The A/D converter contains 4 special registers which
are; ADRL (28H), ADRH (29H), ADCR (2AH) and ACSR
(2BH). The ADRH and ADRL are A/D result register
higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PE configuration, select the converted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising
edge and falling edge means that the A/D conversion
has started. In order to ensure that the A/D conversion is
completed, the START should remain at ²0² until the
EOCB is cleared to ²0² (end of A/D conversion). Bit1
and bit0 of the ACSR register are used to select the A/D
clock source.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D converter each time the Port E A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port E channel selection bits being modified. Note that if the Port E channel
selection bits are all cleared to zero then an A/D initialisation is not required.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the are used to select an
analog input channel. There are a total of five channels
to select. The bit5~bit3 of the ADCR are used to set PE
configurations. PE can be an analog input or as digital
I/O line determined by these 3 bits. Once a PE line is seBit No.
Label
0
1
ADCS0
ADCS1
2~7
¾
Function
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
Unused bit, read as ²0²
ACSR (2BH) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select
3
4
5
PCR0
PCR1
PCR2
Defines the port E configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0= end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialised by issuing a START signal,
otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialisation².
7
START
Starts the A/D conversion.
0®1®0= Start
0®1= Reset A/D converter and set EOCB to ²1².
ADCR (2AH) Register
Rev. 1.00
25
December 13, 2006
HT45R38
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
*
1
1
0
*
1
1
1
*
Analog Input Channel Selection
Note: * undefined, cannot be used
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL (20H)
D3
D2
D1
D0
0
0
0
0
ADRH (21H)
D11
D10
D9
D8
D7
D6
D5
D4
Note: D0~D11 is A/D conversion result data bit LSB~MSB.
PCR2
PCR1
PCR0
4
3
2
1
0
0
0
0
PE4
PE3
PE2
PE1
PE0
0
0
1
PE4
PE3
PE2
PE1
AN0
0
1
0
PE4
PE3
PE2
AN1
AN0
0
1
1
PE4
PE3
AN2
AN1
AN0
1
0
0
PE4
AN3
AN2
AN1
AN0
1
0
1
AN4
AN3
AN2
AN1
AN0
1
1
0
1
1
1
Undefined, cannot be used
Port E Configuration
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P E p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P E c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 8 0 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.00
26
December 13, 2006
HT45R38
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
mov
mov
mov
mov
EADI
a,00000001B
ACSR,a
a,00100000B
ADCR,a
:
:
:
Start_conversion:
clr
START
set
START
clr
START
Polling_EOC:
sz
EOCB
jmp
polling_EOC
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
:
:
jmp
Start_conversion
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PE0~PE3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port E channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
; start next A/D conversion
Example: using Interrupt Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PE0~PE3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port E channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
Rev. 1.00
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
27
December 13, 2006
HT45R38
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
; restore STATUS from user defined memory
; restore ACC from user defined memory
OP Amplifier
The device contains an internal Operational Amplifier, which can be used for amplification purposes. The OPA can be
disabled or enabled under software control and by the OPA configuration option.
OPA
Configuration
Option
OPAEN
Register
PCR2~PCR0
Register
0
Function
000B
PE0/AN0/OPO is digital input pin, OPA is disabled.
001B
010B
011B
100B
101B
PE0/AN0/OPO is ADC channel 0 input pin, OPA is disabled.
000B
PE0/AN0/OPO is OPA output pin, OPA is enabled.
001B
010B
011B
100B
101B
PE0/AN0/OPO is OPA output pin and OPA output signal is input to
ADC channel 0, OPA is enabled.
000B
PE0/AN0/OPO is digital input/output pin, OPA is disabled.
001B
010B
011B
100B
101B
PE0/AN0/OPO is ADC channel 0 input pin, OPA is disabled.
Enable
1
Disable*
0, 1
Note: ²*² If the OPA configuration option is disabled, the OPAEN (bit 7 of OPAC) must not be set an unknown value will
be read.
Bit No.
0~3
Label
Function
AOF0~AOF3 Operational amplifier input offset voltage cancellation control bits
Operational amplifier input offset voltage cancellation reference selection bit
1/0: select OPP/OPN as the reference input
4
ARS
5
AOFM
6
OPAOP
Operational amplifier output; positive logic. This bit is read only.
7
OPAEN
Operational amplifier enable/disable (1/0)
Input offset voltage cancellation mode and operational amplifier mode selection
1/0: input offset voltage cancellation mode/operational amplifier mode
OPAC Register (Operational Amplifier Control Register)
O P P
O P N
P E 0 /A N 0 /O P O
S 1
S 2
P E 0 /A N 0
S 3
A O F 0 ~ A O F 3
O P A E N
A R S
0
0
1
1
A O F M
0
1
0
1
S 1
O N
O F F
O N
O N
S 2
O N
O N
O N
O F F
S 3
O F F
O N
O F F
O N
OPA Block Diagram
Rev. 1.00
28
December 13, 2006
HT45R38
The OPA allows its input voltage offset to be adjusted by using common mode inputs to calibrate the offset.
The calibration steps are as following:
S 1
O P P
S 2
O P N
P E 0 /A N 0
S 3
A O F 0 ~ A O F 3
O P A E N
P E 0 /A N 0 /O P O
Note: Set AOFM=1 to offset cancellation mode - S3 is closed
Set ARS to select which input pin is the reference voltage - S1 or S2 closed
Adjust AOF0~AOF3 until the output status has changed.
Set AOFM=0 to normalise the OPA mode
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
The LVR includes the following specifications:
V
· The low voltage (0.9V~VLVR) has to remain in its origi-
2 .2 V
nal state for longer than tLVR. If the low voltage state
does not exceed tLVR, the LVR will ignore it and will not
perform a reset function.
0 .9 V
· The LVR uses an ²OR² function with the external RES
Note: V
OPR is the voltage range for proper chip operation at 4MHz system clock.
signal to perform a chip reset.
V
L V R
3 .0 V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting the normal operation.
*2: Since low voltage has to be maintained its original state for longer than tLVR, therefore a tLVR delay enters
the reset mode.
Rev. 1.00
29
December 13, 2006
HT45R38
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Function
Description
1
Wake up PA0~PA7 (bit option)
None wake-up or wake-up
2
Pull high PA0~PA7 (bit option)
None pull-high or pull-high
3
Pull high PE0~PE4 (bit option)
None pull-high or pull-high
4
Pull high PB0~PB7 (port option)
None pull-high or pull-high
5
Pull high PC0~PC7 (port option) None pull-high or pull-high
6
OPA function
Enable or disable
7
WDT clock source
WDTOSC or fSYS/4
8
WDT
Enable or disable
9
CLRWDT
1 or 2 instructions
10
LVR
Enable or disable
11
OSC
X¢tal mode or RC mode
12
INT0 trigger edge
Disable, rising edge, falling edge or double edge
13
INT1 trigger edge
Disable, rising edge, falling edge or double edge
14
PWM0 output
Enable or disable
15
PWM1 output
Enable or disable
16
PWM mode
6+2 mode or 7+1 mode
Rev. 1.00
30
December 13, 2006
HT45R38
Application Circuits
R to F Application Circuit
V
D D
P B 0 ~ P B 7
0 .0 1 m F *
V D D
P A 0 /P W M
P A 1 /P W M
P A
P A 3 /IN T
P A 4 /IN T
P A 5 /T M R
P A 6 /T M R
P A
1 0 0 k W
R E S
0 .1 m F
L E D
P C 0 ~ P C 7
1 0 k W
0 .1 m F *
V S S
0
1
2
0
1
0
1
7
R
s e n s o r
1
R
s e n s o r
2
R C 1
O S C 1
O S C
C ir c u it
R C 2
O S C 2
S e e R ig h t S id e
R
s e n s o r
R C 1 2
O P N
R R E F
R C O U T
IN
O P P
C R E F
P E 0 /A N 0 /O P O
D is p la y
V
D D
1 2
R
*R
O S C
4 7 0 p F
O S C 1
fS
Y S
/4
*C
C 1
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
P E 1 /A N 1 ~ P E 4 /A N 4
C 2
O S C 2
R 1
H T 4 5 R 3 8
O S C
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
C to F Application Circuit 1
V
D D
P B 0 ~ P B 7
0 .0 1 m F *
V D D
P A 0 /P W M
P A 1 /P W M
P A
P A 3 /IN T
P A 4 /IN T
P A 5 /T M R
P A 6 /T M R
P A
1 0 0 k W
0 .1 m F
L E D
P C 0 ~ P C 7
R E S
1 0 k W
0 .1 m F *
V S S
0
2
1
0
1
0
1
7
R C 1
O S C 1
O S C
C ir c u it
D is p la y
R C 2
C
s e n s o r
1
C
s e n s o r
2
O S C 2
S e e R ig h t S id e
R C 1 2
O P N
C R E F
R C O U T
IN
O P P
R R E F
P E 0 /A N 0 /O P O
C
s e n s o r
V
1 2
*C
D D
R
O S C
4 7 0 p F
O S C 1
fS
*R
C 1
C 2
R 1
Rev. 1.00
/4
O S C 2
O S C 1
P E 1 /A N 1 ~ P E 4 /A N 4
H T 4 5 R 3 8
Y S
O S C 2
O S C
31
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
December 13, 2006
HT45R38
C to F Application Circuit 2
P B 0 ~ P B 7
V
0 .0 1 m F *
V D D
1 0 0 k W
0 .1 m F
L E D
P C 0 ~ P C 7
P A 0 /P W M 0
P A 1 /P W M 1
P A 2
P A 3 /IN T 0
P A 4 /IN T 1
P A 5 /T M R 0
P A 6 /T M R 1
P A 7
D D
R E S
1 0 k W
0 .1 m F *
C
s e n s o r
1
C
s e n s o r
2
R C 1
V S S
R C 2
D is p la y
O S C 1
O S C
C ir c u it
O S C 2
R C 1 2
S e e R ig h t S id e
O P N
R C O U T
IN
R R E F
O P P
C R E F
P E 0 /A N 0 /O P O
C
s e n s o r
1 2
V
D D
R
*R
O S C
4 7 0 p F
O S C 1
fS
C 1
*C
Y S
/4
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
P E 1 /A N 1 ~ P E 4 /A N 4
C 2
R 1
O S C 2
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C C ir c u it
H T 4 5 R 3 8
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
10pF
12kW
8MHz Crystal
10pF
4.3kW
4MHz Resonator
10pF
10kW
8MHz Resonator
10pF
4.7kW
3.58MHz Crystal
10pF
12kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal
25pF
15kW
2MHz Resonator
35pF
15kW
1MHz Crystal
68pF
15kW
480kHz Resonator
300pF
12kW
455kHz Resonator
300pF
12kW
429kHz Resonator
300pF
12kW
400kHz Resonator
300pF
12kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.
Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD
is stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The ²*R² resistance and ²*C² capacitance should be consideration for the frequency of RC OSC.
Rsensor1~Rsensor12 are the resistance sensors.
Csensor1~Csensor12 are the capacitance sensors.
Rev. 1.00
32
December 13, 2006
HT45R38
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
33
December 13, 2006
HT45R38
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter Power Down Mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
34
December 13, 2006
HT45R38
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
35
December 13, 2006
HT45R38
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
December 13, 2006
HT45R38
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
37
December 13, 2006
HT45R38
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
38
December 13, 2006
HT45R38
HALT
Enter Power Down Mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
December 13, 2006
HT45R38
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
40
December 13, 2006
HT45R38
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
December 13, 2006
HT45R38
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
42
December 13, 2006
HT45R38
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
43
December 13, 2006
HT45R38
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
44
December 13, 2006
HT45R38
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
45
December 13, 2006
HT45R38
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Note that this instruction is not valid for HT48R07A-1/HT48C07
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
46
December 13, 2006
HT45R38
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
47
December 13, 2006
HT45R38
Package Information
52-pin QFP (14´14) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
A
Rev. 1.00
1 3
Dimensions in mm
Min.
Nom.
Max.
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
48
December 13, 2006
HT45R38
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
49
December 13, 2006