19-2856; Rev 0; 4/03 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout The MAX9178 operates from a single +3.3V supply, and is available in a 16-pin TSSOP and 16-pin thin QFN package with exposed pad. The MAX9178 is specified for operation from -40°C to +85°C. Applications Digital Copiers DSLAMs Laser Printers Network Switches/Routers Cell Phone Base Stations Add/Drop Muxes Backplane Interconnect Digital Cross-Connects Clock Distribution Features ♦ Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk ♦ Pin Compatible with DS90LV047A and MAX9123 ♦ Guaranteed 400Mbps Data Rate ♦ Single-Ended Inputs Tolerate 1V Overshoot/Undershoot ♦ 250ps Maximum Pulse Skew ♦ IEC 61000-4-2 Level 4 ESD Tolerance on LVDS Outputs ♦ Conforms to ANSI TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply Ordering Information TEMP RANGE PIN-PACKAGE MAX9178EUE PART -40°C to +85°C 16 TSSOP MAX9178ETE -40°C to +85°C 16 Thin QFN-EP* *EP = Exposed pad. Typical Application Circuit LVDS SIGNALS Functional Diagram appears at end of data sheet. Pin Configurations 13 OUT2- VCC 4 GND 5 MAX9178 12 OUT3- IN3 6 11 OUT3+ IN4 7 10 OUT4+ EN 8 9 OUT4- TSSOP IN2 1 VCC 2 GND EN OUT1- OUT1+ 13 TX 107Ω RX TX 107Ω RX LVTTL/CMOS DATA INPUT 12 OUT2+ LVTTL/CMOS DATA OUTPUT TX 107Ω RX TX 107Ω RX 11 OUT2- MAX9178 3 10 OUT3- EXPOSED PAD IN3 4 9 5 6 7 8 OUT4+ 14 OUT2+ 14 OUT4- 15 OUT1+ IN2 3 15 EN 16 OUT1- 16 IN4 EN 1 IN1 TOP VIEW IN1 2 MAX9122 MAX9178 QFN OUT3+ 100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9178 General Description The MAX9178 quad low-voltage differential signaling (LVDS) line driver with high-ESD tolerance is ideal for applications requiring high data rates and low power with reduced noise. The MAX9178 is guaranteed to transmit data at speeds up to 400Mbps (200MHz) over controlled impedance of media of approximately 100Ω. The transmission media can be printed circuit (PC) board traces, backplanes, or cables. The MAX9178 accepts four LVTTL/LVCMOS inputs and translates them to LVDS output signals. All inputs tolerate overshoot of VCC +1V and undershoot of -1V. The EN and EN inputs are ANDed together and control the high-impedance outputs. When the device is disabled, power drops to ultra-low 12.6mW (typ). Outputs conform to the ANSI TIA/EIA-644 LVDS standard. MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-1.4V to (VCC + 1.4V) OUT_ to GND ........................................................-0.3V to +4.0V Short-Circuit Duration (OUT_) ....................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/oC above +70°C) .........755mW 16-Pin QFN (derate 16.9mW/oC above +70°C) .........1349mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C ESD Protection Human Body Model All Pins to GND ............................................................±2kV OUT_ ............................................................................±2kV IEC 61000-4-2 Level 4 Contact Discharge (OUT_)...............................................±8kV Air Discharge (OUT_) .....................................................±15kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, IN_ = high or low, EN = high, EN = low, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 250 368 450 mV 0.3 25 mV 1.28 1.375 V 0.3 25 mV 1.6 V LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 Change in Magnitude of VOS Between Complementary Output States ∆VOS Figure 1 Output High Voltage VOH Figure 1 Output Low Voltage VOL Figure 1 0.90 V 1.9 V Change in Magnitude of VOD Between Complementary Output States Offset Voltage Unterminated Output High Voltage VOHUT Output open, Figure 6 Unterminated Output Low Voltage VOLUT Output open, Figure 6 Differential Output Short-Circuit Current Magnitude IOSD 1.125 0.1 V VOD = 0 (Note 3) 9 mA -9 mA Output Short-Circuit Current IOS OUT_+ = 0 at IN_ = high, or OUT_- = 0 at IN_ = low Output High-Impedance Current IOZ EN = low and EN = high, OUT_ = 0 or VCC, no load -0.5 ±0.002 +0.5 µA Power-Off Output Current IOFF VCC, IN_, EN, EN = 0 or open, OUT_ = 0 or 3.6V, no load -0.5 ±0.001 +0.5 µA INPUTS (IN_, EN, EN) High-Level Input Voltage VIH 2.0 VCC + 1 V Low-Level Input Voltage VIL -1.0 +0.8 V 2 _______________________________________________________________________________________ Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, IN_ = high or low, EN = high, EN = low, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS 0 ≤ IN_, EN, EN ≤ VCC Input Current IIN MIN -20 VCC ≤ IN_, EN, EN ≤ VCC + 1 -1V ≤ IN_, EN, EN ≤ 0 -1.5 TYP MAX UNITS 5 +20 µA 0.67 1.5 -0.46 mA SUPPLY CURRENT Supply Current ICC IN_ = VCC or 0, EN = VCC, EN = 0, no load 3.8 6.0 ICCL IN_ = VCC or 0, EN = VCC, EN = 0, outputs loaded 18 25 ICCZ IN_ = VCC or 0, EN = 0, EN = VCC 3.8 6 mA SWITCHING CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 15pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 4–7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2, 3 0.9 1.4 2.0 ns Differential Propagation Delay Low to High tPLHD Figures 2, 3 0.9 1.5 2.0 ns Differential Pulse Skew tSKD1 Figures 2, 3 (Note 8) 0.1 0.25 ns Differential Channel-to-Channel Skew tSKD2 Figures 2, 3 (Note 9) 0.15 0.35 ns tSKD3 Figures 2, 3 (Note 10) 0.9 tSKD4 Figures 2, 3 (Note 11) 1.1 Differential Part-to-Part Skew ns Rise Time tR Figures 2, 3 0.20 0.43 0.70 ns Fall Time tF Figures 2, 3 0.20 0.41 0.70 ns Disable Time High to Z tPHZ Figures 4, 5 3.9 5 ns Disable Time Low to Z tPLZ Figures 4, 5 3.9 5 ns Enable Time Z to High tPZH Figures 4, 5 5.0 7 ns Enable Time Z to Low tPZL Figures 4, 5 5.0 7 ns Active to High Time tAH RL = 80Ω to 132Ω ±1%; Figures 6, 7 50 100 ns High to Active Time tHA RL = 80Ω to 132Ω ±1%; Figures 6, 7 (Note 12) 1.0 1.5 µs Maximum Operating Frequency fMAX (Note 13) 200 MHz Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +85°C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD, ∆VOD, VOS, and ∆VOS. Note 3: Guaranteed by design. Note 4: AC parameters are guaranteed by design and characterization. Limits are set at ±6 sigma. Note 5: CL includes probe and jig capacitance. Note 6: Pulse generator output for AC tests: tR = tF = 1ns (0.2 x VCC to 0.8 x VCC), 50% duty cycle, RO = 50Ω, VOH = VCC + 1V settling to VCC, VOL = -1V settling to zero, frequency = 200MHz. _______________________________________________________________________________________ 3 MAX9178 DC ELECTRICAL CHARACTERISTICS (continued) SWITCHING CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 15pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 4–7) Note 7: Pulse generator output for tPHZ, tPLZ, tPZH, tPZL, tAH, and tHA tests: tR = tF = 1ns (0.2 x VCC to 0.8 x VCC), 50% duty cycle, RO = 50Ω, VOH = VCC + 1V settling to VCC, VOL = -1V settling to zero, frequency = 100kHz. Note 8: tSKD1 is the magnitude of the difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 9: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 10: tSKD3 is the magnitude of the difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. Note 11: tSKD4 is the magnitude of the difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 12: After tHA time, all switching characteristics specifications are met. Note 13: Meets all AC parameters at fMAX = 200MHz with |VOD | ≥ 250mV. Typical Operating Characteristics (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE 4.6 4.2 3.8 OUT_ TO GND 3.4 -3.0 3.0 VIN = VCC OR GND -3.4 -3.8 -4.2 OUT_ TO VCC -4.6 -5.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT HIGH-IMPEDANCE STATE CURRENT vs. SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 30 0 -30 OUT_ TO VCC 3.6 MAX9178 toc04 OUT_ TO GND 60 370 DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9178 toc03 90 368 366 364 362 360 358 356 354 352 -60 350 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 4 MAX9178 toc02 VIN = VCC OR GND OUTPUT SHORT-CIRCUIT CURRENT (mA) MAX9178 toc01 OUTPUT SHORT-CIRCUIT CURRENT (mA) 5.0 OUTPUT HIGH-IMPEDANCE CURRENT (pA) MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout 3.5 3.6 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.5 3.6 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR 1.276 300 200 SUPPLY CURRENT (mA) 400 1.274 1.272 1.270 1.268 1.266 MAX9178 toc07 1.278 OFFSET VOLTAGE (V) 500 27 MAX9178 toc06 1.280 MAX9178 toc05 600 DIFFERENTIAL OUTPUT VOLTAGE (mV) SUPPLY CURRENT vs. FREQUENCY OFFSET VOLTAGE vs. SUPPLY VOLTAGE 24 21 ALL-CHANNELS SWITCHING 18 1.264 100 ONE-CHANNEL SWITCHING 1.262 0 3.2 3.3 3.4 3.5 3.6 10 100 1000 DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 24 22 20 ONE-CHANNEL SWITCHING ALL-CHANNELS SWITCHING 24 22 20 18 16 ONE-CHANNEL SWITCHING 3.2 3.3 3.4 3.5 3.6 -40 -15 10 35 60 SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY vs. AMBIENT TEMPERATURE DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE 1.6 tPLHD 1.5 1.4 tPHLD 1.3 3.0 160 180 140 120 100 80 60 FREQUENCY = 200MHz 60 20 1.0 0 TEMPERATURE (°C) 3.6 80 40 85 3.5 100 20 60 3.4 120 1.1 35 3.3 140 40 10 3.2 160 1.2 -15 3.1 200 DIFFERENTIAL SKEW (ps) 1.7 1.30 DIFFERENTIAL SKEW vs. AMBIENT TEMPERATURE FREQUENCY = 200MHz 180 DIFFERENTIAL SKEW (ps) 1.8 tPHLD 1.35 85 MAX9178 toc12 FREQUENCY = 200MHz 1.40 SUPPLY VOLTAGE (V) 200 MAX9178 toc11 2.0 tPLHD 1.45 1.25 18 3.1 FREQUENCY = 200MHz 1.50 MAX9178 toc13 SUPPLY CURRENT (mA) 26 1.55 MAX9178 toc10 FREQUENCY = 200MHz DIFFERENTIAL PROPAGATION DELAY (ns) MAX9178 toc08 28 MAX9178 toc09 SUPPLY CURRENT vs. AMBIENT TEMPERATURE ALL-CHANNELS SWITCHING -40 1 SUPPLY CURRENT vs. SUPPLY VOLTAGE 26 3.0 0.1 FREQUENCY (MHz) 28 DIFFERENTIAL PROPAGATION DELAY (ns) 3.1 SUPPLY VOLTAGE (V) FREQUENCY = 200MHz SUPPLY CURRENT (mA) 3.0 LOAD RESISTOR (Ω) 30 1.9 15 0.01 1.260 50 60 70 80 90 100 110 120 130 140 150 0 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9178 Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) TRANSITION TIME vs. SUPPLY VOLTAGE TRANSITION TIME vs. AMBIENT TEMPERATURE FREQUENCY = 200MHz 450 tR 400 FREQUENCY = 200MHz TRANSITION TIME (ps) 500 tF MAX9178 toc15 500 MAX9178 toc14 550 TRANSITION TIME (ps) MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout 450 tR tF 400 350 350 300 3.0 3.1 3.2 3.3 3.4 3.5 3.6 300 -40 -15 SUPPLY VOLTAGE (V) 10 35 60 85 TEMPERATURE (°C) Pin Description PIN 6 NAME FUNCTION TSSOP QFN 1 15 2 16 IN1 LVTTL/LVCMOS Input 1. Input internally pulled down. 3 1 IN2 LVTTL/LVCMOS Input 2. Input internally pulled down. 4 2 VCC Power-Supply. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. 5 3 GND 6 4 IN3 LVTTL/LVCMOS Input 3. Input internally pulled down. 7 5 IN4 LVTTL/LVCMOS input 4. Input internally pulled down. 8 6 EN LVTTL/LVCMOS Inverting Enable Input. All outputs are disabled when EN is high. Internally pulled down. EN LVTTL/LVCMOS Enable Input. All outputs are disabled when EN is low. Internally pulled down. Ground 9 7 OUT4- Inverting LVDS Output 4 10 8 OUT4+ Noninverting LVDS Output 4 11 9 OUT3+ Noninverting LVDS Output 3 12 10 OUT3- Inverting LVDS Output 3 13 11 OUT2- Inverting LVDS Output 2 14 12 OUT2+ Noninverting LVDS Output 2 15 13 OUT1+ Noninverting LVDS Output 1 16 14 OUT1- Inverting LVDS Output 1 — EP Exposed Pad Exposed Pad. Solder to ground plane. _______________________________________________________________________________________ Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout CL OUT_+ 2V TO VCC + 1 -1V TO 0.8V RL / 2 OUT_ + IN_ IN_ PULSE GENERATOR VOD RL VOS RL / 2 OUT_ - 50Ω CL OUT_- Figure 2. Transition Time and Propagation Delay Test Circuit Figure 1. Driver VOD and VOS Test Circuit VCC + 1V VCC 0.5 x VCC 0.5 x VCC IN_ 0 tPLHD -1V tPHLD OUT_0 (DIFFERENTIAL) 0 (DIFFERENTIAL) OUT_+ 80% 80% 0 (DIFFERENTIAL) VDIFF = (OUT_+) - (OUT_-) 20% VDIFF 0 (DIFFERENTIAL) 20% tF tR Figure 3. Transition Time and Propagation Delay Waveform Timing CL OUT_+ 2V TO VCC + 1V RL / 2 IN_ -1V TO 0.8V +1.2V RL / 2 OUT_CL EN PULSE GENERATOR 50Ω EN 1/4 MAX9178 Figure 4. High-Impedance Delay Test Circuit _______________________________________________________________________________________ 7 MAX9178 Test Circuits/Timing Diagrams Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout MAX9178 Test Circuits/Timing Diagrams (continued) VCC + 1V EN WHEN EN = LOW OR OPEN 1.5V VCC 1.5V 0 -1V VCC + 1V EN WHEN EN = HIGH VCC 1.5V 1.5V 0 -1V tPHZ tPZH OUT_+ WHEN IN_ = 2V TO VCC + 1 OUT_- WHEN IN_ = -1V TO 0.8V VOH 50% 50% 1.2V tPZL tPLZ 1.2V 50% 50% OUT_+ WHEN IN_ = -1V TO 0.8V OUT_- WHEN IN_ = 2V TO VCC + 1 VOL Figure 5. High-Impedance Delay Waveform Timing S1 OUT_+ CL PULSE GENERATOR IN_ RL 50Ω OUT_- TERMINATION ONLY. ZERO CABLE LENGTH. CL Figure 6. Active-to-High and High-to-Active Test Circuit IN_ VOHUT(MIN) OUT_+ OUT_VOLUT(MAX) tAH tHA RL DISCONNECTED RL CONNECTED Figure 7. Active-to-High and High-to-Active Timing Diagram 8 _______________________________________________________________________________________ Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout Termination The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9178 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90Ω and 132Ω, depending on the characteristic impedance of the transmission medium. Table 1 lists the I/O functions. Termination Detection The MAX9178 has a limited-capability termination detection circuit at each output that drives the output high when the output termination is removed (or is not present at power-up), and starts the output switching when a termination is connected. These circuits prevent EMI and crosstalk that occur (due to reflections) if an unterminated line is driven. Table 1. Input/Output Function Table ENABLES EN EN H L or open OUTPUT LOAD INPUTS Connected All other combinations of enable inputs X OUTPUTS IN_ OUT_+ OUT_- L L H H H L X Z Z Z = High impedance. X = Don’t care. Table 2. Cable Lengths and Frequencies CONDITIONS 100Ω cable termination, 5pF load (each output to ground), 10% to 90% duty cycle CABLE LENGTH (m) TYPICAL SWITCHING FREQUENCY (MHz) 1 10.75 2 8.5 4 7.8 Bench testing with CAT-5E unshielded twisted-pair cable showed the termination detection working for the cable lengths and frequencies listed in Table 2. Other combinations of cable length and frequency are possible. The termination detection worked with 30m of CAT-5 at 3MHz and with alternating 3MHz and 9MHz. The termination detection is prevented from working at various cable lengths, switching frequencies, and data patterns by reflections that discharge the detection circuit. Applications Information Power-Supply Bypassing Bypass V CC with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Output trace characteristics affect the performance of the MAX9178. Use controlled-impedance traces to match trace impedance to the transmission medium. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. _______________________________________________________________________________________ 9 MAX9178 Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9178 is a 400Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/ LVCMOS input levels and translates them to LVDS output signals. The MAX9178 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9178 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9178 produces an output voltage of 370mV when driving a 100Ω load. MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Transmission media should have a nominal differential impedance of 100Ω. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. Overshoot and Undershoot Voltage Protection The MAX9178 is designed to protect the inputs (IN_, EN, and EN) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND by up to 1V, an internal circuit limits input current to 1.5mA. RC 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF The IEC 61000-4-2 standard specifies ESD tolerance for electronic systems. The IEC 61000-4-2 model (Figure 8) specifies a 150pF capacitor that is discharged into the device through a 330Ω resistor. The MAX9178 outputs are rated for IEC 61000-4-2 level 4 (±8kV Contact Discharge and ±15kV Air Discharge). The Human Body Model (HBM, Figure 9) specifies a 100pF capacitor that is discharged into the device through a 1.5kΩ resistor. The IEC 61000-4-2 circuit discharges higher peak current and more energy than the HBM circuit due to the lower series resistance and larger capacitor. Board Layout A four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Separate the LVTTL/LVCMOS and LVDS signals to prevent coupling. RC 1MΩ RD 330Ω CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 8. IEC 61000-4-2 Contact Discharge ESD Test Model 10 IEC 61000-4-2 Level 4 ESD Protection HIGHVOLTAGE DC SOURCE Cs 100pF RD 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 9. Human Body ESD Test Model ______________________________________________________________________________________ DEVICE UNDER TEST Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout OUT1+ Chip Information TRANSISTOR COUNT: 1089 PROCESS: CMOS IN1 OUT1- OUT2+ IN2 OUT2- OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN EN ______________________________________________________________________________________ 11 MAX9178 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 12 ______________________________________________________________________________________ A Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A ______________________________________________________________________________________ 13 MAX9178 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX9178 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.