19-1927; Rev 0; 2/01 Quad LVDS Line Driver with Flow-Through Pinout The MAX9123 operates from a single +3.3V supply and is specified for operation from -40°C to +85°C. It is available in 16-pin TSSOP and SO packages. Refer to the MAX9121/ MAX9122* data sheet for quad LVDS line receivers with integrated termination and flow-through pinout. Features ♦ Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk ♦ Pin Compatible with DS90LV047A ♦ Guaranteed 800Mbps Data Rate ♦ 250ps Maximum Pulse Skew ♦ Conforms to TIA/EIA-644 LVDS Standard ♦ Single +3.3V Supply ♦ 16-Pin TSSOP and SO Packages Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX9123EUE -40°C to +85°C 16 TSSOP MAX9123ESE -40°C to +85°C 16 SO Typical Applications Circuit Applications Digital Copiers DSLAMs Laser Printers Network Switches/Routers Cell Phone Base Stations Add Drop Muxes Backplane Interconnect Digital Cross-Connects Clock Distribution LVDS SIGNALS MAX9122* MAX9123 Pin Configuration TX 107Ω RX TX 107Ω RX LVTTL/CMOS DATA INPUT TOP VIEW EN 1 16 OUT1- IN1 2 15 OUT1+ IN2 3 14 OUT2+ VCC 4 MAX9123 LVTTL/CMOS DATA OUTPUT TX 107Ω RX TX 107Ω RX 13 OUT2- GND 5 12 OUT3- IN3 6 11 OUT3+ IN4 7 10 OUT4+ EN 8 9 OUT4- TSSOP/SO 100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES * Future product—contact factory for availability. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX9123 General Description The MAX9123 quad low-voltage differential signaling (LVDS) differential line driver is ideal for applications requiring high data rates, low power, and low noise. The MAX9123 is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100Ω. The transmission media may be printed circuit (PC) board traces, backplanes, or cables. The MAX9123 accepts four LVTTL/LVCMOS input levels and translates them to LVDS output signals. Moreover, the MAX9123 is capable of setting all four outputs to a high-impedance state through two enable inputs, EN and EN, thus dropping the device to an ultra-low-power state of 16mW (typ) during high impedance. The enables are common to all four transmitters. Outputs conform to the ANSI TIA/EIA-644 LVDS standard. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. MAX9123 Quad LVDS Line Driver with Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +3.9V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW 16-Pin SO (derate 8.7mW/°C above +70°C)................696mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection Human Body Model, IN_, OUT_+, OUT_-.......................±4kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 250 368 450 mV 1 35 mV 1.25 1.375 V 4 25 mV 1.6 V LVDS OUTPUT (OUT_+, OUT_-) Differential Output Voltage VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 Change in Magnitude of VOS Between Complementary Output States ∆VOS Figure 1 Output High Voltage VOH Output Low Voltage VOL Differential Output Short-Circuit Current (Note 3) IOSD Change in Magnitude of VOD Between Complementary Output States Offset Voltage 1.125 0.90 V Enabled, VOD = 0 -9 mA -9 mA Output Short-Circuit Current IOS OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0, enabled Output High-Impedance Current IOZ EN = low and EN = high, OUT_+ = 0 or VCC, OUT_- = 0 or VCC , RL = ∞ -10 10 µA Power-Off Output Current IOFF VCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_= 0 or 3.6V, RL = ∞ -20 20 µA -3.8 INPUTS (IN_, EN, EN) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V Input Current IIN IN_, EN, EN = 0 or VCC -20 20 µA No-Load Supply Current ICC RL = ∞, IN_ = VCC or 0 for all channels 9.2 11 mA Loaded Supply Current ICCL 22.7 30 mA Disabled Supply Current ICCZ RL = 100Ω, IN_ = VCC or 0 for all channels Disabled, IN_ = VCC or 0 for all channels, EN = 0, EN = VCC 4.9 6 mA SUPPLY CURRENT 2 _______________________________________________________________________________________ Quad LVDS Line Driver with Flow-Through Pinout (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 15pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 4, 5, 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2 and 3 0.7 1.7 ns Differential Propagation Delay Low to High tPLHD Figures 2 and 3 0.7 1.7 ns Differential Pulse Skew (Note 7) tSKD1 Figures 2 and 3 0.04 0.25 ns Differential Channel-to-Channel Skew (Note 8) tSKD2 Figures 2 and 3 0.07 0.35 ns Differential Part-to-Part Skew (Note 9) tSKD3 Figures 2 and 3 0.13 0.8 ns Differential Part-to-Part Skew (Note 10) tSKD4 0.43 1.0 ns Figures 2 and 3 Rise Time tTLH Figures 2 and 3 0.2 0.39 1.0 ns Fall Time tTHL Figures 2 and 3 0.2 0.39 1.0 ns Disable Time High to Z tPHZ Figures 4 and 5 2.7 5 ns Disable Time Low to Z tPLZ Figures 4 and 5 2.7 5 ns Enable Time Z to High tPZH Figures 4 and 5 2.3 7 ns Enable Time Z to Low tPZL Figures 4 and 5 2.3 7 ns Maximum Operating Frequency (Note 11) fMAX 400 MHz Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. Note 3: Guaranteed by correlation data. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes probe and jig capacitance. Note 6: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0% to 100%). Note 7: tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 8: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. Note 10: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 11: fMAX signal generator conditions: VOL = 0, VOH = 3V, f = 400MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0% to 100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD ≥ 250mV. _______________________________________________________________________________________ 3 MAX9123 SWITCHING CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) OUTPUT LOW VOLTAGE vs. POWER-SUPPLY VOLTAGE 1.094 1.092 1.090 1.090 3.3 POWER-SUPPLY VOLTAGE (V) OUTPUT HIGH-IMPEDANCE STATE CURRENT vs. POWER-SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs. POWER SUPPLY -100 -150 -200 -250 -3.670 -3.665 -3.660 -3.655 385 3.0 380 375 370 365 360 355 OFFSET VOLTAGE vs. POWER-SUPPLY VOLTAGE 1.252 1.248 1.244 3.3 500 450 400 350 3.6 100 110 120 130 140 LOAD RESISTOR (Ω) POWER-SUPPLY CURRENT vs. FREQUENCY POWER-SUPPLY CURRENT vs. POWER-SUPPLY VOLTAGE VIN = 0 to 3V 38 90 POWER-SUPPLY VOLTAGE (V) 40 POWER-SUPPLY CURRENT (mA) MAX9123 toc07 1.256 550 300 3.0 POWER-SUPPLY VOLTAGE (V) 1.260 3.6 600 35 33 30 28 ALL SWITCHING 25 25.0 POWER-SUPPLY CURRENT (mA) 3.6 MAX9123 toc08 3.3 3.3 DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR 350 3.0 MAX9123 toc03 -3.675 POWER-SUPPLY VOLTAGE (V) MAX9123 toc05 -50 390 DIFFERENTIAL OUTPUT VOLTAGE (V) VIN = VCC or GND -3.680 3.6 POWER-SUPPLY VOLTAGE (V) 0 -3.685 -3.650 3.0 3.6 -3.690 MAX9123 toc06 1.092 3.3 MAX9123 toc02 1.096 VIN = VCC or GND -3.695 FREQ = 1MHz VIN = 0 to 3V 24.0 150 MAX9123 toc09 1.094 1.098 -3.700 DIFFERENTIAL OUTPUT VOLTAGE (mV) OUTPUT LOW VOLTAGE (V) 1.096 3.0 OUTPUT HIGH-IMPEDANCE STATE CURRENT (pA) 1.100 MAX9123 toc01 1.098 MAX9123 toc04 OUTPUT HIGH VOLTAGE (V) 1.100 OUTPUT SHORT-CIRCUIT CURRENT vs. POWER-SUPPLY VOLTAGE OUTPUT SHORT-CIRCUIT CURRENT (mA) OUTPUT HIGH VOLTAGE vs. POWER-SUPPLY VOLTAGE OFFSET VOLTAGE (V) MAX9123 Quad LVDS Line Driver with Flow-Through Pinout 23.0 22.0 21.0 23 ONE SWITCHING 1.240 3.3 POWER-SUPPLY VOLTAGE (V) 4 20.0 20 3.0 3.6 0.1 1 10 FREQUENCY (MHz) 100 1000 3.0 3.3 POWER-SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.6 Quad LVDS Line Driver with Flow-Through Pinout 22.0 21.0 20.0 1.550 1.500 1.600 MAX9123 toc11 FREQ = 1MHz DIFFERENTIAL PROPAGATION DELAY (ns) 23.0 1.600 DIFFERENTIAL PROPAGATION DELAY (ns) tPLHD 1.450 1.400 tPHLD 1.350 1.300 1.250 -15 10 35 60 85 3.0 AMBIENT TEMPERATURE (°C) 3.3 1.400 1.300 tPHLD FREQ = 1MHz 1.200 -40 3.6 -15 FREQ = 1MHz 200 60 40 FREQ = 1MHz 175 DIFFERENTIAL SKEW (ps) 80 35 60 85 DIFFERENTIAL SKEW vs. AMBIENT TEMPERATURE MAX9123 toc13 100 10 AMBIENT TEMPERATURE (°C) POWER-SUPPLY VOLTAGE (V) DIFFERENTIAL SKEW vs. POWER-SUPPLY VOLTAGE DIFFERENTIAL SKEW (ps) tPLHD 1.100 1.200 150 125 100 75 50 20 25 0 0 3.3 3.6 -40 POWER-SUPPLY VOLTAGE (V) 390 380 370 tTLH tTHL 35 60 85 TRANSITION TIME vs. AMBIENT TEMPERATURE 600 FREQ = 1MHz 550 TRANSITION TIME (ps) FREQ = 1MHz 10 AMBIENT TEMPERATURE (°C) TRANSITION TIME vs. POWER-SUPPLY VOLTAGE 400 -15 360 500 450 tTLH 400 350 tTHL 300 350 MAX9123 toc16 3.0 MAX9123 toc15 -40 1.500 MAX9123 toc14 24.0 MAX9123 toc10 FREQ = 1MHz VIN = 0 to 3V TRANSITION TIME (ps) POWER-SUPPLY CURRENT (mA) 25.0 DIFFERENTIAL PROPAGATION DELAY vs. AMBIENT TEMPERATURE DIFFERENTIAL PROPAGATION DELAY vs. POWER SUPPLY MAX9123 toc12 POWER-SUPPLY CURRENT vs. AMBIENT TEMPERATURE 250 200 340 3.0 3.3 POWER-SUPPLY VOLTAGE (V) 3.6 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9123 Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) Quad LVDS Line Driver with Flow-Through Pinout MAX9123 Pin Description PIN NAME FUNCTION 1 EN Driver Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and are high impedance. 2, 3, 6, 7 IN_ LVTTL/LVCMOS Driver Inputs 4 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. 5 GND 8 EN 9, 12, 13, 16 OUT_- Inverting LVDS Driver Outputs 10, 11, 14, 15 OUT_+ Noninverting LVDS Driver Outputs Ground Driver Enable Input. The transmitter is disabled when EN is high. EN is internally pulled down. Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9123 is an 800Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The MAX9123 generates a 2.5mA to 4.0mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9123 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9123 produces an output voltage of 370mV when driving a 100Ω load. 6 Termination Because the MAX9123 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9123 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90Ω and132Ω, depending on the characteristic impedance of the transmission medium. Table 1. Input/Output Function Table ENABLES INPUTS OUTPUTS EN EN IN_ OUT_+ OUT_ - H L or open L L H H L or open H H L Don’t care Z Z All other combinations of ENABLE pins Applications Information Power-Supply Bypassing Bypass V CC with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Output trace characteristics affect the performance of the MAX9123. Use controlled-impedance traces to match trace impedance to the transmission medium. _______________________________________________________________________________________ Quad LVDS Line Driver with Flow-Through Pinout OUT_ + RL/2 IN_ IN_ S VOS GND VOD VO VCC MAX9123 CL OUT_+ GENERATOR RL/2 RL OUT_ - 50Ω CL OUT_- Figure 2. Driver Propagation Delay and Transition Time Test Circuit Figure 1. Driver VOD and VOS Test Circuit 3V IN_ 1.5V 1.5V tPLHD tPHLD 0 OUT_ - VOH 0 DIFFERENTIAL 0 OUT_+ VOL 80% 0 VDIFF 80% VDIFF = (VOUT_+) - (VOUT_-) 0 20% 20% tTLH tTHL Figure 3. Driver Propagation Delay and Transition Time Waveforms Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the LVTTL/LVCMOS and LVDS signals from each other to prevent coupling. Cables and Connectors Transmission media should have a nominal differential impedance of 100Ω. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate Chip Information TRANSISTOR COUNT: 1246 PROCESS: CMOS _______________________________________________________________________________________ 7 MAX9123 Quad LVDS Line Driver with Flow-Through Pinout Functional Diagram CL OUT1+ OUT_+ VCC IN_ IN1 RL/2 OUT1- GND +1.2V EN GENERATOR RL/2 EN 50Ω OUT2+ OUT_- 1/4 MAX9123 IN2 CL OUT2- Figure 4. Driver High-Impedance Delay Test Circuit OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN EN EN WHEN EN = 0 OR OPEN 3V 1.5V 1.5V 0 3V 1.5V 1.5V EN WHEN EN = VCC 0 tPZH tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 VOH 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL Figure 5. Driver High-Impedance Delay Waveform 8 _______________________________________________________________________________________ Quad LVDS Line Driver with Flow-Through Pinout TSSOP,NO PADS.EPS _______________________________________________________________________________________ 9 MAX9123 Package Information Quad LVDS Line Driver with Flow-Through Pinout SOICN.EPS MAX9123 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.