Power Dissipation: LVDS Driver/Receiver Family

Aeroflex Colorado Springs Application Note
AN-LVDS-002-01
Calculating Power Dissipation on LVDS Driver/Receiver Family
Table 1: Cross Reference of Applicable Products
Manufacturer Part
SMD #
Number
3.3-VOLT QUAD DRIVER
UT54LVDS031LV/E
5962-98651
Product Name:
Device
Type
02, 03,
04, 05
Internal PIC*
3.3-VOLT QUAD RECEIVER
UT54LVDS032LV/E
5962-98652
02, 03,
04, 05
3.3-VOLT QUAD RECEIVER with
TERMINATION RESISTOR
3.3V BUS QUAD DRIVER
3.3V DUAL DRIVER and
RECEIVER
5.0V QUAD DRIVER
5.0V QUAD RECEIVER
5.0V QUAD DRIVER with COLD
SPARE
5.0V QUAD RECEIVER with
COLD SPARE
UT54LVDS032LVT
5962-04201
01, 02
UT54LVDM031LV
UT54LVDM055LV
5962-06201
5962-06202
01
01
WD03,
WD07,
WD28,
WD30
WD04,
WD08,
WD29,
WD31
WD06,
WD10
WD21
WD22
UT54LVDS031
UT54LVDS032
UT54LVDSC031
5962-95833
5962-95834
5962-95833
02
02
03
JR05, JR08
JR06. JR09
JR10
UT54LVDSC032
5962-95834
03
JR11
*PIC = Product Identification Code
1.0 Overview
Low Voltage Differential Signaling (LVDS) and bus Low Voltage Differential Signaling
(LVDM) technologies are excellent solutions for moving large amounts of data quickly between
system components. LVDS/LVDM systems run at high data rates, with low switching power,
high noise immunity, and wide common mode range.
Accurate power calculations are necessary determine system power supply and thermal
management requirements. The purpose of this application note is to review power consumption
of Aeroflex Colorado Springs LVDS/LVDM driver and receiver families. To perform a thorough
power analysis, it is necessary to investigate both static power consumption and “at frequency” or
dynamic power consumption. Static power is the power dissipated under DC conditions when the
part is powered, the drivers/receivers are enabled, but the device is not switching. Dynamic
power consumption is due to the clocking and switching activity of the device.
This application note develops the components of LVDS/LVDM power consumption and
example power dissipation calculations for typical LVDS/LVDM differential line drivers and
receivers.
A standard point-to-point configuration is shown in Figure 1. This configuration is terminated by
either a 100Ω or 35Ω resistor across the differential pair. Termination resistor selection is
Creation Date: 09/16/09
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determined the differential signaling standard is used. LVDS requires a 100Ω resistor, while
LVDM requires 35Ω. A constant current source feeds the differential outputs of the driver. The
direction of current flow through the termination resistor (RT) determines the logic state of the
receiver output. In most cases (except when UT54LVDS032LVT is used) the termination is
external to the receiver input terminals. Total power consumed by the standard point-to-point
configuration is the device power minus the termination power. The LVDS output power
consumption is a function of the output swing and the termination.
Figure 1. Standard point-to-point LVDS Driver Receiver Configuration
2.0 Technical Figures and Data
The following plots show active current, or AIDD, measurements versus frequency and are used
as input current for calculating power dissipation and power dissipation capacitance(CPD). The
AIDD values are from maximum measurements taken during characterization of a single
driver/receiver channel on each device configured under the following conditions.
Please note that the following data was obtained in a lab. The test setup does not match the test
configurations shown for the AC and DC electrical characteristics described in the Aeroflex
Datasheets and corresponding DSCC SMDs.
2.1 3.3V Device Data
Devices: UT54LVDS031LV/E, UT54LVDS032LV/E, UT54LVDS032LVT,
UT54LVDM031LV, and UT54LVDM055LV
Temperature:
Voltage:
Frequency:
TC = 25°C, +125°C, -55°C,
VDD =3.3 V
f =1MHz, 50MHz, 100MHz, 150MHz, 200MHz
Creation Date: 09/16/09
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EN = 3.3V
EN = 0V
VDD
DOUT+
+
CLT
DIN
100 Ω
-
DOUTCLT
Figure 2A. LVDS Driver Test Configuration.
Unused drivers are driven low, meaning DIN = Vss
VDD
EN = 3.3V
EN = 0V
+
RIN+
ROUT
CLT
-
RIN-
Figure 2B. LVDS Receiver Test Configuration.
Unused receivers have inputs floating, RIN+ = RIN- = FLOAT
UT54LVDS031LV/E AIDD
20
19.5
19
AIDD (mA)
18.5
18
25°C
17.5
-55°C
17
125°C
16.5
16
15.5
15
14.5
0
50
100
150
200
Frequency (MHz)
Figure 2. UT54LVDS031LV/E Active current vs. Frequency
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UT54LVDS032LV AIDD
35
30
AIDD (mA)
25
25°C
-55°C
20
125°C
15
10
5
0
50
100
150
200
Frequency (MHz)
Figure 3. UT54LVDS032LV/E Active current vs. Frequency
UT54LVDS032LVT AIDD
35
30
AIDD (mA)
25
25°C
20
-55°C
125°C
15
10
5
0
50
100
150
200
Frequency (MHz)
Figure 4. UT54LVDS032LVT Active current vs. Frequency
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UT54LVDM031LV AIDD
19
18.5
18
AIDD (mA)
17.5
17
25°C
16.5
-55°C
16
125°C
15.5
15
14.5
14
0
50
100
150
200
Frequency (MHz)
Figure 5. UT54LVDM031LV Active current vs. Frequency
AIDD (mA)
UT54LVDM055LV AIDD DRIVER/RECEIVER
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
16.5
25°C
-55°C
125°C
0
50
100
150
200
Frequency (MHz)
Figure 6. UT54LVDM055LV Active current vs. Frequency
Using the AIDD graphs provided above, or the data contained in tables 2 through 6 below, an
estimate of the power supply current can be calculated by taking the slope of the line between two
adjacent frequencies at a given temperature and multiplying by the user’s desired frequency. The
values in the “Slope (mA/MHz)” column are the values for the power supply input current that
will be used in determining the power dissipation, power dissipation capacitance, and dynamic
current consumption later in this application note.
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Power dissipation capacitance or (CPD) for the LVDS drivers was calculated using
equation 1 as follows. It can be noted that the LVDS driver output switches only 340mV
which is approximately 10x less than VDD = 3.3V or 5.0V, so CLT can be neglected.
C PD =
Average( AIDD( slope) )
VDD
(1)
The CPD value presented in Table 2 was calculated as follows in example 1.
2.1.1 Example 1
C PD =
Average( AIDD( slope) ) Average(0.0236, 0.221,0.216 )
=
= 6.81 pF
VDD
3.3V
CPD for the LVDS receivers was calculated using equation 2 as follows. Since the LVDS
receiver outputs switch rail to rail VDD = 3.3V or 5.0V, CLT must be accounted for.
C PD =
Average( AIDD( slope) )
− C LT
VDD
(2)
The CPD value presented in Table 3 was calculated as follows in example 2.
2.1.2 Example 2
C PD =
Average(0.178, 0.178, 0.180)
Average( AIDD( slope) )
− C LT =
− 40 pF = 14.37 pF
VDD
3.3
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Table 2.
UT54LVDS031LV/E Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS031LV/E
VDD=3.3V
CLT=20pF
CPD=6.81pF
Creation Date: 09/16/09
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
50
100
150
200
AIDD
Slope
(mA/MHz)
(mA)
15.0
15.1
16.5
0.028
17.7
0.024
18.4
0.014
19.8
0.028
Average Slope = 0.0236
-55
-55
-55
-55
-55
-55
SIDD
0
1
50
100
150
200
15.2
15.3
16.7
0.028
17.8
0.022
18.6
0.016
19.7
0.022
Average Slope = 0.0221
125
125
125
125
125
125
SIDD
0
1
50
100
150
200
15.0
15.1
16.4
0.026
17.3
0.018
18.5
0.024
19.4
0.018
Average Slope = 0.0216
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Table 3.
UT54LVDS032LV/E E Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS032LV/E
VDD=3.3V
CLT=40pF
CPD=14.37pF
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
50
100
150
200
Slope
AIDD
(mA/MHz)
(mA)
10.9
11
20
0.183
28.7
0.174
31
0.046*
32
0.02*
Average Slope = 0.178
-55
-55
-55
-55
-55
-55
SIDD
0
1
50
100
150
200
12.1
12.2
20
0.159
29.9
0.198
32.2
0.046*
33.5
0.026*
Average Slope = 0.178
125
125
125
125
125
125
SIDD
0
1
50
100
150
200
9.8
9.9
18.9
0.183
27.8
0.178
30.3
0.05*
30.8
0.01*
Average Slope = 0.180
* = These values were not included in the Average Slope calculation. These values were omitted because
the output of the receiver was not swinging rail to rail.
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Table 4.
UT54LVDS032LVT E Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS032LVT
VDD=3.3V
CLT=40pF
CPD=11.31pF
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
50
100
150
200
AIDD
(mA)
Slope
(mA/MHz)
7.3
7.49
18.04
0.215
24
0.119
30.98
0.139
31.43
0.009*
Average Slope =0.158
-55
-55
-55
-55
-55
-55
SIDD
0
1
50
100
150
200
9.1
9.35
20.77
0.233
28
0.144
32.01
0.080*
32.98
0.019*
Average Slope =0.188
125
125
125
125
125
125
SIDD
0
1
50
100
150
200
7.08
7.2
17.67
0.213
23.1
0.1086
29.81
0.1342
30.4
0.0118*
Average Slope =0.161
* = These values were not included in the Average Slope calculation. These values were omitted because
the output of the receiver was not swinging rail to rail.
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Table 5.
UT54LVDM031LV Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDM031LV
VDD=3.3V
CLT=20pF
CPD=4.72pF
Creation Date: 09/16/09
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
50
100
150
200
AIDD
Slope
(mA/MHz)
(mA)
14.53
14.56
15.17
0.0124
15.54
0.0074
16.27
0.0146
18.09
0.0364
Average Slope = 0.017
-55
-55
-55
-55
-55
-55
SIDD
0
1
50
100
150
200
14.9
14.96
15.65
0.0140
16.48
0.0166
17.1
0.0124
18.17
0.0214
Average Slope = 0.016
125
125
125
125
125
125
SIDD
0
1
50
100
150
200
14.7
14.72
14.96
0.0048
15.45
0.0098
15.76
0.0062
17.3
0.0308
Average Slope = 0.013
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Table 6.
UT54LVDM055LV Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDM055LV
VDD=3.3V
CLT=20pF (DRIVER)
CLT=40pF (RECEIVER)
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
50
100
150
200
AIDD
Slope
(mA/MHz)
(mA)
17
17.03
17.97 0.0191837
18.9
0.0186
20.56
0.0332
22.7
0.0428
Average Slope =0.0284
CPD=8.25pF
Creation Date: 09/16/09
-55
-55
-55
-55
-55
-55
SIDD
0
1
50
100
150
200
17.23
18.17
18.44 0.0055102
19.4
0.0192
21.01
0.0322
23.81
0.056
Average Slope =0.0282
125
125
125
125
125
125
SIDD
0
1
50
100
150
200
16.9
17
17.32 0.0065306
18.1
0.0156
20.21
0.0422
22
0.0358
Average Slope =0.025
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2.2 5.0V Device Data
Devices: UT54LVDS031, UT54LVDS032, UT54LVDSC031, and UT54LVDSC032
Temperature:
Voltage:
Frequency:
TC = 25°C, +125°C, -55°C
VDD =5.0 V
f =1MHz, 25MHz, 50MHz, 75MHz, 100MHz
AIDD (mA)
UT54LVDS031 AIDD
21
20.5
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
25°C
-55°C
125°C
0
20
40
60
80
100
120
Frequency (MHz)
Figure 7. UT54LVDS031 Active current vs. Frequency
UT54LVDS032 AIDD
35
30
AIDD (mA)
25
25°C
20
-55°C
125°C
15
10
5
0
20
40
60
80
100
120
Frequency (MHz)
Figure 8. UT54LVDS032 Active current vs. Frequency
Creation Date: 09/16/09
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AIDD (mA)
UT54LVDSC031 AIDD
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
14
25°C
-55°C
125°C
0
20
40
60
80
100
120
Frequency (MHz)
Figure 9. UT54LVDSC031 Active current vs. Frequency
UT54LVDCS032 AIDD
35
30
AIDD (mA)
25
25°C
-55°C
20
125°C
15
10
5
0
20
40
60
80
100
120
Frequency (MHz)
Figure 10. UT54LVDSC032 Active current vs. Frequency
Again, the device characterization data used to generate Figures 7 to 10 follows in Tables
7 through 10. Using the AIDD graphs provided above, or the data contained below, an
estimate of the power supply current can be calculated by taking the slope of the lines at
various frequencies.
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Table 7.
UT54LVDS031 Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS031
VDD=5.0V
CLT=20pF
CPD=9.31pF
Creation Date: 09/16/09
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
25
50
75
100
AIDD
Slope
(mA/MHz)
(mA)
15.1
15.2
16.6
0.0583
17.8
0.048
18.6
0.032
19.7
0.044
Average Slope =0.046
-55
-55
-55
-55
-55
-55
SIDD
0
1
25
50
75
100
15.8
15.9
17
0.0458
18.2
0.048
19.4
0.048
20.4
0.04
Average Slope =0.045
125
125
125
125
125
125
SIDD
0
1
25
50
75
100
14.9
15.0
16.5
0.0625
17.7
0.048
18.4
0.028
19.8
0.056
Average Slope =0.048
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Table 8.
UT54LVDS032 Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS032
VDD=5.0V
CLT=40pF
CPD=21.12pF
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
25
50
75
100
AIDD
(mA)
Slope
(mA/MHz)
6.8
7
14.5
0.3125
22
0.3
26.7
0.188*
31
0.172*
Average Slope =0.306
-55
-55
-55
-55
-55
-55
SIDD
0
1
25
50
75
100
8
8.2
15.9 0.32083333
23.5
0.304
27
0.14*
32.7
0.228*
Average Slope =0.312
125
125
125
125
125
125
SIDD
0
1
25
50
75
100
6.3
6.5
14
0.3125
21.1
0.284
25.4
0.172*
30.2
0.192*
Average Slope =0.298
* = These values were not included in the Average Slope calculation. These values were omitted because
the output of the receiver was not swinging rail to rail.
Creation Date: 09/16/09
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Table 9.
UT54LVDSC031 Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDSC031
VDD=5.0V
CLT=20pF
CPD=10.2pF
Creation Date: 09/16/09
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
25
50
75
100
AIDD
Slope
(mA/MHz)
(mA)
15.16
15.23
15.83
0.025
16.72
0.0356
19.3
0.1032
21.2
0.076
Average Slope =0.0599
-55
-55
-55
-55
-55
-55
SIDD
0
1
25
50
75
100
15.5
15.56
17.3
0.0725
18.78
0.0592
20.3
0.0608
21.4
0.044
Average Slope =0.0591
125
125
125
125
125
125
SIDD
0
1
25
50
75
100
14.4
14.57
14.95 0.0158333
15.16
0.0084
16.35
0.0476
19.18
0.1132
Average Slope =0.046
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Table 10.
UT54LVDSC032 Current vs. Frequency Data over Temperature with mA/MHz calculated
UT54LVDS032
VDD=5.0V
CLT=40pF
CPD=26.43pF
Temperature
(°C)
25
25
25
25
25
25
Frequency
(MHz)
SIDD 0
1
25
50
75
100
AIDD
Slope
(mA/MHz)
(mA)
6.8
7.09
15.04
0.3312
24.03
0.3596
25.9
0.0748*
29.87
0.1588*
Average Slope =0.345
-55
-55
-55
-55
-55
-55
SIDD
0
1
25
50
75
100
8.1
8.34
15.4
0.294
25.76
0.4144
30
0.1696*
33.21
0.1284*
Average Slope =0.354
125
125
125
125
125
125
SIDD
0
1
25
50
75
100
6.53
6.77
14.2
0.3095
21.3
0.284
24.8
0.14*
30.11
0.2124*
Average Slope =0.296
* = These values were not included in the Average Slope calculation. These values were omitted because
the output of the receiver was not swinging rail to rail.
Creation Date: 09/16/09
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3.0 Calculating of Power with Variable Load Capacitance
The following equations and examples are provided as a guide for estimating static power
dissipation, dynamic power dissipation, and power dissipation capacitance using various
capacitive loads.
Definition of Terms:
VDD
VOD
VOL
VOL(actual)
VOH
VOH(actual)
Supply Voltage (V)
Differential Output Voltage, ±0.340V for Drivers/Receivers (V)
Low-level output voltage (V)
Load Dependant Low-level output voltage (V)
High-level output voltage (V)
Load Dependant High-level output voltage (V)
AIDD
AIDD(slope)
AIDD(frequency)
SIDD
IOL
IOH
IOD
Active Current (mA)
Slope of AIDD (mA/MHz)
Active current at given frequency (mA)
Standby Current Device Enabled f=0MHz (mA)
Low level output current (mA)
High level output current (mA)
LVDS Driver Output Current (mA)
PDCL
PDCH
Percent Duty Cycle Driving Logic Low (%)
Percent Duty Cycle Driving Logic High (%)
NSWDP
NO
Number of switching differential pairs
Number of switching CMOS outputs
CPD
CL
CLT
Power Dissipation Capacitance (F)
Load Capacitance (F)
Capacitive per switching output Tester Load (F)
f
PRLOAD
PSTD
PSTR
PDYND
PDYNR
PTOTALD
PTOTALR
Frequency (Hz)
Resistive Load Output Power (W)
Static DC Power Dissipation for Driver (W)
Static DC Power Dissipation for Receiver (W)
Dynamic Power Dissipation for Driver (W)
Dynamic Power Dissipation for Receiver (W)
Total Driver Power Dissipation (W)
Total Receiver Power Dissipation (W)
Driver Static Power is the power the device consumes when enabled and VDD is within
the recommended operating conditions. Dynamic power is the power required to switch
“N” number of LVDS/LVDM differential output pairs or single ended digital output
loads. The total driver power is the static power plus the dynamic power plus the internal
switching power at a given toggle frequency.
Creation Date: 09/16/09
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LVDS Driver Power Calculations:
Static Device Power (PSTD):
PSTD = SIDD * VDD
(3)
Dynamic Power per Switching Driver (PDYND):
(( (
))
)
PDYND = C PD VDD * f + (C L (VDD * VOD ) * f )
2
(4)
Total Driver Power (PTOTALD):
PTOTALD = (PSTD + ( N SWDP * PDYND )) =
(SIDD * VDD ) + (N SWDP [(C PD (VDD 2 * f )) + (C L (VDD * VOD ) * f )])
(5)
LVDS Receiver Power Calculations:
Static Device Power (PSTR):
PSTR = SIDD * VDD
(6)
Resistive Output Load Power (PLOAD):
PRLOAD = [(PDCL * VOL * I OL ) + (PDCH * (V DD − VOH ) * I OH
)]
(7)
Dynamic Power per Switching Receiver (PDYNR):
( (
)) (
PDYNR = C PD VDD * f + C L (VOH (actual ) − VOL (actual ) ) * f
2
2
)
(8)
Total Receiver Power (PTOTALR):
PTOTALR = PSTR + ( N O (PDYNR + PRLOAD ))
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Table 11. LVDS Driver/Receiver DC Electrical Parameters 1,2
LVDS Part ID
UT54LVDS031
UT54LVDS032
UT54LVDSC031
UT54LVDSC032
UT54LVDS031LV/E
UT54LVDS032LV/E
UT54LVDS032LVT
UT54LVDM031LV
UT54LVDM055LV3
CLT
IOD
f (max)
20pF
40pF
20pF
40pF
20pF
40pF
40pF
20pF
20pF
40pF
3.5mA
-3.5mA
-3.5mA
-3.5mA
10mA
10mA
--
77.7MHz
77.7MHz
77.7MHz
77.7MHz
200MHz
200MHz
200MHz
200MHz
200MHz
200MHz
VOL4
0.90V
0.3V
0.90V
0.3V
0.925V
0.25V
0.25V
0.855V
0.855V
0.25V
VOH4
1.60V
4.0V
1.60V
4.0V
1.650V
2.7V
2.7V
1.750V
1.750V
2.7V
IOH4
--0.4mA
--0.4mA
--0.4mA
----0.4mA
IOL4
-2.0mA
-2.0mA
-2.0mA
---2.0mA
Notes:
1. All values are typical unless otherwise noted.
2. The top line contains specifications for the Driver, the bottom line for the Receiver.
3. Values are per the datasheet DC electrical characteristics.
4.0 Example Calculations
The following sections walk the designer through two example calculations using the data and
equations presented in sections 2.0 and 3.0 above.
4.1 Example 3
The UT54LVDS031LV analysis assumes utilization of 2 driver channels switching at
170MHz with 50pF capacitive loads at 25°C.
UT54LVDS031LV Driver Power
V DD = 3.3V
N SWDP = 2
C L = 50 pF
AIDD( slope) = 0.028mA/MHz
SIDD = 15.0mA (Table 2)
VOD = 0.340V
I OD = .0035 A
f = 170 MHz
C PD = 6.81 pF (Table 2)
Static Device Power (PSTD):
Using equation (3):
PSTD = SIDD * VDD = 15.0mA * 3.3V = 49.5 mW
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Dynamic Power per Active Driver (PDYND):
(( (
))
)
PDYND = C PD VDD * f + (C L (VDD * VOD ) * f ) =
((6.81 pF (3.3V
2
))
)
*170MHz + (50 pF (3.3V * 0.340V ) * 170 MHz ) =
12.61mW + 9.53mW = 22.14mW
2
Total Device Power Dissipation (PTOTALD):
2 switching differential outputs:
PTOTALD = PSTD + ( N SWDP (PDYND )) = 49.56mW + (2(22.14mW )) = 93.78mW
Quickly comparing the measured data from table 2 using Joule’s Law (P=I*V):
I = ( AIDD( slope) * f * N SWDP ) + SIDD = (0.028mA / MHz * 170 MHz * 2 ) + 15.0mA = 24.52mA
2 switching differential outputs:
P = I * V = 24.52mA * 3.3V = 80.92mW
If example 4 were recalculated using a CL of 20pF, a result of 82.34mW is obtained.
Therefore, the CPD form of the power calculation is within 2% of the Joule’s Law form.
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4.1 Example 4
The UT54LVDS032 analysis assumes utilization of all 4 receivers switching at 40MHz
(50/50 duty cycle), with a 20pF capacitive load, and a 2.35kΩ pull up on the CMOS
output, at -55°C. A pull up resistor is present on the CMOS output of the receiver to pull
up the output of the receiver if the enable signals disable and Z state the outputs (EN = L
and /EN = H). In practice the bias resistor will be defined by the system designer.
V DD = 5.0V
C L = 20 pF
C PD = 21.12 pF (Table 8)
NO = 4
PDCL = 0.5
PDCH = 0.5
f = 40 MHz
VOH (actual ) = 5.0V
VOL (actual ) = VDD − (2.35kΩ * I OH ) = 5.0V − 4.7V = 0.3V
at I OL = 2.0mA
Static Device Power (PSTR):
PSTR = SIDD * VDD = 8.0mA * 5.0V = 40.0mW
Dynamic Power per Switching Receiver (PDYNR):
( (
)) (
)
PDYNR = C PD V DD * f + C L (VOH (actual ) − VOL (actual ) ) * f =
(21.12 pF (5.0V
2
2
)) (
)
* 40 MHz + 20 pF (5.0V − 0.3V ) * 40 MHz =
21.1mW + 17.7mW = 38.79mW
2
2
Resistive Output Load Power (PLOAD):
PRLOAD = [(PDCL * VOL * I OL ) + (PDCH * (VDD − VOH ) * I OH
)] =
[(0.5 * 0.3V * 2.0mA) + (0.5 * (5.0V − 5.0V ) * 0.4mA)] = 0.3mW + 0 = 0.3mW
Total Device Power (PTOTALR):
PTOTALRm = PSTR + ( N O (PDYNR + PRLOAD )) =
= 40.0mW + (4(38.79mW + 0.3mW )) = 196.37mW
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Quickly comparing this to Joule’s Law (P=I*V):
4 switching outputs:
I = (( AIDD( slope) ) * f * N O ) + SIDD = (0.304mA / MHz * 40 MHz * 4 ) + 8.0mA = 56.64mA
P = I * V = 56.64mA * 5.0V = 283.2mW
for 4 outputs switching
If example 5 were recalculated using a CL of 40pF, a result of 267.06mW is obtained.
Therefore, the CPD form of the power calculation is within 6% of the Joule’s Law form.
5.0 Conclusion
This application note empowers the designer to more accurately determine the power
dissipation of Aeroflex’s LVDS products as implemented in the user’s application. The
calculations described in the above sections employ application specific variables such as
load capacitance, frequency, DC loading, etc that contribute to overall power dissipation.
With accurate power dissipation improved power supply selection and thermal
management schemes can be designed.
6.0 Additional Comments
Data contained in this application note is NOT GUARANTEED. The data is intended to
provide system designers with better estimate of LVDS driver and receiver power
dissipation.
To optimize power conservation tie unused driver inputs either high (VDD) or low (VSS),
and leave unused outputs unconnected (no termination resistor connected, RT).
Leave unused receiver inputs floating, the unused input pins should be floated near the
pin on the receiver device. There is a fail safe mode on the Aeroflex LVDS receivers that
force the outputs to a high state. Unused receiver inputs should not be connected to noise
sources. Do not connect unused receiver input pins to a floating cable or trace because
they will act as a noise antenna. Unused receiver outputs should be left unconnected to
further power conservation.
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