19-2274; Rev 0; 1/02 Dual LVDS Line Receiver Features ♦ Pin Compatible with SN65LVDS9637 ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs ♦ Conforms to ANSI TIA/EIA-644 Standard ♦ Single 3.3V Supply ♦ Designed for Data Rates up to 400Mbps ♦ ±100mV (max) Differential Input Threshold ♦ 2.2ns (typ) Propagation Delay ♦ 41mW (typ) Power Dissipation per Receiver at 200MHz ♦ ±8kV ESD Protection for LVDS Inputs ♦ Low-Voltage TTL (LVTTL) Logic Output Levels Applications Network Switches/Routers Telecom Switching Equipment Cellular Phone Base Stations Ordering Information Digital Copiers LCD Displays PART Backplane Interconnect MAX9159ESA TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 SO Clock Distribution Pin Configuration Typical Operating Circuit TOP VIEW 3.3V 3.3V 0.001µF 0.001µF 0.1µF 0.1µF VCC 1 MAX9159 8 1A _A DIN_ RT = 100Ω DRIVER LVDS MAX9110 MAX9112 RECEIVER 1Y 2 7 1B 2Y 3 6 2A GND 4 5 2B _Y _B MAX9159 SO ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9159 General Description The MAX9159 dual low-voltage differential signaling (LVDS) receiver is ideal for applications requiring high speed, low power, and low noise. The MAX9159 is pin compatible with the SN65LVDS9637. The MAX9159 conforms to the ANSI TIA/EIA-644 LVDS standard and converts LVDS to LVTTL-compatible outputs. A fail-safe feature sets the output high when the inputs are undriven and open, terminated, or shorted. The MAX9159 is available in an 8-pin SO package and fully specified for the -40°C to +85°C extended temperature range. Refer to the MAX9111/MAX9113 data sheet for higher performance single/dual LVDS line receivers in SOT23 and SO packages. Refer to the MAX9110/MAX9112 data sheet for single/dual LVDS line drivers in SOT23 and SO packages. MAX9159 Dual LVDS Line Receiver ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.5V to +4V 1A, 1B, 2A, 2B to GND ............................................-0.5V to +4V Y1, Y2 to GND ............................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation ................................(TA = +70°C) 8-Pin SO (derate 5.88mW/°C above +70°C)................471mW Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C ESD Protection LVDS Inputs (1A, 1B, 2A, 2B) Human Body Model ........................................................±8kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 0.6V, common-mode input voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 100 mV LVDS INPUTS (1A, 1B, 2A, 2B) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current Input Current with Differential Input II IID Power-Off Input Current II(OFF) Power-Off Input Current with Differential Input IID(OFF) -100 mV VIN = 0 -1.0 -2.3 VIN = 2.4V -0.3 -0.67 0.1V ≤ |VID| ≤ 0.6V; _A or _B inputs -20 _A or _B inputs VCC = 0, VIN = 3.6V; _A or _B inputs 0.1V ≤ |VID| ≤ 0.6V, VCC = 0; _A or _B inputs 2.3 -15 -20 µA 20 µA 20 µA 15 µA Input Resistor 1 RIN1 VCC = 0 or 3.6V, Figure 1 35 kΩ Input Resistor 2 RIN2 VCC = 0 or 3.6V, Figure 1 157 kΩ IOH = -8mA 2.4 3.14 IOH = -4mA 2.8 3.2 LVTTL OUTPUTS (Y1, Y2) Output High Voltage VOH Output Low Voltage VOL IOL = 8mA 0.19 0.4 V ICC No load 5.7 10 mA V SUPPLY Supply Current 2 _______________________________________________________________________________________ Dual LVDS Line Receiver (VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 0.6V, common-mode input voltage VCM = |VID/2| to 2.4V - |VID/2|, CL = 10pF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) (Figures 2 and 3) (Notes 3, 4, PARAMETER SYMBOL Propagation Delay High to Low Propagation Delay Low to High MIN TYP MAX UNITS tPHL CONDITIONS 1.5 2.2 3 ns tPLH 1.5 2.13 3 ns Pulse Skew | tPHL - tPLH | tSK(P) 0.07 0.4 ns Channel-to-Channel Output Skew (Note 6) tSK(O) 0.03 0.3 ns Part-to-Part Skew (Note 7) tSK(PP) 1 ns Output Signal Rise Time (20% to 80%) tR 0.40 0.8 ns Output Signal Fall Time (80% to 20%) tF 0.42 0.8 ns Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground, except VTH, VTL, and VID. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: All input pulses are supplied by a generator having the following characteristics: tR or tF ≤ 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ±0.2ns. Note 6: tSK(O) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Note 7: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. Typical Operating Characteristics (VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 10pF, TA = +25°C, unless otherwise noted.) OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE OUTPUT HIGH VOLTAGE (V) 195 190 185 180 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 OUTPUT SOURCING 8mA 100 MAX9159 toc03 OUTPUT LOW VOLTAGE (mV) OUTPUT SINKING 8mA SHORT-CIRCUIT CURRENT (mA) MAX9159 toc01 200 OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE MAX9159 toc02 OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 90 80 70 60 50 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3 MAX9159 SWITCHING CHARACTERISTICS Typical Operating Characteristics (continued) (VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 10pF, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. FREQUENCY SUPPLY CURRENT (mA) -1.0 -1.5 -2.0 -2.5 VTH -3.0 VTL -3.5 35 30 25 TWO CHANNELS SWITCHING 20 15 ONE CHANNEL SWITCHING 10 6 5 4 5 -4.5 0 3.2 3.3 3.4 3.5 0.01 3.6 0.1 1 10 100 3 1000 -40 PROPAGATION DELAY vs. SUPPLY VOLTAGE 2.4 PROPAGATION DELAY (ns) tPHL 2.2 tPLH 2.1 2.3 2.2 tPHL 2.1 125 tPLH 2.0 3.2 3.3 3.4 3.5 3.6 75 50 -40 -15 10 35 60 0 3.0 85 3.1 3.2 3.3 3.4 3.5 TEMPERATURE (°C) SUPPLY VOLTAGE (V) PULSE SKEW vs. TEMPERATURE PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 70 60 50 40 2.4 2.3 tPHL tPLH 2.2 2.1 30 -15 10 35 TEMPERATURE (°C) 60 85 MAX9159 toc12 3.6 2.4 2.3 tPHL 2.2 tPLH 2.1 2.0 20 2.5 PROPAGATION DELAY (ns) 2.5 PROPAGATION DELAY (ns) 80 2.6 MAX9159 toc11 2.6 MAX9159 toc10 90 -40 100 SUPPLY VOLTAGE (V) 100 85 25 1.8 3.1 60 PULSE SKEW vs. SUPPLY VOLTAGE 1.9 2.0 35 150 MAX9159 toc08 2.5 MAX9159 toc07 2.3 10 TEMPERATURE (°C) PROPAGATION DELAY vs. TEMPERATURE 2.4 3.0 -15 FREQUENCY (MHz) SUPPLY VOLTAGE (V) MAX9159 toc09 3.1 PULSE SKEW (ps) 3.0 4 fIN = 1MHz BOTH CHANNELS SWITCHING 7 -4.0 -5.0 PROPAGATION DELAY (ns) 8 SUPPLY CURRENT (mA) -0.5 SUPPLY CURRENT vs. TEMPERATURE MAX9159 toc05 40 MAX9159 toc04 DIFFERENTIAL INPUT THRESHOLD (mV) 0 MAX9159 toc06 DIFFERENTIAL INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE PULSE SKEW (ps) MAX9159 Dual LVDS Line Receiver 2.0 0 500 1000 1500 2000 DIFFERENTIAL INPUT VOLTAGE (mV) 2500 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V) _______________________________________________________________________________________ 3.0 Dual LVDS Line Receiver PROPAGATION DELAY vs. LOAD CAPACITANCE 3.4 tF 0.4 tR 0.3 3.2 3.0 tPHL 2.8 2.6 tPLH 2.4 -15 10 35 60 85 1.6 1.4 tF 1.2 tR 1.0 0.8 0.6 0.2 2.0 -40 1.8 0.4 2.2 0.2 2.0 TRANSITION TIME (ns) 0.5 2.2 MAX9159 toc14 MAX9159 toc13 3.6 PROPAGATION DELAY (ns) TRANSITION TIME (ns) 0.6 TRANSITION TIME vs. LOAD CAPACITANCE MAX9159 toc15 TRANSITION TIME vs. TEMPERATURE 0 10 15 20 25 30 35 40 LOAD CAPACITANCE (pF) TEMPERATURE (°C) Pin Description PIN NAME 1 VCC FUNCTION 2 1Y Channel 1 Output 3 2Y Channel 2 Output 4 GND 5 2B Channel 2 Inverting Differential Input 6 2A Channel 2 Noninverting Differential Input 7 1B Channel 1 Inverting Differential Input 8 1A Channel 1 Noninverting Differential Input Power Supply Ground Detailed Description LVDS is intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9159 is a dual LVDS line receiver ideal for applications requiring high data rates, low power, and low noise. The device accepts an LVDS input and translates it to an LVTTL output. The receiver detects differential signals as low as 100mV and as high as 0.6V within an input voltage range of 0 to 2.4V. 45 50 10 15 20 25 30 35 40 45 50 LOAD CAPACITANCE (pF) The 250mV to 450mV differential output of an LVDS driver is nominally centered around a 1.25V offset. This offset, coupled with the receiver’s 0 to 2.4V input voltage range, allows an approximate ±1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the driver and the receiver, the common-mode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to 2.4V referenced to receiver ground. Fail-Safe The fail-safe feature of the MAX9159 sets the output high and reduces supply current when: • Inputs are open. • Inputs are undriven and shorted. • Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the input may switch the receiver and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when an LVDS driver output is in high impedance. A short condition can occur because of a cable failure. The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not acti- _______________________________________________________________________________________ 5 MAX9159 Typical Operating Characteristics (continued) (VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 10pF, TA = +25°C, unless otherwise noted.) MAX9159 Dual LVDS Line Receiver Board Layout vated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the failsafe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high. For LVDS applications, use a four-layer PC board with separate layers for power, ground, and input/output. To minimize crosstalk, do not run the output in parallel with the inputs. Applications Information Chip Information Power-Supply Bypassing Bypass VCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the device. TRANSISTOR COUNT: 461 PROCESS: CMOS VCC Differential Traces Input trace characteristics affect the performance of the MAX9159. Use controlled-impedance PC board traces, typically 100Ω. Match the termination resistor to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Input differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. RIN2 _A _Y RIN1 Termination In point-to-point connections, the MAX9159 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance is typically 100Ω, but may range between 90Ω to 132Ω, depending on the characteristic impedance of the transmission medium. When using the MAX9159, minimize the distance between the input termination resistor and the MAX9159 inputs. Use 1% surface-mount resistors. MAX9159 _B GND Figure 1. Input Fail-Safe Network _A PULSE GENERATOR Cables and Connectors Transmission media should typically have a controlled differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. VCC - 0.3V RIN1 _Y _B CL MAX9159 *50Ω *50Ω *50Ω REQUIRED FOR PULSE GENERATOR. Figure 2. Propagation Delay and Transition-Time Test Circuit 1.4V V_B VID VID = 0 VID = 0 1V V_A tPHL tPLH 80% V_Y VOH 80% 1.4V 1.4V 20% 20% tR VOL tF COMMON-MODE VOLTAGE: VCM = (V_A + V_B) / 2 DIFFERENTIAL INPUT VOLTAGE: VID = (V_A) - (V_B) Figure 3. Propagation Delay and Transition-Time Waveforms 6 _______________________________________________________________________________________ Dual LVDS Line Receiver SOICN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9159 Package Information