Z9974 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Features • • • • • • • • • • The Z9974 integrates PLL technology for zero delay propagation from input to output. The PLL feedback is externally available for propagation delay tuning and divide ratio alternatives as per Table 1. Output Frequency up to 125 MHz Supports PowerPC®, and Pentium® processors 15 Clock outputs: frequency configurable Two Reference clock inputs for dynamic toggling Output Three-State control Spread spectrum compatible 3.3V power supply Pin compatible with MPC974 Industrial temperature range: –40°C to +85°C 52-pin TQFP package The Z9974 has three banks of outputs with independent divider stages. These dividers allow the banks to have different frequencies as per Table 2. TCLK0 and TCLK1 are selectable input reference clocks and may be toggled dynamically during operation to provide modulation and phase shifting designs. This device includes a Master Reset signal, which disables the outputs (Hi-Z) mode, and reset all internal digital circuitry (excluding the PLL). Description The Z9974 is a low-cost 3.3V zero delay clock driver for high-speed signal buffering and redistribution. An Output Enable, OE, input pin is available for disabling the Qa(0:4), Qb(0:4), and Qc(0:3) outputs and forcing them to LOW state. All outputs are held LOW with input clock turned off. The designer can select various Input/Output Frequency by setting fsela, fselb, fselc, fselFB(0:1), and VCO_Sel. VDDc QC1 VSSc QC2 VDDc Qc3 VSSc NC VDDb Qb0 VCO_Sel VSSc QC0 Pin Configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 VSSA MR# OE fselb fselc PLL_EN fsela TClk_Sel TClk0 TClk1 NC VDDI VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 Z9974 39 38 37 36 35 34 33 32 31 30 29 28 27 VSSb QB1 VDDb Qb2 VSSb Qb3 VDDb Qb4 FB_IN VSSFB QFB VDDFB NC Cypress Semiconductor Corporation Document #: 38-07090 Rev. *C • VDDa Qa3 VSSa selFB1 Qa2 VDDa Qa1 VSSa Qa0 VDDa selFB0 VSSI Qa4 14 15 16 17 18 19 20 21 22 23 24 25 26 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 21, 2002 Z9974 Block Diagram fsela 0 250K A AND Gate B 1 TCLK_sel Y 5 5 Qa(0:4) AND Gate Y 5 5 Qb(0:4) AND Gate Y 4 4 Qc(0:3) 1 QFB 5 250K VDD 0 250K TCLK0 B 0 Ref-in 1 TCLK1 A 1 PLL 0 VCO-out C 1 /2 /4 250K 0 1 5 C /2 /4 Reset# Feedback VDD Divide by 2&4 250K /6 0 Reset# 1 A B FB_In Divide by 2, 4 & 6 4 VDD 250K PLL_EN VCO_sel 0 0 250K C 1 /2 fselb 1 Reset# Div. by 2 250K fselc 250K fselFB1 250K fselFB0 250K VDD 250K OE VDD 250K MR# Table 1. Feedback Divider Selection Inputs Output VCO_Sel fselFB0 fselFB1 QFB 0 0 0 VCO/8 0 0 1 VCO/12 0 1 0 VCO/16 0 1 1 VCO/24 1 0 0 VCO/16 1 0 1 VCO/24 1 1 0 VCO/32 1 1 1 VCO/48 Table 2. Output Divider Selection VCO_Sel fsela Qa fselb Qb fselC Qc 0 0 VCO/4 0 VCO/4 0 VCO/8 0 1 VCO/8 1 VCO/8 1 VCO/12 1 0 VCO/8 0 VCO/8 0 VCO/16 1 1 VCO/16 1 VCO/16 1 VCO/24 Document #: 38-07090 Rev. *C Page 2 of 7 Z9974 Pin Description[1] Pin Name PWR I/O Description 2 MR# I Master Reset pin. Active LOW. It has a 250-KΩ internal pull-up. When forced LOW, all outputs are three-stated (high impedance) and internal dividers are reset. 3 OE I Output Enable pin. Active LOW. It has a 250-KΩ internal pull-up. When forced LOW, Qa(0:4), Qb(0:4), and Qc(0:3) outputs are stopped in a LOW state. QFB is not affected by this control signal. 7, 5, 4 fsel(a,b, c) I Input select pins for setting the output dividers of Qa(0:4), Qb(0:4), and Qc(0:3) respectively. Each pin has an internal 250-KΩ pull-down. See Table 2 for output divide ratios. 6 PLL_EN I Input pin for bypassing the PLL. It has an internal 250-KΩ pull-up. When forced LOW, the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL and drives the dividers, typically for device testing. 8 TCLK_sel I Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel = 0, TCLK0 is selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a 250-kΩ internal pull-down. 9,10 TCLK(0:1) I Input pins for applying a reference clock to the PLL. The active input is selected by TCLK_sel, pin# 8. TCLK0 has a 250-KΩ internal pull-down. TCLK1 has a 250-KΩ internal pull-up. 14,20 fselFB(0:1) I Input select pins for setting the Feedback divide ratio at QFB output, pin #29. See Table 1. Each of these pins has a 250-KΩ internal pull-down. 16,18,21,23, Qa(0:4) 25 VDDa O High-drive, low-voltage CMOS, output clock buffers, Bank Qa. Their divide ratio is programmed by fsela, pin #7. 29 QFB VDDFB O Low-voltage CMOS output feedback clock to the internal PLL. The divide ratio for this output is set by fselFB(0:1). A delay capacitor or trace may be applied to this pin in order to control the Input Reference/Output Banks phase relationship. 31 FB_In I Feedback input pin. Typically connects to the QFB output for accessing the feedback to the PLL. It has a 250-kΩ internal pull-up. 32,34,36,48, Qb(0:4) 40 VDDb O High-drive, low-voltage CMOS, output clock buffers, Bank Qb. Their divide ratio is programmed by fselb, pin #4. 44,46,48,50 Qc(0:3) VDDc O High-drive, low-voltage CMOS, output clock buffers, Bank Qc. Their divide ratio is programmed by fselc, pin #5. 52 VCO_Sel I Input select pin for setting the divider of the VCO output. It has a 250-kΩ internal pull-down. If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL VCO output is divided by 4. See Table 1 and Table 2. 11,27,42 n/c - These pins are not connected internally. They may be attached to a ground plane. 12 VDDI P Power for input logic circuitry. 15 VSSI P Ground for input logic circuitry. 13 VDDA P Power and Ground supply pins for internal analog circuitry. 17,22,26 VDDa P 3.3V supply for Qa(0:4) output bank, and fselFB1 input. 19,24 VSSa P Common ground for Qa(0:4) output bank, and fselFB1 input. 28 VDDFB P Power supply pin for QFB output and FB_In input pins and digital circuitry. 30 VSSFB P Ground supply pin for QFB output and FB_In input pins and digital circuitry. 33,37,41 VDDb P 3.3V supply for Qb(0:4) output bank. Note: 1. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductances of the traces. Document #: 38-07090 Rev. *C Page 3 of 7 Z9974 Pin Description[1] (continued) Pin Name PWR I/O Description 35,39 VSSb P Common ground for Qb(0:4) output bank. 45,49 VDDc P 3.3V supply for Qc(0:3) output bank and VCO_sel pin. 43,47,51 VSSc P Common ground for Qc(0:3) output bank and VCO_sel pin. 1 VSSA P Analog Ground Glitch-Free Output Frequency Transitions Customarily when zero delay buffers have their internal counters change “on the fly” their output clock periods will: 1. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed “on the fly” while it is operating: Fsela, Fselb, Fselc, and VCO_Sel 2. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. Document #: 38-07090 Rev. *C Page 4 of 7 Z9974 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Storage Temperature: ................................ –65°C to + 150°C precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: ................................ –40°C to +85°C VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VDD:............. VDD + 0.3V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, DC Parameters VDD = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V IIL Input Low Current –100 µA IIH Input High Current 100 µA VOL Output Low Voltage IOL = 20 mA 0.5 V VOH Output High Voltage IOH = –20 mA IDDQ Quiescent Supply Current Cin Input Capacitance 2.4 V 20 mA per input 8 pF Max. Unit 10 ms 500 MHz 3 ns AC Parameters[3] VDD = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. TLOCK Maximum PLL Lock Time Stable power supply & valid clocks presented on TCLK(0:1) pins FVCO VCO Lock Range FselFB(0:1)=/4 to /12 Tinr,Tinf TCLK(0:1) Input Rise/Fall Time FREF Input Reference Frequency Note 4 Note 4 MHz FREFpw Input Reference Duty Cycle Note 4 Note 4 % Tpw Output Duty Cycle Measured at VDD/2 Tcycle/2 + 800 ps Tr,Tf Rise Time/Fall Time Measured between 0.8V and 2.0V 1.5 ns Zo Output Impedance 10 Ω 250 ps 100 ps 200 Tcycle/2 – 800 Tcycle/2 ± 500 0.15 7 Ts Output to Output Skew All outputs equally loaded Tpd Propagation Delay, TCLK(0:1) to FBIN Measured at 50 MHz, VDD/2 Tj Cycle to Cycle Jitter Measured at 50 MHz, VDD/2 TPLZ, TPHZ Output Disable Time After MR# goes LOW 2 10 ns TPZL Output Enable Time After MR# goes HIGH 2 10 ns Fout Maximum Output Frequency Q (/2) 125 MHz Q (/4) 62 Q (/6) 41 –250 ±100 ps Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Z9974 outputs can drive series or parallel terminator 50Ω (or 50Ω to VDD/2). 4. Input Reference Frequency is limited by the divider selection and the VCO lock range. Document #: 38-07090 Rev. *C Page 5 of 7 Z9974 Test Circuit Diagram VDD* 1K Ω Output under Test 43 Ω 50 Ω Impedance PROBE 7Ω 1K Ω Note: All buffer outputs are tied to a common 3.3-Volt VDD (VDD*) for testing purposes Ordering Information Part Number Package Type Production Flow IMIZ9974CA 52-pin TQFP Industrial, –40°C to +85°C IMIZ9974CAT 52-pin TQFP–Tape and Reel Industrial, –40°C to +85°C Package Drawing and Dimensions 52-Lead Thin Plastic Quad Flat Pack (10x10x1.4 mm) A52 51-85131-** PowerPC is a registered trademark of International Business Machines. Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07090 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.. Z9974 Document Title: Z9974 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Document #: 38-07090 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107126 06/05/01 IKA Converted to IMI Cypress Spec *A 108068 07/03/01 NDP Changed Commercial to Industrial *B 116195 08/14/02 ITH Converted from Word to Framemaker Corrected TCLK0 & TCLK1 on schematic to match the Pull-up/down in the pin description Corrected PLL_EN in the pin description. Corrected the package drawing and dimension *C 122775 12/21/02 RBI Add power up requirements to maximum ratings information. Document #: 38-07090 Rev. *C Page 7 of 7