PRELIMINARY
SFP95N03L
SemiWell Semiconductor
Logic N-Channel MOSFET
Features
Symbol
■
Low RDS(on) (0.0085Ω )@VGS=10V
■
Low Gate Charge (Typical 39nC)
Low Crss (Typical 185pF)
Improved dv/dt Capability
100% Avalanche Tested
Maximum Junction Temperature Range (175°C)
■
■
■
■
{
2. Drain
●
◀
1. Gate
{
▲
●
●
{
General Description
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a low
gate charge with superior switching performance, and rugged
avalanche characteristics. This Power MOSFET is well suited
for synchronous DC-DC Converters and Power Management in
portable and battery operated products.
3. Source
TO-220
1 2
3
Absolute Maximum Ratings
Symbol
VDSS
ID
Parameter
Drain to Source Voltage
Continuous Drain Current(@TC = 25°C)
(Note 6)
Continuous Drain Current(@TC = 100°C)
IDM
Drain Current Pulsed
VGS
Gate to Source Voltage
(Note 1)
Value
Units
30
V
95
A
67.3
A
380
A
±20
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
450
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
7.0
V/ns
150
W
PD
TSTG, TJ
TL
Total Power Dissipation(@TC = 25 °C)
Derating Factor above 25 °C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
1.0
W/°C
- 55 ~ 175
°C
300
°C
Thermal Characteristics
Symbol
Parameter
Value
Min.
Typ.
Max.
Units
RθJC
Thermal Resistance, Junction-to-Case
-
-
1.0
°C/W
RθCS
Thermal Resistance, Case to Sink
-
0.5
-
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
-
-
62.5
°C/W
1/7
September, 2002. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Electrical Characteristics
Symbol
( TC = 25 °C unless otherwise noted )
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250uA
Δ BVDSS/
Δ TJ
Breakdown Voltage Temperature
coefficient
ID = 250uA, referenced to 25 °C
-
0.023
-
V/°C
IDSS
Drain-Source Leakage Current
VDS = 30V, VGS = 0V
-
-
1
uA
VDS = 24V, TC = 150 °C
-
-
10
uA
Gate-Source Leakage, Forward
VGS = 20V, VDS = 0V
-
-
100
nA
Gate-Source Leakage, Reverse
VGS = -20V, VDS = 0V
-
-
-100
nA
IGSS
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250uA
1.0
-
3.0
V
RDS(ON)
Static Drain-Source On-state Resistance
VGS =10 V, ID = 47.5A
VGS =5 V, ID = 47.5A
-
0.0065
0.0085
0.0085
0.0115
Ω
Dynamic Characteristics
Ciss
Input Capacitance
-
1015
1320
Coss
Output Capacitance
-
845
1110
Crss
Reverse Transfer Capacitance
-
185
240
-
45
100
-
165
340
-
70
150
-
140
290
-
39
51
-
13
-
-
18
-
Min.
Typ.
Max.
VGS =0 V, VDS =25V, f = 1MHz
pF
Dynamic Characteristics
td(on)
tr
td(off)
tf
Turn-on Delay Time
VDD =15V, ID =95A, RG =50Ω
Rise Time
Turn-off Delay Time
※ see fig. 13.
Fall Time
(Note 4, 5)
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS =24V, VGS =5V, ID =95A
Qgd
Gate-Drain Charge(Miller Charge)
※ see fig. 12.
(Note 4, 5)
ns
nC
Source-Drain Diode Ratings and Characteristics
Symbol
Parameter
Test Conditions
Unit.
IS
Continuous Source Current
-
95
Pulsed source Current
Integral Reverse p-n Junction
Diode in the MOSFET
-
ISM
-
-
380
A
VSD
Diode Forward Voltage
IS =95A, VGS =0V
-
-
1.5
V
trr
Reverse Recovery Time
-
55
-
ns
Qrr
Reverse Recovery Charge
-
65
-
nC
IS=95A,VGS=0V,dIF/dt=100A/us
※ NOTES
1. Repeativity rating : pulse width limited by junction temperature
2. L = 50 uH, IAS =95A, VDD = 15V, RG = 0Ω , Starting TJ = 25°C
3. ISD ≤ 95A, di/dt ≤ 300A/us, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially independent of operating temperature.
6. Continuous Drain current calculated by maximum junction temperature ; limited by package
2/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig 1. On-State Characteristics
Fig 2. Transfer Characteristics
VGS
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
2
10
2
10
ID, Drain Current [A]
ID, Drain Current [A]
Top :
o
175 C
1
10
o
25 C
o
-55 C
0
10
※ Notes :
1. 250µ s Pulse Test
2. TC = 25℃
1
10
※ Notes :
1. VDS = 15V
2. 250µ s Pulse Test
-1
-1
0
10
10
1
10
10
0
2
4
6
8
10
12
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Fig 4. On State Current vs.
Allowable Case Temperature
Fig 3. On Resistance Variation vs.
Drain Current and Gate Voltage
2
15
10
IDR, Reverse Drain Current[A]
RDS(ON) [mΩ ],
Drain-Source On-Resistance
20
VGS = 5V
VGS = 10V
10
5
1
10
175℃
25℃
0
10
※ Notes :
1. VGS = 0V
2. 250µ s Pulse Test
※ Note : TJ = 25℃
0
-1
0
100
200
300
400
10
0.2
0.4
0.6
Fig 5. Capacitance Characteristics
1.0
1.2
1.4
1.8
Fig 6. Gate Charge Characteristics
4000
VGS, Gate-Source Voltage [V]
Ciss=Cgs+Cgd(Cds=shorted)
Coss=Cds+Cgd
Crss=Cgd
5000
※ Notes :
1. VGS = 0V
2. f=1MHz
3000
Ciss
2000
Coss
1000
VDS = 15V
10
VDS = 24V
8
6
4
2
※ Note : ID = 95 A
Crss
0
1.6
12
6000
Capacitance [pF]
0.8
VSD, Source-Drain voltage[V]
ID, Drain Current [A]
0
5
10
15
20
25
VDS, Drain-Source Voltage [V]
30
35
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
Qg, Total Gate Charge [nC]
3/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig 7. Breakdown Voltage Variation
Fig 8. On-Resistance Variation
3.0
RDS(ON), (Normalized)
Drain-Source On-Resistance
BVDSS, (Normalized)
Drain-Source Breakdown Voltage
1.2
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 µ A
0.9
0.8
-100
-50
0
50
100
150
2.5
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 47.5 A
0.5
0.0
-100
200
-50
0
50
100
150
200
150
175
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Fig 10. Maximum Drain Current
vs. Case Temperature
Fig 9. Maximum Safe Operating Area
100
3
10
Limited by Package
Operation in This Area
is Limited by R DS(on)
80
ID, Drain Current [A]
ID, Drain Current [A]
100 µs
1 ms
2
10
10 ms
DC
1
10
※ Notes :
60
40
20
o
1. TC = 25 C
o
2. TJ = 175 C
3. Single Pulse
0
10
-1
10
0
0
25
1
10
10
50
75
100
125
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
Fig 11. Transient Thermal Response Curve
Zθ JC(t), Thermal Response
10
0
D = 0 .5
0 .2
10
※ N o te s :
1 . Z θ JC(t) = 1 .0 ℃ /W M a x.
2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C(t)
0 .1
-1
0 .0 5
0 .0 2
0 .0 1
10
s in g le p u ls e
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
t 1 , S q u a re W a ve P u ls e D u ra tio n [s e c ]
4/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
0
10
1
SFP95N03L
Fig. 12. Gate Charge Test Circuit & Waveforms
50KΩ
12V
VGS
Same Type
as DUT
Qg
200nF
5V
300nF
VDS
VGS
Qgs
Qgd
DUT
1mA
Charge
Fig 13. Switching Time Test Circuit & Waveforms
RL
VDS
VDS
90%
VDD
( 0.5 rated V DS )
5V
Pulse
Generator
Vin
DUT
RG
10%
tr
td(on)
td(off)
t on
tf
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
VDS
VDD
ID
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
BVDSS
IAS
RG
10V
ID (t)
DUT
VDS (t)
VDD
tp
Time
5/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
Vf
Body Diode
Forward Voltage Drop
6/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
VDD
SFP95N03L
TO-220 Package Dimension
Dim.
mm
Typ.
Min.
9.7
6.3
9.0
12.8
1.2
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Max.
10.1
6.7
9.47
13.3
1.4
Inch
Typ.
Min.
0.382
0.248
0.354
0.504
0.047
1.7
2.5
0.067
0.098
3.0
1.25
2.4
5.0
2.2
1.42
0.45
1.17
3.4
1.4
2.7
5.15
2.6
1.62
0.6
1.37
Ø
0.118
0.049
0.094
0.197
0.087
0.056
0.018
0.046
0.134
0.055
0.106
0.203
0.102
0.064
0.024
0.054
3.6
E
B
0.142
H
A
φ
I
F
C
M
L
G
1
D
2
1. Gate
2. Drain
3. Source
3
J
Max.
0.398
0.264
0.373
0.524
0.055
N
O
K
7/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.