SFP840
SemiWell Semiconductor
N-Channel MOSFET
Features
■
■
■
■
■
■
Symbol
High ruggedness
RDS(on) (Max 0.85 Ω )@VGS=10V
{
2. Drain
●
Gate Charge (Typical 48nC)
Improved dv/dt Capability, High ruggedness
100% Avalanche Tested
Maximum Junction Temperature Range (150°C)
◀
1. Gate
{
▲
●
●
{
General Description
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a high
rugged avalanche characteristics. This devices is specially well
suited for half bridge and full bridge resonant topolgy like a
electronic lamp ballast.
3. Source
TO-220
1 2
3
Absolute Maximum Ratings
Symbol
VDSS
ID
Parameter
Value
Units
500
V
Continuous Drain Current(@TC = 25°C)
8
A
Continuous Drain Current(@TC = 100°C)
5.1
A
32
A
±30
V
Drain to Source Voltage
IDM
Drain Current Pulsed
VGS
Gate to Source Voltage
EAS
Single Pulsed Avalanche Energy
(Note 2)
660
mJ
EAR
Repetitive Avalanche Energy
(Note 1)
12.5
mJ
Peak Diode Recovery dv/dt
(Note 3)
dv/dt
PD
TSTG, TJ
TL
(Note 1)
Total Power Dissipation(@TC = 25 °C)
Derating Factor above 25 °C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
5
V/ns
125
W
1.0
W/°C
- 55 ~ 150
°C
300
°C
Thermal Characteristics
Symbol
Parameter
Value
Min.
Typ.
Max.
Units
RθJC
Thermal Resistance, Junction-to-Case
-
-
1
RθCS
Thermal Resistance, Case to Sink
-
0.5
-
°C/W
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
-
-
62
°C/W
1/7
May, 2003. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP840
Electrical Characteristics
Symbol
( TC = 25 °C unless otherwise noted )
Parameter
Test Conditions
Min
Typ
Max
Units
500
-
-
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250uA
Δ BVDSS/
Δ TJ
Breakdown Voltage Temperature
coefficient
ID = 250uA, referenced to 25 °C
-
0.6
-
V/°C
IDSS
Drain-Source Leakage Current
VDS = 500V, VGS = 0V
-
-
1
uA
IGSS
VDS = 400V, TC = 125 °C
-
-
10
uA
Gate-Source Leakage, Forward
VGS = 30V, VDS = 0V
-
-
100
nA
Gate-source Leakage, Reverse
VGS = -30V, VDS = 0V
-
-
-100
nA
2.0
-
4.0
V
-
-
0.85
Ω
-
1470
-
-
170
-
-
40
-
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250uA
RDS(ON)
Static Drain-Source On-state Resistance
VGS =10 V, ID = 4A
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VGS =0 V, VDS =25V, f = 1MHz
pF
Dynamic Characteristics
td(on)
tr
td(off)
tf
Turn-on Delay Time
VDD =250V, ID =8A, RG =50Ω
Rise Time
Turn-off Delay Time
Fall Time
※ see fig. 13.
(Note 4, 5)
-
22
-
-
25
-
-
130
-
-
30
-
-
48
60
ns
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS =400V, VGS =10V, ID =8A
-
7
-
Qgd
Gate-Drain Charge(Miller Charge)
※ see fig. 12.
-
20
-
Min.
Typ.
Max.
-
-
8
-
-
32
IS =8A, VGS =0V
-
-
2.0
-
335
-
ns
IS=8A, VGS=0V, dIF/dt=100A/us
-
3.6
-
uC
(Note 4, 5)
nC
Source-Drain Diode Ratings and Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
Pulsed Source Current
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Test Conditions
Integral Reverse p-n Junction
Diode in the MOSFET
※ NOTES
1. Repeativity rating : pulse width limited by junction temperature
2. L = 18.5mH, IAS =8A, VDD = 50V, RG = 0Ω , Starting TJ = 25°C
3. ISD ≤ 10A, di/dt ≤ 300A/us, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially independent of operating temperature.
2/7
Unit.
A
V
SFP840
Fig 1. On-State Characteristics
Fig 2. Transfer Characteristics
ID, Drain Current [A]
10
10
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
Bottom : 4.5V
ID, Drain Current [A]
Top :
1
0
10
1
o
25 C
o
150 C
10
0
o
-55 C
※ Notes :
1. VDS = 50V
2. 250µ s Pulse Test
10
-1
10
-1
10
0
10
10
1
-1
2
3
4
VDS, Drain-Source Voltage [V]
5
6
7
8
9
VGS, Gate-Source Voltage [V]
10
Fig 4. On State Current vs.
Allowable Case Temperature
Fig 3. On Resistance Variation vs.
Drain Current and Gate Voltage
IDR, Reverse Drain Current [A]
RDS(ON),
Drain-Source On-Resistance [Ω ]
1.8
1.6
1.4
VGS = 20V
VGS = 10V
1.2
1.0
0.8
10
1
10
0
0.4
※ Notes :
1. VGS = 0V
2. 250µ s Pulse Test
0
5
10
15
20
10
25
-1
0.2
0.4
VGS, Gate-Source Voltage [V]
※ Notes :
1. VGS = 0V
2. f=1MHz
2000
Ciss
1500
1000
500
0
Coss
Crss
0
5
10
1.0
1.2
1.4
1.6
12
Ciss=Cgs+Cgd(Cds=shorted)
Coss=Cds+Cgd
Crss=Cgd
2500
0.8
Fig 6. Gate Charge Characteristics
Fig 5. Capacitance Characteristics
3000
0.6
VSD, Source-Drain Voltage [V]
ID, Drain Current [A]
Capacitance [pF]
25℃
150℃
0.6
VDS = 400V
10
VDS = 250V
8
6
4
2
※ Note : ID = 8 A
15
20
25
30
VDS, Drain-Source Voltage [V]
35
40
0
0
10
20
30
40
50
60
QG, Total Gate Charge [nC]
3/7
SFP840
Fig 7. Breakdown Voltage Variation
Fig 8. On-Resistance Variation
3.0
RDS(on), (Normalized)
Drain-Source On-Resistance
BVDSS, (Normalized)
Drain-Source Breakdown Voltage
1.2
1.1
1.0
0.9
※ Notes :
1. VGS = 0 V
2. ID = 250 µ A
0.8
-100
-50
0
50
100
150
2.5
2.0
1.5
1.0
※ Notes :
1. V GS = 10 V
2. ID = 4 A
0.5
0.0
-100
200
-50
50
100
150
200
o
TJ, Junction Temperature [ C]
Fig 10. Maximum Drain Current
vs. Case Temperature
Fig 9. Maximum Safe Operating Area
8
2
10
Operation in This Area
is Limited by R DS(on)
6
100 µs
ID' Drain Current [A]
ID, Drain Current [A]
0
T J, Junction Temperature [ C]
o
1
10
1 ms
10 ms
DC
0
10
※ Notes :
o
1. TC = 25 C
4
2
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
10
1
2
10
0
25
3
10
10
50
75
100
TC' Case Temperature [ C]
Zθ JC(t), Thermal Response
Fig 11. Transient Thermal Response Curve
10
0
D = 0 .5
0 .2
10
※ N o te s :
1 . Z θ J C( t) = 1 ℃ /W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C(t)
0 .1
-1
0 .0 5
0 .0 2
0 .0 1
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
4/7
125
o
VDS, Drain-Source Voltage [V]
10
0
10
1
150
SFP840
Fig. 12. Gate Charge Test Circuit & Waveforms
VGS
Same Type
as DUT
50KΩ
200nF
12V
Qg
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
1mA
Charge
Fig 13. Switching Time Test Circuit & Waveforms
RL
VDS
VDS
90%
VDD
( 0.5 rated V DS )
10V
V
Pulse
Generator
Vin
DUT
RG
10%
tr
td(on)
td(off)
t on
tf
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
VDS
VDD
ID
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
BVDSS
IAS
RG
10V
ID (t)
DUT
VDS (t)
VDD
tp
Time
5/7
SFP840
Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
Vf
Body Diode
Forward Voltage Drop
6/7
VDD
SFP840
TO-220 Package Dimension
Dim.
mm
Typ.
Min.
9.7
6.3
9.0
12.8
1.2
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Max.
10.1
6.7
9.47
13.3
1.4
Inch
Typ.
Min.
0.382
0.248
0.354
0.504
0.047
1.7
2.5
0.067
0.098
3.0
1.25
2.4
5.0
2.2
1.25
0.45
0.6
3.4
1.4
2.7
5.15
2.6
1.55
0.6
1.0
0.118
0.049
0.094
0.197
0.087
0.049
0.018
0.024
0.134
0.055
0.106
0.203
0.102
0.061
0.024
0.039
3.6
Ø
E
B
0.142
H
A
φ
I
F
C
M
L
G
1
D
2
1. Gate
2. Drain
3. Source
3
J
N
K
7/7
Max.
0.398
0.264
0.373
0.524
0.055
O