www.fairchildsemi.com AN-6003 “Shoot-through” in Synchronous Buck Converters Jon Klein Power Management Applications Abstract The synchronous buck circuit is in widespread use to provide “point of use” high current, low voltage power for CPU’s, chipsets, peripherals etc. In the synchronous buck converter, the power stage has a “high-side” (Q1 below) MOSFET to charge the inductor, and a “Low-side” MOSFET which replaces a conventional buck regulator’s “catch diode” to provide a low-loss recirculation path for the inductor current. PWM CONTROLLER V IN H igh-S ide Q1 VO U T L1 2. Adaptive gate drive: This circuit looks at the VGS of the MOSFET that’s being driven off to determine when to turn on the complementary MOSFET. Theoretically, adaptive gate drives produce the shortest possible dead-time for a given MOSFET without producing shootthrough. In practice, a combination of adaptive and fixed produces the best results, and is typically what is in today’s PWM controllers and gate drivers as shown in Figure 2 D1 BOOT + C BO O T V IN – Low -S ide Q2 D C GD H D RV PW M Fixed “dead-time”: A MOSFET is turned off, then a fixed delay is provided before the lowside is turned on. This circuit is simple and usually effective, but suffers from its lack of flexibility if a wide range of MOSFET gate capacitances are to be used with a given controller. Too long a dead-time means high conduction losses. Too short a dead time can cause shoot-through. A fixed dead-time typically must err on the “too long” side to allow high CGS MOSFETs to fully discharge before turning on the complementary MOSFET. C GS S SW D elay Q1 D C GD LDR V PW M R G A TE G C GS S Q2 PG ND D elay + Shoot-through is defined as the condition when both MOSFETs are either fully or partially turned on, providing a path for current to “shoot through” from VIN to GND. To minimize shoot-through, synchronous buck regulator IC’s employ one of two techniques to ensure “break before make” operation of Q1 and Q2 to minimize shoot-through: R G A TE G 1V + Figure 1. Synchronous Buck output stage 1. +5 RG 1V Figure 2. Typical Adaptive Gate drive Even though there apparently is a “break before make” action by the controller, shoot-through can still occur when the High-side MOSFET turns on, due to Gate Step. Shoot-through is very difficult to measure directly. Shoot-through currents persist for only a few nS, hence the added inductance in a current probe drastically affects the shoot-through waveform. Shoot-through manifests itself typically as increased ringing, reduced efficiency, higher MOSFET temperatures (especially in Q1) and higher EMI. This paper will provide analytical techniques to predict shoot-through, and methods to reduce it. 04/25/2003 AN-6003 Shoot-through in Synchronous Buck Regulators “Gate Step” – The shootthrough culprit 6 If the adaptive circuits are working, then we shouldn’t see any shoot-through, right? 4 5 20 − TR V R •(C + C ) VSTEP(PK ) ≈ RT • CGD • IN • 1 − e T GD GS TR (1a) Where RT = RDRIVER + RGATE + RDAMPING (see Figure 5), and TR is the rise-time of the SW node. The limiting case is when TR = 0. Then CGD CGD + CGS (1b) This expression only illustrates the AC portion of the gate step. The gate step is injected onto whatever voltage the MOSFET’s gate has discharged to. For example, if the switch node rises when VGS = 1V, and the gate step amplitude is 2V, instantaneously there will be 3 VGS which is more than enough to have a high instantaneous current through both MOSFETs. It’s important, therefore that adaptive gate drive circuits allow sufficient delay to prevent the high side from turning on before the low-side VGS is discharged down to a few hundred mV. 15 LS MOSFET GATE 3 10 2 5 1 0 0 V VGS SW NODE VOLTAGE Not exactly. Most shoot-through occurs when the high-side MOSFET is turned on. The high dv/dT on the SW node (Drain of the low-side MOSFET) couples charge through CGD. This drives the gate positive at the very moment when the driver is trying to hold the gate low. CGD and CGS form a capacitive voltage divider, which attenuates the gate step such that the worst case peak amplitude of the gate step (VSTEP) seen is: VSTEP(MAX ) ≈ VIN • 25 -5 0 20 40 60 80 t (nS) Figure 4. Gate Step for VIN .=20V Further exacerbating the problem for adaptive circuits is the fact that the adaptive comparator is not actually sensing the voltage at the internal gate junction of the MOSFET. As seen in Figure 5, the internal MOSFET’s gate voltage has an unavoidable internal RGATE resistance. In addition, some designers like to have a “damping” resistor in series with the gates of MOSFETs that are located physically far away from their gate drives. This creates a bigger problem for the adaptive gate drive circuit. These series resistances form a voltage divider with the internal pull-down resistance of the low-side gate drive of the IC, causing it to think the gate voltage is lower than it really is when it decides to release the High-side driver. HDRV H.S. MOSFET D Delay CGD 1V LDRV RGATE G RDamping CGS RDRIVER S Q2 An illustration of gate step is seen below. 6 14 SW NODE VOLTAGE 10 4 8 LS MOSFET GATE 3 6 4 2 2 1 V VGS Figure 5. Resistance in the gate drive path attenuates the voltage at the MOSFET gate node. 12 5 When there is 1V at the pin of the IC, the internal MOSFET VGS is: VGS(I) = 1V RDRIVER ( • RDRIVER + R GATE + RDamping 0 0 -2 0 20 40 60 80 t (nS) Figure 3. Gate Step for VIN .=12V. 04/25/2003 Consider an example where: RDRIVER = 2Ω , RDAMPING = 5Ω RGATE = 1.2Ω 2 ) AN-6003 Shoot-through in Synchronous Buck Regulators When the adaptive gate circuit switches, the internal MOSFET gate voltage will be: 1V • (2 + 1.2 + 5)Ω = 4.1V 2Ω In this example, if there were no delay in the circuit, the HDRV would turn on when the low-side MOSFET has just begun to discharge, causing a very high shoot-through current. Much of the problem in the above circuit is the damping resistor. If a damping resistance is necessary, place a Schottky diode across the resistor (as shown below) to reduce the effect the damping resistor will have on the adaptive gate drive. HDRV H.S. MOSFET D Delay CGD RGATE 1V LDRV RDamping CGS S MOSFET characteristics can have a dramatic effect on how much shoot-through current can be induced by the gate step. The worst case for shoot-through is an infinitely fast (0 rise time) on the drain node. The amount of gate step is largely determined by the ration of CGS and CGD . Once the size of the gate step is determined (eq. 1 above), the peak magnitude of the shoot-through current can be calculated as : ( IPEAK (MAX) ≈ K • GM • VSTEP(MAX) − VTH(MIN) Q2 Figure 6. Schottky diode reduces damping resistor error in adaptive gate drive as RDRIVER or 2.1V for our example. A dramatic improvement. Furthermore, the Schottky reduces the duration of the shoot-through step, since only RGATE + RDRIVER will be discharging CGS, rather than the sum of RGATE + RDAMPING + RDRIVER . Table 1 below illustrates the performance improvement in our example with and without the Schottky diode: Comparator Flips @ VGS(INT) = VGS(INT) after 20nS delay VSTEP Peak Peak current Power Loss @ FSW=300KHz With Schottky 2.1 1.14 1.25 0.29 20 Conditions: Typical low-side MOSFET, 25nS delay from comparator sense to beginning of SW node rise, 19VIN, 10nS SW node rise time. Table 1 . Peak Currents with and without Schottky with RDAMPING = 5Ω . 04/25/2003 VTH(MIN) 0.8 • (RDRIVER + R GATE ) No Schottky 4.1 2.23 2.50 36 1100 VGS − VTH(MIN) 1.0 K (GM Multipler) 1V (2) where GM is the transconductance (in S, or A/V) given in the datasheet. While only a small percentage of MOSFETs exhibit VTH(MIN) at room temperature, VTH goes down with increasing junction temperature, therefore VTH(MIN) is a good proxy for the VTH at the operating junction temperature of the MOSFET. Subsequent calculations use VTH(MIN) for this reason. When using the schottky, the internal gate node will be at: VGS(I) = 0.5 + ) GM is not really a contstant, however, and its value is greatly reduced low enhancement voltages (VGS-VTH). In these calculations we use a factor "K" from the graph below, which is typical of GM with low values of enhancement. The X axis of Figure 7 is calculated G RDRIVER MOSFET Choices 0.6 0.4 0.2 0.0 0% 50% 100% 150% 200% 250% 300% Normalized Enhancement Voltage Figure 7 GM factor (K) V V V A mW Table 2 shows the relevant MOSFET characteristics which determine the maximum shoot-through current. MOSFET CGS CGD MOSFET1 MOSFET2 MOSFET3 MOSFET4 MOSFET5 3,514 5,070 4,942 3,888 6,324 307 230 315 401 281 Typical Min VTH VTH 1.6 1.2 1.6 1.6 1.15 1 0.8 1 1 0.6 GM 86 97 80 135 90 Table 2 . Low-Side MOSFET Characteristics 3 AN-6003 Shoot-through in Synchronous Buck Regulators Each of the MOSFETs represented is from a different process and has different ratios of internal capacitance. MOSFET MOSFET1 MOSFET2 MOSFET3 MOSFET4 MOSFET5 VSTEP(MAX) VTH(MIN) 1.53 0.82 1.14 1.78 0.81 1 0.8 1 1 0.6 VSTEP –VTH(MIN) 0.53 0.02 0.14 0.78 0.21 IPEAK (max) 0.31 0.02 0.07 16.37 0.13 Table 3. Maximum VSTEP and ISHOOTTHROUGH @ VIN = 19V and VGS(START) = 0V. Table 3 assumes that the VGS has dropped to 0 before the SW node rises when HDRV turns on. As demonstrated above, the smallest amplitude of VSTEP comes from MOSFET2 and MOSFET5, which are low-threshold devices. Low threshold in large part is due to a thin gate oxide, giving the MOSFET a high CGS ratio, which attenuates VSTEP. more than other CGD MOSFETs. Also, Table 3 only shows the theoretical peak current in Q2 due to the gate step. In a real converter, parasitic inductance limits the rise in current to 4A/nS. Even for the MOSFET4, the gate pulse only stays above threshold for about 5nS, so the shootthrough current would be further limited. An additional shortcoming of the simplified calculations of Table 3 is the assumption that SW node turn-on begins when VGS of the low-side is at 0. As we saw from the earlier discussion, this may not be the case. 04/25/2003 Reducing gate step by slowing down Q1 rise time Usually, designers attempt to achieve the fastest risetime possible on the High-Side MOSFET in order to minimize switching losses. A simplified expression for turn-on losses (P(TURN-ON)) for the high-side MOSFET is: PTURN − ON ≈ FSW • TR • VIN • IOUT 2 (3) where TR is the rise-time of the MOSFET. A very dV on SW) is desirable to fast rise-time (high dt minimize high-side power dissipation, but if it results in a large gate-step, causing shoot-through, the dissipation effect can be greater than the dissipation induced by slowing the rise time. In some situations this is the only practical approach to eliminate shootthrough. As can be seen in Figure 8, slowing down the rise time has a dramatic effect on the amplitude of VSTEP that is coupled into the Low-side MOSFET gate. TR slowdown has the added benefit of reducing EMI, but comes at a cost of efficiency loss . Figure 8 and subsequent tables were simulated with MOSFETs typical of those used in notebook PC’s (2 in parallel) with 15A output current and 19VIN. Figure 8 assumes that the SW node begins to rise when the internal gate node has discharged down to 0.5V. 4 AN-6003 Shoot-through in Synchronous Buck Regulators 2.0 1.8 MOSFET4 MOSFET1 MOSFET3 MOSFET5 MOSFET2 1.6 V(STEP) Peak 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 35 19V RiseTime(nS) Figure 8 . Effect of SW node rise-time on VSTEP VIN=19V, SW rise starts @ VGS(Q2) = 0.5V Table 4 shows the power loss due to shoot-through for each MOSFET. SW will rise when there is still a substantial VGS on Q2 as shown is Table 5. Slowing down Q1 can then be an effective strategy to reduce shoot-through losses. The major component of switching loss during Q1 turn-on is: PTURN−ON ≈ t R • FSW • VIN • IOUT 2 (3) and is computed in the right-most column for each rise-time in Table 4 for IOUT = 15A. TR(SW) 5 10 15 20 25 30 FET1 18 12 7 3 0 0 FET2 10 6 3 0 0 0 FET3 10 6 3 0 0 0 FET4 56 39 28 19 11 4 FET5 27 24 19 16 12 8 Q1 tR Loss 214 428 641 855 1,069 1,283 Table 4. Worst case (Min VTH) shoot-through power loss (mW) SW rise starts @ VGS(Q2) = 0.5V In most cases, the shoot-through is negligble, so slowing down high-side rise-time would not be a prudent choice, since the more power would be lost in slowing down the rise time than power saved by eliminating shoot-through. TR(SW) 5 10 15 20 25 30 FET1 90 30 23 16 8 0 FET2 62 31 26 21 16 11 FET3 29 24 18 13 7 1 FET4 380 127 61 50 39 25 FET5 551 266 58 54 51 47 Q1 tR Loss 214 428 641 855 1,069 1,283 Table 5. Worst case (Min VTH) shoot-through power loss (mW) SW rise starts @ VGS(Q2) = 1V This is typically achieved by adding resistance (RG in Figure 2) in series with CBOOT . An approximation for TR provides a good starting point for choosing a value of RG: ( TR ≈ C GS • RDRIVE(L − H) + RG ) (4) where RDRIVE(L-H) is the resistance of the IC’s high-side MOSFET gate driver when driving from low to high. If, the controller's gate drive starts to turn Q1 on before allowing the internal node of Q2 to discharge, 04/25/2003 5 AN-6003 Shoot-through in Synchronous Buck Regulators DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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