DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
Modern power electronics products require small size and lighter weight of power
electronics parts. Filter inductor and capacitor sizes must be small. With the small filter,
the switching semiconductor devices must have small switching loss. And heat sink also
must be reduced. For the safe operation with the small heat sink, the switching
semiconductor devices must have small conduction loss. IXYS developed new generation
of Trench MOSFET (Trench2TM), which has small gate charge and low on-resistance.
The MOSFET will be well suited for high power applications of synchronous DC to DC
converters used in various systems. The MOSFET is rugged and has avalanche energy
capability.
Table 1: Few Examples of IXYS TrenchT2TM N-Channel Power MOSFETs
Part Number
Vdss
(max)
(V)
Id @
Tc=25C
(A)
Rds(on)
@
Tj=25°C
(Ω)
IXTA220N04T2 IXTP220N04T2 IXTA90N055T2 IXTP90N055T2
IXTA110N055T2
IXTP110N055T2
IXTA200N055T2
IXTP200N055T2
IXTA70N075T2
IXTP70N075T2
IXTA90N075T2
IXTP90N075T2
40
40
55
55
55
55
55
55
75
75
75
75
220
220
90
90
110
110
200
200
70
70
90
90
0.0035
0.0035
0.0084
0.0084
0.0066
0.0066
0.0042
0.0042
0.012
0.012
0.010
0.010
Ciss
(pF)
Qg
(nC
)
trr @
Tj=
25°C
(ns)
R(th)JC
(°C/W)
6500
6500
2670
2670
3060
3060
6800
6800
2580
2580
3100
3100
112
112
42
42
57
57
109
109
46
46
54
54
45
45
37
37
38
38
49
49
48
48
50
50
0.42
0.42
1.0
1.0
0.82
0.82
0.42
0.42
1.0
1.0
0.82
0.82
Pd
(W)
360 360 150 150 180 180 360 360 150 150 180 180 Package
Type
EAS
(mJ)
600 600 300 300 400 400 600 600 300 300 400 400 TO‐263 TO‐220 TO‐263 TO‐220 TO‐263 TO‐220 TO‐263 TO‐220 TO‐263 TO‐220 TO‐263 TO‐220 DC-to-DC Synchronous Converter Design:
Figure 1: Synchronous Buck Converter using IXYS TrenchT2TM Power MOSFET
1
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
In Figure 1, the Q1 is called the high-side or control FET and Q2 is called the
low-side or sync FET applied in a step-down DC to DC synchronous converter
application. The ratio Vo / Vin is controlled by the duty cycle of Q1. To improve the
efficiency, it’s desirable to have Q2 turned ON when Q1 is turned OFF. A simplified
switch state diagram is shown in Figure 2 [2]. It depicts the switching sequence as A-BC-B-A where the state B called “dead time” when both Q1 and Q2 are OFF and the
Schottky diode, D1 is ON to provide the freewheeling operation in the inductive load
circuit. It’s desirable to reduce the dead time to a minimum to improve the efficiency.
However, if the dead time is lower than the turn-on or turn-off times of Q1 and Q2, the
circuit may go into state D, the shoot-through state when both Q1 and Q2 are ON at the
same time causing a short-circuit in the input voltage source, Vin. The state D is
undesirable since it would destroy transistors Q1 and Q2.
Figure 2: Circuit Switch State Diagram [2]
2
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
Figure 3: Ideal Circuit waveforms (with no dead time)
The Switching Period, TS = Ton + Toff , the Switching frequency, f S =
The duty cycle, D =
1
TS
Ton
Ton
=
, Turn-on time, Ton = DTS
TS Ton + Toff
Turn-off time, Toff = (1 − D)TS .
Figure 4: Ideal synchronous buck converter inductor current
An output DC voltage with lowest ripple is considered the best solution. Ripple appears
in the output voltage as the L1 current’s ripple component, ΔI L1 (t ) , which charges and
discharges the output capacitor, C1, as shown in Figure 4. C1 is charged during the
3
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
period when I L1 (t ) is greater than Io. The charge ( ΔQ ) that flows into C1 at this time
divided by the value of C1 is the output voltage ripple component.
Output Inductor Ripple Current and Voltage:
The inductor voltage can be defined as,
di
Δt (Vin − Vo)
, here, Δt = Ton = DTs
V L = L1 = Vin − Vo , or, Δi = ΔI L1 (t ) =
L1
dt
The inductor ripple current is,
Vin − Vo D(Vin − Vo)
=
(1)
ΔI L1 (t ) = DTs
L1
f S • L1
The charge, ΔQ , indicated in Figure 5, can be determined by calculating the area of the
ΔI L1 (t )
Ts
shown in Figure 5.
and width
triangle with height
2
2
ΔI (t ) •T S ΔI L1 (t )
1 ΔI (t ) T
ΔQ = • L1 • S = L1
=
2
2
2
8
8 fS
The ripple voltage is,
ΔQ ΔI L1 (t )Ts D(1 − D)VinTs 2 π 2 (1 − D)Vo f C 2
ΔVL (t ) =
=
=
=
( ) = ΔVO (t )
(2)
C1
8C1
8 L1C1
2
fS
1
, Output low pass filter (LPF) resonant frequency, f S = The
Where, f C =
2π L1C1
switching frequency. The inductor value of L1 and the effective series resistance (ESR)
of the output capacitor, C1, affect the output ripple voltage, ΔVL . A capacitor with the
lowest possible ESR is recommended for the application. For example, 4.7–10 uF
capacitors in X5R/X7R technology have ESR approximately 10 m Ω. .
Summary of design equations:
Ripples voltage/current, Inductor and Capacitor:
ΔI (t )Ts ΔI L1 (t )
=
Output ripple voltage, ΔV L (t ) = L1
8C1
8C1 f S
Inductor ripple current, ΔI L1 (t ) = 8C1 f S • ΔVL (t )
Vin − Vo D(Vin − Vo)
=
Output inductor, L1 ≥ DTs
f S • ΔI L1 (t )
ΔI L1 (t )
ΔI L1
1 ΔI (t ) Ts
since ΔQ = • L1 •
= C1 • ΔVo
Output capacitor, C1 ≥
8 f s ΔVo
2
2
2
1
Output filter cut-off frequency, f C =
2π L1C1
(3)
(4)
(5)
(6)
(7)
4
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
Overview of Synchronous Converter Power Loss: [1]
The losses in the synchronous converter’s power switches can be defined by:
PTotal = PC + PSW + PGate + PBD
(8)
Where PC is the conduction loss, Psw is the switching power loss, PGate is the gate drive
loss and PBD is the body diode loss. In addition, inductor equivalent DC resistance losses
and output capacitor’s ESR loss play significant role in the converter design.
MOSFET Q1 and Q2’s Power Loss: [1]
The conduction losses: (replace D to 1-D for Sync FET, Q2):
2
PC = ( I O D) • RDS ( on )
(9)
The gate-charge losses:
Pg −C = VGS • Q g • f s
(10)
The switching losses:
Figure 5: Transitions waveforms of MOSFET for inductive load
The switching loss is,
PSwitching = Pt ( on ) + Pt ( off )
=
[VDS (max) {I DS ( on ) • t t ( on ) + I DS ( off ) • t t ( off ) } • f s ]
2
(11)
MOSFET Body Diode Loss: [1]
The body diode loss is a function of dead time and in every switching cycle; there are two
dead-time intervals, td1 and td2. The dead-time is defined as the time required when both
the MOSFETs Q1 and Q2 are OFF in order to prevent shoot-through.
5
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
We can write as:
PBD = Ptd 1 + Ptd 2
(12)
Where Ptd1 is the body diode loss during dead time td1 and Ptd2 is the body diode loss
during dead time td2.
ΔI ⎞
1
⎛
Ptd 1 = Pcd 1 + Prr1 = V f • ⎜ I O − L ⎟ • td1 • f S + • Vin • I rr • t rr • f S
2 ⎠
2
⎝
ΔI ⎞
⎛
Ptd 2 = Pcd 2 (Prr 2 = 0) = V f • ⎜ I O + L ⎟ • td 2 • f S
2 ⎠
⎝
(13)
(14)
PWM Gate Driver Power loss: [1]
The power dissipation in the driver is defined by,
PDRIVER = QG ( onl ) • VDD • f S
(15)
where Qg(onl) is the total gate charge of the MOSFET and VDD is the driver power supply.
The gate “point of voltage” is,
I
VSP = VTH + O
g fs
The driver current is,
VDD − VSP
I DRIVER ( L− H ) =
RDRIVER ( PULL−UP ) + RGate
I DRIVER ( H − L ) =
VDD − VSP
RDRIVER ( PULL− DOWN ) + RGate
The rise time is,
QG ( on )
t t ( on ) =
I DRIVER ( L − H )
The fall time is,
QG ( on )
t t ( off ) =
I DRIVER ( H − L )
(16)
(17)
(18)
(19)
(20)
If an external Schottky diode (D1) is used across Q2, the Schottky’s capacitance needs to
be charged during Q1 turn-on. The power loss to charge the Schottky’s capacitance is,
C
• VIN2 • f S
PC ( SCHOTTKY ) = SCHOTTKY
(21)
2
6
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
Design Example 1:
Assume design parameters as VIN=12V, VO=3.3V and Io=12A.
Table 1: Design Consideration 1 for synchronous buck converter
Input Voltage, Vin
12V
Output Voltage, Vo
3.3V
Output Current, Io
12A
Assume the output ripple voltage is within ± 1% of Vo. For Vo =3.3V, the output ripple
is limited within, ΔV L (t ) ≤ 0.033V . When the output capacitor (C1) is 10uF, the inductor
L1 values for the range of switching frequencies from 100 kHz to 500 kHz are given in
Table: 2 based on equations 3-7.
Table 2: When C1= 10uF
Vin
(V)
12
12
12
12
12
Vo
(V)
3.3
3.3
3.3
3.3
3.3
D
0.275
0.275
0.275
0.275
0.275
ΔVL
(V)
0.033
0.033
0.033
0.033
0.033
fs
(kHz)
100
200
300
400
500
C1
(uF)
10
10
10
10
10
ΔΙL1
(A)
0.264
0.528
0.792
1.056
1.32
L1
(uH)
90
45.31
30.20
22.65
18.12
fc
(kHz)
5.31
7.48
9.16
10.60
11.83
Synchronous Driver Controller: ISL6594D from Intersil:
Based on equation 18 and 19, From ISL6594D driver datasheet, given high-side: tr=26nS,
tf=18nS and source/sink current = 1.25/2A (max). For low-side, trr=18nS, tf=12nS and
source/sink current = 2/3.0 A (max):
Table 4: from Datasheet
High-Side
Rise time
Source Current (A)
Required Qg(on)
Source
Sink
Low-Side
26 ns
18 ns
Rise time
1.25
2
Source Current (A)
32.5nC
36nC
Required Qg(on)
Source
Sink
18nS
12ns
2
3
36nC
36nC
7
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
ISL6594D Specification:
Recommended devices for this application:
1. IXTA90N055T2
VDS = 55V, Id25=90A
Qg(on) = 42nC, Qgs = 14nC, Qgd = 8.5nC,
td(on) = 19nS, tr = 21nS, td(off) = 39nS, tf = 19nS.
Rds(on) = 8.4m Ω
Vgs(th) = 2-4V, gfs = 43
Ciss = 2670pF, Coss = 420pF, Crss = 100pF
Or,
1. IXTA110N055T2
Vds = 55V, Id25=110A
Qg(on) = 57nC, Qgs = 16nC, Qgd = 11nC,
td(on) = 18nS, tr = 25nS, td(off) = 40nS, tf = 23nS.
Rds(on) = 6.6m Ω , Vgs(th) = 2-4V, gfs = 49
Ciss = 3060pF, Coss = 497pF, Crss = 105pF
Analysis based on Above IXTA90N055T2:
14nC
QG ( SW ) = 8.5nC +
= 15.5nC
2
The “point of voltage” is defined by, VSP = VTH +
IO
15
= 3+
= 3.35V
g fs
43
The driver current is,
I DRIVER ( L− H ) =
10 − 3.35 6.65
VDD − VSP
=
=
= 1.33 A
RDRIVER ( PULL−UP ) + RGate
3+ 2
5
8
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
I DRIVER ( H − L ) =
VDD − VSP
RDRIVER ( PULL− DOWN ) + RGate
=
10 − 3.35
= 1.58 A
2.2 + 2
The rise time is, t t ( on ) = 26nS + 10nS = 36nS
The fall time is, t t ( off ) = 18ns + 10nS = 28nS
High-Side MOSFET loss (Q1=IXTA90N055T2):
The conduction loss is,
PCond _ Q1 = I O2 • RDS ( on ) • D
= 12 2 • 0.0084 • 0.275 = 0.332 = 332mW
The Gate-Charge losses: (assume fs = 200 kHz)
PGC _ Q1 = VGS • Q g • f s = 10.0 x 42 x10 −9 x 200 x10 3 = 84mW
And estimated switching loss is,
[VDS (max) {I DS ( on ) • t t ( on ) + I DS ( off ) • t t ( off ) } • f s ]
Pt =
2
12 • 12
=
• (36 + 28) x10 −9 x 200 x10 3 = 0.921W=921mW
2
Total high-side losses: 332mW+84mW+921mW = 1337mW=1.337W
Low-Side MOSFET loss (Q2):
The conduction loss is,
PCond _ Q 2 = I O2 • RDS ( on ) • (1 − D)
= 12 2 • 0.0084 • 0.725 = 0.877W = 877mW
The Gate-Charge loss:
PGC _ Q1 = VGS • Q g • f s = 10.0 x 42 x10 −9 x 200 x10 3 = 84mW
Total low-side losses: 877mW+84mW =961mW
ISL6594D Driver loss:
From datasheet: VDD = 5V
Table 6: IXS839 Driver Output Stage from datasheet
RDRIVER(PULL_UP)
3.0 Ω
Driver pull up resistance
Driver pull down resistance RDRIVER(PULL_DOWN) 2.2 Ω
Driver gate resistance
RGATE
2Ω
9
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
The power dissipation in the driver is defined by,
T − Ta
PDRIVER = J
= QG ( total ) • VDD • f SW
RthJC
where VDD = 10V and fS = 200 kHz (assume for this case)
The estimated driver power dissipation, PD ≈ 42 • 10 −9 • 10 • 200 • 10 3 = 84mW
Dead-Time Power Loss: [3]
The dead-time is defined as the time required when both the MOSFETs are off in order to
prevent shoot-through. In this period, the Schottky diode (or integral body diode is
forward-biased and provided a power loss defined by,
Driver IXS839 provides delay time in the datasheet,
t Delay _ Time (nS ) = C Delay ( pF ) • (0.5nS / pF )
(22)
Assume, t d 1 = t d 2 = 100nS , which provides C Delay ( pF ) = 200 pF
The Delay-Time loss is define in (11-13) as
ΔI ⎞
1
⎛
Ptd 1 = Pcd 1 + Prr1 = V f • ⎜ I O − L ⎟ • td1 • f S + • Vin • I rr • t rr • f S
2 ⎠
2
⎝
0.528 ⎞
1
⎛
−9
3
−9
3
= 0.85 • ⎜12 −
⎟ • 100 x10 • 200 x10 + • 12 • 2.2 • 37 x10 • 200 x10
2 ⎠
2
⎝
= 0.19905+0.09768= 0.297W= 297mW
ΔI ⎞
⎛
Ptd 2 = Pcd 2 (Prr 2 = 0) = V f • ⎜ I O + L ⎟ • td 2 • f S
2 ⎠
⎝
0.528 ⎞
⎛
−9
3
= 0.85 • ⎜12 +
⎟ • 100 x10 • 200 x10 =0.208W= 208mW
2
⎝
⎠
PBD = Ptd 1 + Ptd 2 = 297 mW + 208mW = 505mW
Synchronous Converter Efficiency:
If we neglect inductor’s DC power loss and capacitor’s ESR loss then the total
estimated power loss, Ploss= 1337mW+1007mW+84mW+505mW=2933mW= 2.933W
Given output power, Po = Vo*Io = 3.3*12= 39.6W
Estimated input power, Pin= 39.6+2.933=42.6W
The efficiency is defined as, η =
VoIo
Po
=
Vin • Iin Pin
(23)
10
DC to DC Synchronous Converter Design
Abdus Sattar, IXYS Corporation
IXAN0068
The estimated efficiency, η =
39.6
= 0.93 = 93% %,
42.6
Estimated input current:
If we assume only 93% efficiency, then the estimated input current can be obtained,
3.3 • 12
VoIo
=
= 3.5 A A
Estimated input current, I in =
Vin • η 12 • 0.93
Bootstrap Circuit Design: [3]
Selecting bootstrap circuit components are done with consideration of the electrical rating
and characteristics of the high-side MOSFET (Q1).
The capacitance is defined by datasheet of IXS839 driver,
Q
(24)
C BST = G ( total )
ΔVBST
Where QG(total) is the total gate charge of high-side MOSFET (Q1), and ΔVBST is the
allowable voltage droop in Q1. Assume this voltage droop equal to 0.1V.
42nC
= 0.210uF
200mV
The bootstrap diode and capacitor voltage rating should be
C BST =
V Bootstrap _ DiodeandCapacitor > VIN + VDD
The average forward current is defined by,
I F ( Avg ) = QG ( total ) • f SW
−9
(25)
= 42 • 10 • 250 • 10 = 10.5mA
3
Bibliography
[1] “Synchronous Buck MOSFETs loss calculation” AN-6005, Jon Klein, Fairchild
Semiconductor, 01/04/2006, www.fairchildsemi.com
[2] “Examination of reverse recovery losses in a synchronous buck converter circuit”
Application Note from Silicon Semiconductor, 2003, www.siliconsemi.com
[3] Datasheet for ISL6594D “Advanced Synchronous Rectified Buck MOSFET Driver”
from Intersil Corporation, 2007, www.intersil.com
11