MITSUBISHI PSM05S93E5-A

< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FUNCTION AND RATINGS
 3 phase DC/AC inverter
 500V / 5A (MOSFET)
 N-side MOSFET open source
 Built-in bootstrap diodes with current limiting resistor
APPLICATION
 AC 100~240Vrms(DC voltage:400V or below) class
low power motor control
TYPE NAME
PSM05S93E5-A
With over temperature protection
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
● For P-side
: Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection
● For N-side
: Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC),
Over temperature protection (OT)
● Fault signaling : Corresponding to SC fault (N-side MOSFET), UV fault (N-side supply) and OT fault
● Input interface : 3, 5V line, Schmitt trigger receiver circuit (High Active)
●UL Recognized : UL1557 File E323585
INTERNAL CIRCUIT
MOSFET1
P(24)
VUFB(2)
VVFB(3)
U(23)
MOSFET2
VWFB(4)
HVIC
UP(5)
V(22)
MOSFET3
VP(6)
W P(7)
VP1(8)
W(21)
VNC(9)
MOSFET4
UN(10)
VN(11)
NU(20)
W N(12)
MOSFET5
VN1(13)
FO(14)
CIN(15)
LVIC
NV(19)
MOSFET6
VNC(16)
NW(18)
Publication Date : October 2013
1
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tch = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VDD
VDD(surge)
VDSS
±ID
±IDP
PD
Tch
Parameter
Supply voltage
Supply voltage (surge)
Drain-source voltage
Each MOSFET drain current
Each MOSFET drain current (peak)
Drain dissipation
Channel temperature
Condition
Applied between P-NU,NV,NW
Applied between P-NU,NV,NW
TC= 25°C
TC= 25°C, less than 1ms
TC= 25°C, per 1 chip
(Note 1)
Ratings
400
450
500
5
10
35.7
-20~+150
Unit
V
V
V
A
A
W
°C
Note1: The maximum junction temperature rating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the average
channel temperature should be limited to Tch(Ave)≤125°C (@Tc≤100°C).
CONTROL (PROTECTION) PART
Symbol
VD
VDB
VIN
VFO
IFO
VSC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
20
20
-0.5~VD+0.5
-0.5~VD+0.5
1
-0.5~VD+0.5
Unit
V
V
V
V
mA
V
Ratings
Unit
400
V
-20~+100
-40~+125
°C
°C
1500
Vrms
TOTAL SYSTEM
Symbol
TC
Tstg
Parameter
Self protection supply voltage limit
(Short circuit protection capability)
Module case operation temperature
Storage temperature
Viso
Isolation voltage
VDD(PROT)
Condition
VD = 13.5~16.5V, Inverter Part
Tch = 125°C, non-repetitive, less than 2μs
Measurement point of Tc is provided in Fig.1
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
Fig. 1: TC MEASUREMENT POINT
Control terminals
DIPIPM
11.6mm
3mm
IGBT chip position
Tc point
Heat sink side
Power terminals
THERMAL RESISTANCE
Symbol
Rth(ch-c)Q
Parameter
Junction to case thermal resistance
Condition
(Note2)
1/6 module
Min.
-
Limits
Typ.
-
Max.
2.8
Unit
K/W
Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Publication Date : October 2013
2
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tch = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VDS(on)
VSD
ton
tC(on)
toff
tC(off)
trr
IDSS
Parameter
Condition
Tch= 25°C
Tch= 125°C
Drain-source on-state
resistance
VD=VDB = 15V, VIN= 5V, ID= 5A
Source-drain voltage drop
VIN= 0V, -ID= 5A
Switching times
VDD= 300V, VD= VDB= 15V
ID= 5A, Tch= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
Drain-source cut-off
current
VDS=VDSS
Tch= 25°C
Tch= 125°C
Min.
0.65
-
Limits
Typ.
0.60
1.30
0.90
1.15
0.35
1.00
0.10
0.25
-
Max.
0.80
1.70
1.30
1.65
0.55
1.50
0.20
1
10
Min.
0.43
7.0
7.0
10.3
10.8
100
4.9
20
0.70
0.80
Limits
Typ.
0.48
10.0
10.0
120
10
1.00
2.10
1.30
Max.
2.80
2.80
0.10
0.10
0.53
12.0
12.0
12.5
13.0
140
0.95
1.50
2.60
-
0.35
0.65
-
1.1
80
1.7
100
2.3
120
Unit
Ω
V
μs
μs
μs
μs
μs
mA
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
ID
Circuit current
Each part of VUFB-U,
VVFB-V, VWFB-W
IDB
VSC(ref)
UVDBt
UVDBr
UVDt
UVDr
OTt
OTrh
VFOH
VFOL
tFO
IIN
Vth(on)
Vth(off)
Vth(hys)
VF
R
VD=15V, VIN=0V
VD=15V, VIN=5V
VD=VDB=15V, VIN=0V
VD=VDB=15V, VIN=5V
Total of VP1-VNC, VN1-VNC
Short circuit trip level
VD = 15V
P-side Control supply
under-voltage protection(UV)
Trip level
Reset level
Tch ≤125°C
Trip level
Reset level
VD = 15V
Trip level
Detect LVIC temperature
Hysteresis of trip-reset
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
N-side Control supply
under-voltage protection(UV)
Over temperature protection
(OT)
(Note4)
Fault output voltage
(Note 3)
Fault output pulse width
Input current
ON threshold voltage
OFF threshold voltage
ON/OFF threshold
hysteresis voltage
Bootstrap Di forward voltage
IF=10mA including voltage drop by limiting resistor
Built-in limiting resistance
Included in bootstrap Di
(Note 5)
VIN = 5V
Applied between UP, VP, WP, UN, VN, WN-VNC
(Note 6)
Unit
mA
V
V
V
V
V
°C
°C
V
V
μs
mA
V
V
Ω
Note 3 : SC protection works for N-side only. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.
4 : When the LVIC temperature exceeds OT trip temperature level(OTt), OT protection works and Fo outputs. In that case if the heat sink dropped off or fixed
loosely, don't reuse that DIPIPM. (There is a possibility that channel temperature of power chips exceeded maximum Tch(150°C).
5 : Fault signal Fo outputs when SC, UV or OT protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed
width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)
6 : The characteristics of bootstrap Di is described in Fig.2.
Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.)
160
140
120
100
80
60
40
20
0
30
IF [mA]
IF [mA]
25
20
15
10
5
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V F [V]
0.0
Publication Date : October 2013
3
0.5
1.0
1.5
2.0
V F [V]
2.5
3.0
3.5
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Min.
0.59
Limits
Typ.
0.69
Max.
0.78
N·m
EIAJ-ED-4701
10
-
-
s
EIAJ-ED-4701
2
-
-
times
-
8.5
-
g
-50
-
100
μm
Condition
Mounting torque
Terminal pulling strength
Terminal bending strength
Mounting screw : M3 (Note 8)
Control terminal: Load 4.9N
Power terminal: Load 9.8N
Control terminal: Load 2.45N
Power terminal: Load 4.9N
90deg. bend
Recommended 0.69N·m
Weight
Heat-sink flatness
(Note 9)
Unit
Note 8: Plain washers (ISO 7089~7094) are recommended.
Note 9: Measurement point of heat sink flatness
4.6mm
Measurement position
+ -
17.5mm
Heat sink side
+
Heat sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
ΔVD, ΔVDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
PWIN(on)
PWIN(off)
VNC
Tch
Min.
0
13.5
13.0
-1
1.0
-
Limits
Typ.
300
15.0
15.0
-
Max.
400
16.5
18.5
+1
20
fPWM= 5kHz
-
-
2.5
fPWM= 15kHz
-
-
2.0
0.7
0.7
-5.0
-20
-
+5.0
+125
Condition
Applied between P-NU, NV, NW
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
For each input signal
TC ≤ 100°C, Tch ≤ 125°C
VDD = 300V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tch ≤ 125°C
(Note10)
Minimum input pulse width
VNC variation
Channel temperature
(Note 11)
Between VNC-NU, NV, NW (including surge)
Note 10: Allowable r.m.s. current depends on the actual application conditions.
11: DIPIPM might not make response if the input signal pulse width is less than PWIN(on), PWIN(off).
Publication Date : October 2013
4
Unit
V
V
V
V/μs
μs
kHz
Arms
μs
V
°C
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 3 Timing Charts of The DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: MOSFET ON and outputs current.
a2. Short circuit current detection (SC trigger)
(It is recommended to set RC time constant 1.5~2.0μs so that MOSFET shut down within 2.0μs when SC.)
a3. All N-side MOSFET's gates are hard interrupted.
a4. All N-side MOSFETs turn OFF.
a5. FO outputs for tFo=minimum 20μs.
a6. Input = “L”: MOSFET OFF
a7. Fo finishes output, but MOSFETs don't turn on until inputting next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: MOSFET ON and outputs current.
Lower-side control
input
a6
SET
RESET
Protection circuit state
a3
Internal gate
a4
SC trip current level
a8
Output current ID
a1
a7
a2
SC reference voltage
Sense voltage of
the shunt resistor
Delay by RC filtering
Error output Fo
a5
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but MOSFET turns ON by next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: MOSFET ON and outputs current.
b3. VD level drops to under voltage trip level. (UVDt).
b4. All N-side MOSFETs turn OFF in spite of control input condition.
b5. Fo outputs for tFo=minimum 20μs, but output is extended during VD keeps below UVDr.
b6. VD level reaches UVDr.
b7. Normal operation: MOSFET ON and outputs current.
Control input
RESET
Protection circuit state
Control supply voltage VD
UVDr
SET
b1
UVDt
b2
b3
b4
Output current ID
Error output Fo
b5
Publication Date : October 2013
5
RESET
b6
b7
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, MOSFET turns on by next ON signal (LH).
c2. Normal operation: MOSFET ON and outputs current.
c3. VDB level drops to under voltage trip level (UVDBt).
c4. MOSFET of the correspond phase only turns OFF in spite of control input signal level, but there is no FO signal output.
c5. VDB level reaches UVDBr.
c6. Normal operation: MOSFET ON and outputs current.
Control input
RESET
SET
c1
UVDBt
RESET
Protection circuit state
UVDBr
Control supply voltage VDB
c3
c2
c5
c6
c4
Output current ID
Error output Fo
Keep High-level (no fault output)
[D] Over Temperature Protection (N-side, Detecting LVIC temperature)
d1. Normal operation: MOSFET ON and outputs current.
d2. LVIC temperature exceeds over temperature trip level(OTt).
d3. All N-side MOSFETs turn OFF in spite of control input condition.
d4. Fo outputs for tFo=minimum 20μs, but output is extended during LVIC temperature keeps over OTt.
d5. LVIC temperature drops to over temperature reset level.
d6. Normal operation: MOSFET turns on by next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
Control input
SET
Protection circuit state
OTt
RESET
d2
d5
Temperature of LVIC
OTt - OTrh
d1
d3
Output current ID
d4
Error output Fo
Publication Date : October 2013
6
d6
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 4 Example of Application Circuit
Bootstrap negative electrodes
should be connected to U,V,W
terminals directly and separated
from the main output wires
P(24)
MOSFET1
C1 D1 C2 VUFB(2)
+
VVFB(3)
U(23)
+
MOSFET2
VWFB(4)
+
HVIC
UP(5)
V(22)
VP(6)
M
MOSFET3
W P(7)
VP1(8)
W(21)
C2
+
MCU
VNC(9)
C3
MOSFET4
UN(10)
VN(11)
NU(20)
W N(12)
MOSFET5
5V
Fo(14)
LVIC
NV(19)
MOSFET6
15V VD
C1
VN1(13)
+
D1
C2
VNC(16)
Long wiring might cause SC level
fluctuation and malfunction.
CIN(15)
B
Long GND wiring might generate
noise to input signal and cause
MOSFET malfunction.
C4
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
C
D
R1
Shunt
resistor
A
N1
Control GND wiring
(1)
Long wiring might cause
short circuit failure
NW(18)
Power GND wiring
If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.
It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).
It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.
To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time
might vary with the wiring pattern, so the enough evaluation on the real system is necessary.
To prevent malfunction, the wiring of A, B, C should be as short as possible.
The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be
connected at near NU, NV, NW terminals.
All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic
type and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off threshold voltage.
Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to
1mA. (IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to
5V, 10kΩ (5kΩ or more) is recommended.)
Thanks to built-in HVIC, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.
If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.
To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase MOSFET or other DIPIPM.
Publication Date : October 2013
7
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 5 MCU I/O Interface Circuit
5V line
10kΩ
Note)
Design for input RC filter depends on PWM control scheme used
in the application and wiring impedance of the printed circuit board.
DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter, it is
necessary to satisfy turn-on threshold voltage requirement.
Fo output is open drain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ
（5kΩ or more） is recommended.
DIPIPM
UP,VP,W P,UN,VN,W N
MCU
3.3kΩ(min)
Fo
VNC(Logic)
Fig. 6 Pattern Wiring Around the Shunt Resistor
NU, NV, NW should be connected
each other at near terminals.
DIPIPM
DIPIPM
Wiring Inductance should be less than 10nH.
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
NU
NV
NW
VNC
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
N1
Shunt
resistor
VNC
NU
NV
NW
GND wiring from VNC should
be connected close to the
terminal of shunt resistor.
N1
Shunt
resistors
GND wiring from VNC should
be connected close to the
terminal of shunt resistor.
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
Fig. 7 Pattern Wiring Around the Shunt Resistor (for the case of open source)
When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use
the external protection circuit as below.
DIPIPM
Drive circuit
P
P-side MOSFETs
U
V
W
N-side MOSFETs
External protection circuit
Comparators
(Open collector output type)
Rf
C
Drive circuit
VNC
Protection circuit
CIN
NW
NV
NU
B
Cf
-
Vref
+
Vref
+
Vref
+
5V
D
-
Shunt
resistors
A
OR output
N1
(1) It is necessary to set the time constant RfCf of external comparator input so that MOSFET stops within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Select the external shunt resistance so that SC trip-level is less than specified value (=1.7 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level when protection works should be over 0.53V (=maximum Vsc(ref) rating).
Publication Date : October 2013
8
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 8 Package Outlines
Long terminal type (PSM05S93E5-A)
Dimensions in mm
TERMINAL CODE
1-A
1-B
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC(VNC)
NC(VP1)
VUFB
VVFB
VWFB
UP
VP
WP
VP1
VNC *1
UN
VN
WN
VN1
Fo
CIN
VNC *1
NC
NW
NV
NU
W
V
U
P
NC
1) 9 & 16 pins (VNC) are connected inside DIPIPM, please connect either one to the control power supply GND outside and leave another one open.
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
Publication Date : October 2013
9
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Revision Record
Rev.
Date
Page
1
10/15/2013
-
Revised contents
New
Publication Date : October 2013
10
< Dual-In-Line Package Intelligent Power Module >
PSM05S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due consideration to safety when
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Publication Date : October 2013
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