ccd linescan controller nc φOSC te RESET nc CCD Linescan controller Designed for Sony ILX 551 All clock signals included. Start of frame output. Selectable exposure time. VCC VCC nc ts0 ts1 ts2 nc nc GND nc nc nc nc nc Key Features: nc nc nc CLS 551 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 CLS 551 Top View 39 38 37 36 35 34 33 32 31 30 29 SOS PCLK nc nc nc VCC nc φCLK φROG nc nc nc ps0 ps1 ps2 nc GND nc nc nc nc nc 18 19 20 21 22 23 24 25 26 27 28 Overview: Interface: The CLS 551 is an easy to use, complete ccd linescan controller, designed for the SONY ILX 551 linescan sensor. The CLS 551 linescan controller includes all CCD-timing signals including pixel clock and exposure control. For operation the CLS 551 requires power +5 V only, and a 10 MHz TTL or CMOS clock input signal. Additional logic is not required. The digital interface provides user selectable pixel clock and exposure time. An output for pixel clock and start of frame facilitates the operation with an additional frame grabber. khs instruments To provide more flexibility, the CLS 551has an interface to control exposure time and pixel clock. All inputs are connected to internal pull up resistors, so they can left unconnected if not required. With an additional oscilloscope and a Sony IILX 551 CCD-sensor the CLS 551converts to a complete very low cost CCD-linescan camera with display. (See the application on the last page). Absolute Maximum Ratings VCC Supply voltage Input voltage applied Digital output current Storage temperature Operating temperature - 0.5 V to + 6 V - 0.5 to Vcc + 0.5 V 0 to 5 mA - 20 to 150 °C 0 to 50 °C DC Characteristics Output low voltage (8 mA) Output high voltage (-4 mA) Input pullup current Input low Voltage (max) Input high voltage (min) 0.4V 2.4V -0.15 mA 0.8 V 2.0V Power requirements: +5V 200mA www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 1/7 nc φOSC te RESET nc VCC VCC nc 7 8 9 10 11 12 13 14 ts0 ts1 ts2 15 16 17 nc nc nc nc nc GND nc nc nc nc nc Pin Configuration 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLS 551 Top View SOS PCLK nc nc nc 44-Pin PLCC Pinout Diagram VCC nc φCLK φROG nc nc nc ps0 ps1 ps2 nc GND nc nc nc nc nc 18 19 20 21 22 23 24 25 26 27 28 User Interface Connections: Pinout description: Signal Pin Pin Name Pin Type Pin Description SOS PCLK ts0..ts1 te ps0..ps1 φOSC Reset nc OUT OUT IN IN IN IN IN NC Start of scan output, low active. Pixelclock output, low active. Exposure control. Exposure control external. Pixelclock control. Oscillator input CCD asynchron reset low active Do not connect! SOS PCLK ts2 ts1 ts0 te 39 38 17 16 15 9 Pin Signal 10 8 21 20 20 Reset φOSC ps2 ps1 ps0 All inputs: 50 K pull up to VCC. CLS 551 CCD Interface Connections: Pinout description: Signal Pin Pin Name φCLK φROG φCLK φROG 32 31 Pin Type Pin Description OUT OUT Clock pulse Readout gate pulse Power Connections: Pinout description: Signal Pin Pin Name Pin Type Pin Description GND VCC Power Power Power Ground. Power + 5 V. GND GND VCC VCC VCC 1 23 12 13 34 www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 2/7 φOsc Timing tf tr φOSC tl th Item φOSC pulse Duty Symbol Min. Typ. Max. Unit - - 50 - % tr, tf 0 10 20 ns - - 10 10 MHz *1 φOSC pulse rise / fall time φOSC frequency *1 100 x th / (tl + th ) Exposure timer control ts2 ts1 ts0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 Note: For timing details see t16, page 4 exposure time 2088 τ 4096 τ 8192 τ 16384 τ 32768 τ 65536 τ extern 1 0 1 0 1 0 0 CLS 551 Note) τ is the period of φCLK (τ = 200 ns at 5 MHz). Pixelclock control ps2 1 1 1 1 ps1 ps0 φCLK (at 10 MHz φCLK) 1 1 0 0 1/2 φOsc 1/4 φOsc 1/8 φOsc 1/16 φOsc ( 5 MHz) ( 2.5 MHz) ( 125 KHz) ( 62.5 KHz) 1 0 1 0 www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 3/7 Clock Timing Diagram Exposure time 2048 1 48 2 SOS PCLK φCLK φROG CLS 551 1 www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 4/7 φClock Timing φCLK t3 Item φCLK pulse Duty *1 *1 t4 Symbol Min. Typ. Max. Unit - - 50 - % 100 x t4 / (t3 + t4 ) φROG, φCLK Timing φROG t9 φCLK CLS 551 t7 Item φROG φCLK pulse timing 1 t11 Symbol t7 Min. Typ. Max. Unit - 10 τ - ns φROG φCLK pulse timing 2 t11 - 6τ - ns φROG pulse period t9 - 8τ - ns Note) τ is the period of φCLK. www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 5/7 φROG, SOS Timing φROG SOS t20 Item t21 Symbol Min. Typ. Max. Unit φROG SOS pulse timing 1 t20 -10 0 10 ns φROG SOS pulse timing 2 t21 -10 0 10 ns φCLK, PCLK Timing φCLK CLS 551 PCLK t22 Item t23 Symbol Min. Typ. Max. Unit φCLK PCLK pulse timing 1 t22 -10 0 10 ns φCLK PCLK pulse timing 2 t23 -10 0 10 ns www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 6/7 Application CH 1: Trigger Set oszilloscope to Timebase Trigger CH1 CH2 0.1 ms/DIV Intern CH1 5 V/DIV 1 V/DIV CH 2:CCD-Signal + te RESET nc nc CLS 551 nc nc nc nc nc GND nc ps0 ps1 ps2 nc ts0 ts1 ts2 6 5 4 3 2 1 44 43 42 41 40 7 39 8 φOSC 38 9 37 10 36 CLS 551 11 35 12 VCC VCC 34 Top View 13 VCC 33 14 φCLK 32 15 φROG 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 GND nc +9V SOS PCLK nc nc nc nc nc nc nc nc nc nc nc 10 MHz in nc nc nc nc nc VCC +5V GND ILX 551 See SONY ILX 551 datasheet for more details. Fig. 1 Test circuit www.khs-instruments.com C551_01 Rev 1.01 / 06.2001 Specifications are subject to change without 7/7