ILX551A
2048-pixel CCD Linear Sensor (B/W)
Description
The ILX551A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads B4 size documents at a density of
200DPI (Dot Per Inch). A built-in timing generator
and clock-drivers ensure direct drive at 5V logic for
easy use.
Features
• Number of effective pixels: 2048 pixels
• Pixel size: 14µm × 14µm (14µm pitch)
• Built-in timing generator and clock-drivers
• Ultra low lag
• Maximum clock frequency: 5MHz
22 pin DIP (Cer-DIP)
9
VDD2
11
φROG
Block Diagram
15 NC
VDD2
9
14 NC
NC
10
13 NC
φROG
11
Clock pulse generator
Sample-and-hold pulse generator
Output amplifier
Sample-and-hold
circuit
SHSW
4
21
VDD2
Read out gate
14
15
22
18
20
VDD2
NC
D14
VDD1
D15
1
12 GND
VOUT
2048
19
8
GND
VDD2
5
16 NC
φCLK
7
8
NC
VDD2
17 GND
7
6
NC
NC
6
18 NC
NC
5
3
φCLK
NC
19 GND
21 VDD2
Clock-drivers
4
16
SHSW
NC
20 VDD1
17
3
S1
NC
1
D33
2
GND
S2
NC
22 VDD2
CCD analog shift register
NC
NC
S2047
1
2
D34
S2048
VOUT
Read out gate
pulse generator
12
D35
Pin Configuration (Top View)
Mode
selector
GND
13
D36
NC
D37
V
V
°C
°C
NC
10
D38
NC
D39
Absolute Maximum Ratings
• Supply voltage
VDD1
11
VDD2
6
• Operating temperature
–10 to +55
• Storage temperature
–30 to +80
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00439-PS
ILX551A
Pin Description
Pin
No.
Symbol
Pin
No.
Description
Symbol
Description
1
VOUT
Signal output
12
GND
GND
2
NC
NC
13
NC
NC
3
NC
NC
14
NC
NC
4
SHSW
Switch
15
NC
NC
5
φCLK
Clock pulse
16
NC
NC
6
NC
NC
17
GND
GND
7
NC
NC
18
NC
NC
8
VDD2
5V power supply
19
GND
GND
9
VDD2
5V power supply
20
VDD1
9V power supply
10
NC
NC
21
VDD2
5V power supply
11
φROG
Clock pulse
22
VDD2
5V power supply
S/H → GND
{ with
without S/H → V
DD2
Recommended Supply Voltage
Item
Min.
Typ.
Max.
Unit
VDD1
8.5
9.0
9.5
V
VDD2
4.75
5.0
5.25
V
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Mode Description
Mode in use
Pin condition
S/H
Pin 4 SHSW
Yes
GND
No
VDD2
Input Capacity of Pins
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φCLK pin
CφCLK
—
10
—
pF
Input capacity of φROG pin
CφROG
—
10
—
pF
Recommended Input Pulse Voltage
Min.
Typ.
Max.
Unit
Input clock high level
4.5
5.0
5.5
V
Input clock low level
0.0
—
0.5
V
Item
–2–
ILX551A
Electrooptical Characteristics
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm))
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Secsitivity
R
30
40
50
V/(lx · s)
Note 1
Sensitivity nonuniformity
PRNU
—
2.0
8.0
%
Note 2
Saturation output voltage
VSAT
1.5
1.8
—
V
—
Dark voltage average
VDRK
—
0.3
2.0
mV
Note 3
Dark signal nonuniformity
DSNU
—
0.5
3.0
mV
Note 3
Image lag
IL
—
0.02
—
%
Note 4
Dynamic range
DR
—
6000
—
—
Note 5
Saturation exposure
SE
—
0.045
—
lx · s
Note 6
9V supply current
IVDD1
—
4.0
8.0
mA
—
5V supply current
IVDD2
—
1.8
5.0
mA
—
Total transfer efficiency
TTE
92.0
97.0
—
%
—
Output impedance
ZO
—
600
—
Ω
—
Offset level
VOS
—
4.0
—
V
Note 7
Notes)
1. For the sensitivity test light is applied with a uniform intensity of illumination.
2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU =
(VMAX – VMIN)/2
VAVE
× 100 [%]
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE.
3. Integration time is 10ms.
4. VOUT = 500mV
5. DR =
VSAT
VDRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in
proportion to optical accumulated time.
VSAT
R
,
6. SE =
7. Vos is defined as indicated below.
D31
OS
D32
D33
S1
VOS
GND
–3–
VOUT
φCLK
φROG
0
5
0
2
3
4
–4–
1-line output period (2087 pixels)
Effective picture
elements signal
(2048 pixels)
D31
D32
D33
S1
S2
S3
S4
Optical black
(18 pixels)
D11
D12
D13
D14
D15
D5
D6
Dummy signal (33 pixels)
D2
D3
D4
5
2087
Dummy signal
(6 pixels)
S2045
S2046
S2047
S2048
D34
D35
D36
S37
S38
D39
1
Fig. 1. Clock Timing Diagram (without S/H mode)
ILX551A
2
1
ILX551A
Fig. 2. φCLK, VOUT Timing
t1
t2
φCLK
t4
,
,
,
,,
t3
t5
VOUT
t6
Item
Symbol
Min.
Typ.
Max.
Unit
φCLK pulse rise/fall time
φCLK pulse duty ∗1
t1, t2
0
10
—
ns
—
40
50
60
%
φCLK – VOUT 1
t5
50
80
110
ns
φCLK – VOUT 2
t6
30
75
120
ns
∗1 100 × t3/(t3 + t4)
Fig. 3. φROG, φCLK Timing
φROG
t8
t9
t10
φCLK
t7
Item
Symbol
t11
Min.
Typ.
Max.
Unit
φROG, φCLK pulse timing
t7, t11
500
1000
—
ns
φROG pulse rise/fall time
t8, t10
0
10
—
ns
φROG pulse period
t9
500
1000
—
ns
–5–
ILX551A
Example of Representative Characteristics
Spectral sensitivity characteristics
(Standard characteristics)
1.0
Ta = 25°C
0.9
Relative sensitivity
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
900
1000
Wavelength [nm]
Dark signal voltage rate vs. Ambient temperature
(Standard characteristics)
VDD1, VDD2 supply current vs. Clock frequency
(Standard characteristics)
10
10
5
5
IVDD1, IVDD2 – VDD1, VDD2 supply current [mA]
Dark signal voltage rate
IVDD1
IVDD2
1
0.5
0.1
0
10
20
30
40
50
1
0.5
0.1
0.1M
60
Ta – Ambient temperature [°C]
1M
Clock frequency [Hz]
–6–
5M
0.01µ
9V
Output signal
10µ/16V
3kΩ
1Ω
2SA1175
2
1
12
13
14
15
16
17
18
19
20
21
22
VDD2 (D)
5V
VDD2 (D)
VOUT
–7–
NC
VDD1 (A)
4
φCLK
5
6
7
8
9
10
φROG
11
0.01µ
22µ/10V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
3
NC
GND (A)
SHSW
NC
φCLK
GND (A)
NC
NC
NC
NC
VDD2 (D)
NC
VDD2 (D)
NC
NC
GND (D)
φROG
Application Circuit
ILX551A
ILX551A
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
,
,
2) Notes on Handling CCD Cer-DIP Packages
The following points should be observed when handling and installing cer DIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1) Compressive strength: 39N/surface
(Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm
Upper ceramic layer
29N
39N
29N
0.9Nm
Low-melting glass
Lower ceramic layer
(1)
(2)
(3)
(4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating.
(4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after
it has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded
30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
–8–
ILX551A
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch
the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
–9–
5.0 ± 0.5
– 10 –
V
H
7.35 ± 0.5
1
22
41.6 ± 0.5
Cer-DIP
TIN PLATING
42 ALLOY
5.20g
LS-A18-01(E)
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
2.54
11
12
0.51
22pin DIP (400mil)
28.672 (14µm X 2048Pixels)
No.1 Pixel
PACKAGE STRUCTURE
4.0 ± 0.5
Unit: mm
3.65
0.3
10.0 ± 0.5
M
4.35 ± 0.5
Package Outline
0.25
0° to 9°
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm.
ILX551A
Sony Corporation