ILX506 5000-pixel CCD Linear Image Sensor (B/W) For the availability of this product, please contact the sales office. Description The ILX506 is a reduction type CCD linear sensor developed for high resolution facsimiles and copiers. This sensor reads A3-size documents at a density of 400 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition, reset pulse can be switched between internal generation and external input. 22 pin DIP (Ceramic) Features • Number of effective pixels: 5000 pixels • Pixel size: 7µm × 7µm (7µm pitch) • Built-in timing generator and clock-drivers • Ultra low lag/ultra high sensitivity/low dark output • Single output method • Maximum clock frequency: 12.5MHz Absolute Maximum Ratings • Supply voltage VDD1 VDD2 • Operating temperature • Storage temperature 11 6 –10 to +60 –30 to +80 V V °C °C Pin Configuration (Top View) 22 φCLK VGG 1 GND 2 21 VDD1 VDD1 3 20 RS/SH VOUT 4 19 VDD1 GND 5 18 VDD1 φROG 6 17 GND VDD2 7 16 VDD2 VDD2 8 15 GND RSSW 9 14 T4 13 T3 12 T2 1 T1 10 GND 11 5000 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92239B78-PS VDD1 6 11 10 20 9 22 8 7 5 Read out gate pulse generator 3 Mode selector 2 Clock-drivers CCD analog shift register Read out gate 12 GND Clock pulse generator Sample-and-hold pulse generator VDD1 VDD1 1 D17 GND VGG VDD1 AAAA AA D18 VDD2 4 Read out gate 13 D29 VDD2 VOUT . CCD analog shift register Clock-drivers 14 GND 15 T2 φCLK D30 RSSW D33 RS/SH • Output amplifier • Sample-and-hold circuit • Feed through suppression circuit 16 GND 17 S1 VDD2 D28 T4 S2 18 S4999 T3 S5000 19 D32 T1 D31 21 D34 GND –2– φROG Block Diagram ILX506 ILX506 Pin Description Pin No. Symbol Description 1 VGG Output circuit gate bias 2 GND GND 3 VDD1 9V power supply 4 VOUT Signal output 5 GND GND 6 φROG Clock pulse 7 VDD2 5V power supply 8 VDD2 9 5V power supply ∗ 1 RSSW Reset pulse switchover pin 10 T1 Test pin (5V) 11 GND GND 12 T2 Test pin (GND) 13 T3 Test pin (5V) 14 T4 Test pin (GND) 15 GND GND 16 VDD2 5V power supply 17 GND GND 18 VDD1 9V power supply 19 VDD1 9V power supply 20 RS/SH∗1 Clock pulse or with S/H; without S/H switch 21 VDD1 9V power supply 22 φCLK Clock pulse ∗1 Output mode is changeable as follows. 20pin GND VDD1 φRS GND Internal RS without S/H Internal RS with S/H — VDD1 — — External RS without S/H 9pin –3– ILX506 Recommended Voltage Item Min. Typ. Max. Unit VDD1 8.5 9.0 9.5 V VDD2 4.75 5.0 5.25 V Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V). Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φCLK pin CφCLK — 10 — pF Input capacity of φROG pin CφROG — 10 — pF Input capacity of RS/SH pin CRS/SH — 10 — pF Frequency of φCLK fφCLK — 1 12.5 MHz Frequency of φRS fφRS — 1 12.5 MHz –4– ILX506 Electro-optical Characteristics (Note 1) (Ta = 25°C, VDD1 = 9V, VDD2 = 5V, φCLK = 1MHz, Internal φRS mode without S/H, Light source = 3200K, IR cut filter, CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 7.5 10.8 13.9 V/(lx · s) Note 2 Sensitivity 2 R2 — 24.6 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 4 10 % Note 4 Saturation output voltage VSAT 1.0 1.5 — V Note 5 Saturation exposure SE 0.072 0.139 — lx · s Note 6 Even and odd black level DC difference ∆V — 1.0 10.0 mV Note 7 Dark voltage average VDRK — 0.3 2 mV Note 8 Dark signal nonuniformity DSNU — 0.6 3 mV Note 9 Image lag IL — 0.02 — % Note 10 9V supply current IVDD1 — 16 32 mA — 5V supply current IVDD2 — 3 7 mA — Total transfer efficiency TTE 92 98 — % — Output impedance ZO — 600 — Ω — Offset level VOS — 3.0 — V Note 11 Dynamic range DR 500 5000 — — Note 12 Notes) 1) In accordance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12 to D14. The odd black level is defined as the mean value of D7 , D9, D11 and D13. 2) For the sensitivity test light is applied with a uniform intensity of illumination. 3) W lamp (2854K) 4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX – VMIN)/2 × 100 [%] VAVE Where the 5000 pixels are divided into blocks of 100, even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. 5) Use below the minimum value of the saturation output voltage. 6) Saturation exposure is defined as follows. SE = VSAT R1 7) Indicates the DC difference in value between odd black level and even black level. 8) Optical signal accumulated time τ int stands at 10ms. –5– ILX506 9) The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms. 10) VOUT = 500mV (Typ.) 11) Vos is defined as indicated below. Vout VOS GND 12) Dynamic range is defined as follows. DR = VSAT VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. –6– 0.01µ 5V 9V –7– 0.01µ 10µ/16V φCLK Application Circuit∗ (A) GND 2 20 1kΩ (A) VDD1 3 19 (A) VOUT 4 VDD1 (A) 18 (A) GND 5 VDD1 (A) 17 6 φROG GND (D) 16 φROG (D) VDD2 7 VDD2 (D) 15 (D) VDD2 8 GND (D) 14 (D) RSSW 9 T4 (D) 13 (D) T1 10 T3 (D) 12 (A) GND 11 T2 (D) 0.01µ 10µ/10V noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and ( When ) pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance. ∗ This application circuit shows when φRS is used externally. 2SA1175 RS/SH (D) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Output signal 10µ/16V (A) VGG 1 21 VDD1 (D) 22 φCLK φRS ILX506 VOUT φRS φCLK 0 5 0 5 0 1 D1 φROG 2 3 4 –8– Optical black (28 pixels) D14 D15 D16 D17 D18 AAAAA AA AAAAAA AAAAA Dummy signal (6 pixels) 2 1 ∗ This clock timing diagram shows when φRS is used externally. Effective picture elements signal (5000 pixels) D26 D27 D28 S1 S2 S3 S4 1-line output period (5034 pixels) Dummy signal (28 pixels) D2 D3 D4 D5 D6 5 5034 S4997 S4998 S4999 S5000 D29 D30 D31 D32 D33 D34 Clock Timing Diagram∗ ILX506 ILX506 Clock Pulse Waveform Conditions φCLK, φROG pulse related t8 t9 t2 φROG t1 φCLK t3 Internal φRS mode t8 t9 t4 φCLK Vout t5 AAAA AAAA AAA AAA t10 t10 t11 External φRS mode φCLK t4 t5 t9 φRS t7 t8 t6 AAAA AAAA t12 –9– t13 AAA AAA t10 ILX506 Item Symbol Min. Typ. Max. Unit φROG, φCLK pulse timing t1 100 200 — ns φROG, φCLK pulse timing t3 800 1000 — ns φROG pulse high level period t2 800 — ns φCLK pulse high level period t4 40 1000 500∗1 — ns 500∗1 — ns φCLK pulse low level period t5 40 φRS pulse low level period t6 25 φCLK, φRS pulse timing t7 60 Input clock pulse rise/fall time t8, t9 — 5 10 ns High level VφCLK, VφROG 4.5 5.0 5.5 V Low level VφRS 0 — 0.5 V t10 — 95 — ns t11 — 70 — ns t12 — 45 — ns t13 — 60 — ns Input clock pulse voltage Internal φRS Signal output delay time External φRS ∗1 Recommended condition during φCLK = 1MHz. – 10 – ns 100∗1 — ∗ 1 550 10 + t4 + t5 ns ILX506 Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 500 600 700 800 Wavelength [nm] 900 1000 MTF of main scanning direction (Standard characteristics) 0 Spatial frequency [cycles/mm] 14.3 28.6 42.9 57.1 71.4 1.0 0.8 MTF 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Normalized spatial frequency Dark signal output temperature characteristics (Standard characteristics) 1.0 Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 1 0.5 0.1 0 10 20 30 40 50 Ta – Ambient temperature [°C] 1 60 – 11 – 5 τ int – Integration time [ms] 10 ILX506 Operational frequency characteristics of the VDD2 supply current (Standard characteristics) IVDD2 – VDD2 supply current [mA] IVDD1 – VDD1 supply current [mA] Operational frequency characteristics of the VDD1 supply current (Standard characteristics) 15 10 5 0 40 30 20 10 0 0 2 4 6 8 10 fφCLK – φCLK clock frequency [MHz] 0 12.5 Offset level vs. VDD1 characteristics (Standard characteristics) 2 4 6 8 10 fφCLK – φCLK clock frequency [MHz] Offset level vs. VDD2 characteristics (Standard characteristics) 6 6 Ta = 25°C Ta = 25°C 5 Vos – Offset level [V] 5 4 3 2 ∆Vos ∆VDD1 4 3 2 ∆Vos ∆VDD2 0.35 1 –0.14 1 0 0 8.5 9 9.5 4.75 VDD1 [V] 5 VDD2 [V] Offset level vs. Temperature characteristics (Standard characteristics) 6 5 Vos – Offset level [V] Vos – Offset level [V] 12.5 4 3 2 ∆Vos ∆Ta –0.8mV/°C 1 0 0 10 30 50 20 40 Ta – Ambient temperature [°C] – 12 – 60 5.25 ILX506 Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficienty. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 13 – – 14 – H 1st. pin index V 8.2 ± 0.8 1 22 Ceramic TIN PLATING 42 ALLOY 3.9g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 2.54 No.1 pixel 0.3 M 49.0 ± 0.5 35.0 (7µm × 5000Pixels) PACKAGE MATERIAL PACKAGE STRUCTURE 4.0 ± 0.5 5.0 ± 0.5 0.97 11 12 0.51 22pin DIP (400mil) 8.1 2.3 Unit: mm 10.0 ± 0.5 3.1 ± 0.5 Package Outline (AT STAND OFF) 10.16 0° to 9° 0.25 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 1.42 ± 0.3mm. ILX506