ILX526A 3000-pixel CCD Linear Image Sensor (B/W) Description The ILX526A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. Features • Number of effective pixels: 3000 pixels • Pixel size: 7µm × 200µm (7µm pitch) • Single 5V power supply • High sensitivity: 300V/(lx · s) • Built-in timing generator and clock-drivers • Built-in sample-and-hold circuit • Electrical shutter function • Clock frequency: 100kHz (Min), 1MHz (Max) 15 NC VDD 9 12 S/HSW φSHUT φROG φCLK 7 6 2 Clock pulse generator Clock-drivers Readout gate CCD analog shift register Clock-drivers 14 22 1 13 GND VOUT 20 NC 11 14 VDD 3000 Vgg T1 10 T1 16 NC GND 8 S/HSW φSHUT 7 10 18 NC 17 NC 12 NC 5 φROG 6 AA 19 NC Output Amplifier S/H circuit NC 4 21 21 GND 20 VOUT GND 1 NC 3 D24 D25 φCLK 2 22 VDD CCD analog shift register Readout gate Vgg 1 Readout gate pulse generator Shutter pulse generator 8 9 13 GND VDD GND VDD VDD Pin Configuration (Top View) D54 D55 S1 S2 S3 V °C °C D65 6 –10 to +60 –30 to +80 Internal Structure S2999 S3000 D56 Absolute Maximum Ratings • Supply voltage VDD • Operating temperature • Storage temperature 22 pin DIP (Cer-DIP) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97803-PS ILX526A Pin Description Pin No. Symbol Description 1 Vgg Output circuit gate bias 2 φCLK Clock pulse input 3 NC NC 4 NC NC 5 NC NC 6 φROG Readout gate pulse input 7 φSHUT Electrical Shutter pulse input 8 GND GND 9 VDD 5V 10 T1 TEST 11 NC NC 12 S/HSW Switch (with S/H or without S/H) 13 GND GND 14 VDD 5V 15 NC NC 16 NC NC 17 NC NC 18 NC NC 19 NC NC 20 VOUT Signal output 21 GND GND 22 VDD 5V Mode Description Mode in Use 12 pin S/HSW With S/H GND Without S/H VDD Recommended Voltage Item Min. Typ. Max. Unit VDD 4.5 5.0 5.5 V Input Pin Capacity Item Symbol Min. Typ. Max. Unit Input capacity of φCLK pin CφCLK — 10 — pF Input capacity of φROG pin CφROG — 10 — pF Input capacity of φSHUT pin CφROG — 10 — pF –2– ILX526A Electro-optical Characteristics (Note 1) Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Without S/H mode Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 210 300 390 V/(lx · s) Note 2 Sensitivity 2 R2 — 3700 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 5.0 10.0 % Note 4 Saturation output voltage VSAT 0.6 0.8 — V — Dark voltage average VDRK — 2.5 6.0 mV Note 5 Dark signal nonuniformity DSNU — 5.0 12.0 mV Note 6 Image lag IL — 5.0 — % Note 7 Dynamic range DR — 320 — — Note 8 Saturation exposure SE — 0.003 — lx · s Note 9 5V current consumption IVDD — 7.0 17.0 mA — Total transfer efficiency TTE 92.0 97.0 — % — Output impedance ZO — 250 — Ω — Offset level VOS — 2.5 — V Note 10 Note) 1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D24, D26 to D52. The odd black level is defined as the average value of D25 , D27 to D53. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. Light source: LED λ = 660nm 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = 5. 6. 7. 8. (VMAX – VMIN)/2 VAVE × 100 [%] Where the 3000 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE. Integration time is 10ms. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. Integration time is 10ms. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. VSAT DR = VDRK When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. VSAT 9. SE = R1 10. Vos is defined as indicated below. VOUT D51 D52 D53 VOS AAA AAA AA AAAAAAAA D54 GND –3– D55 S1 –4– 0 5 0 0 –1 D0 3100 or more clock pulses are required. VOUT φCLK φSHUT 5 0 1 D1 φROG D2 5 2 Clock Timing Diagram (With S/H mode) D53 D24 D22 D23 D21 D4 S2997 S2998 S4 Effective picture elements signal (3000 pixels) S3 S2 D55 S1 D54 1-Line output period (3066 pixels) Dummy signal (55 pixels) Optical black (30 pixels) D63 D62 D60 D61 D59 Dummy signal (10 pixels) ILX526A D65 D64 D57 D58 S3000 D56 S2999 D3 –5– 0 5 0 –1 D0 3100 or more clock pulses are required. VOUT φCLK φSHUT 5 0 1 D1 5 2 D2 φROG D3 0 Clock Timing Diagram (Without S/H mode) D52 D24 D22 D23 D21 S2 D55 S1 D54 D53 S2998 S2997 S3 Effective picture elements signal (3000 pixels) 1-Line output period (3066 pixels) Dummy signal (55 pixels) Optical black (30 pixels) D62 D63 D60 D61 D59 Dummy signal (10 pixels) ILX526A D65 D64 D58 D56 D57 S3000 S2999 D4 ILX526A Input Clock Voltage Condition Min. Typ. Max. Unit VIH 4.5 VDD 5.5 V VIL 0.0 — 0.1 V Item ∗ This is applied to the all external pulses. (φCLK, φROG, φSHUT) φCLK Timing (For all modes) t1 t2 φCLK t3 t4 Item Symbol φCLK pulse rise/fall time φCLK pulse Duty∗1 Min. Typ. Max. Unit 0 10 100 ns 40 50 60 % Min. Typ. Max. Unit (1/8) τ (1/4) τ (3/8) τ ns (1/8) τ (1/4) τ (3/8) τ ns 0 10 100 ns 6τ 10τ 20τ ns t1, t2 — ∗1 100 × t4/ (t3 + t4) φROG, φCLK Timing φROG t6 t7 t8 φCLK t5 t9 Item φROG, φCLKpulse timing 1 φROG, φCLKpulse timing 2 φROG pulse rise/fall time φROG pulse period Symbol t5 t9 t6, t8 t7 Note) τ is the period of φCLK. –6– ILX526A φSHUT, φCLK Timing φSHUT t12 t11 t13 t14 φCLK t15 Item Symbol φSHUT pulse rise/fall time t11, t13 t12 t14 t15 φSHUT pulse period φSHUT, φCLK pulse timing 1 φSHUT, φCLK pulse timing 2 Min. Typ. Max. Unit 0 10 100 ns 4000 5000 — ns 150 200 250 ns 150 200 250 ns Min. Typ. Max. Unit 10τ — — ns φROG, φSHUT Timing φROG t16 t17 φSHUT Item φROG, φSHUT pulse timing Symbol t16, t17 –7– ILX526A φCLK-VOUT Timing ∗1 ∗2 φCLK t18 VOUT∗3 t19 VOUT Item Symbol φCLK-VOUT output delay time1 t18 t19 φCLK-VOUT output delay time2 Min. Typ. Max. Unit — 230 — ns — 210 — ns ∗1 fck = 500kHz, φCLK Duty = 50%, φCLK rise/fall time = 10ns ∗2 is data period ∗3 Using internal sample-and-hold circuit Application Circuit (Without S/H mode (Note)) 5V 1 φCLK φROG φSHUT Vgg VDD 22 2 φCLK GND 21 3 NC VOUT 20 NC NC 19 5 NC NC 18 6 φROG NC 17 4 7 φSHUT 8 GND 9 VDD 0.01µ 22µ/10V 3kΩ 2SA1175 NC 16 NC 15 VDD 14 10 T1 GND 13 11 NC S/HSW 12 Note) This circuit diagram is the case when internal S/H is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –8– ILX526A Example of Representative Characteristics (VDD = 5V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 10 9 Relative sensitivity 8 7 6 5 4 3 2 1 0 400 500 600 700 800 900 1000 Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) 10 Output voltage rate 5 1 0.5 0.1 0.05 0.01 –10 0 10 20 30 Ta – Ambient temperature [°C] –9– 40 50 60 ILX526A Offset level vs. Temperature characteristics (Standard characteristics) Offset level vs. VDD characteristics (Standard characteristics) 5 5 ∆VOS ∆Ta Ta = 25°C –2.1mV/°C 4 VOS – Offset level [V] VOS – Offset level [V] 4 3 2 1 3 2 1 ∆VOS ∆VDD 0 –10 0 10 20 30 40 50 0 4.5 60 0.49 5 5.5 Ta – Ambient temperature [°C] VDD [V] Supply current vs. VDD characteristics (Standard characteristics) Output voltage vs. Integration time (Standard characteristics) 14 10 Ta = 25°C 10 Output voltage rate IVDD – Supply current [mA] 12 8 6 4 5 2 0 4.5 5 1 10 5.5 50 τ – Integration time [ms] VDD [V] – 10 – 100 ILX526A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N (2) (3) 0.9Nm (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 11 – ILX526A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. – 12 – 5.0 ± 0.5 – 13 – 1 V 22 H 5.5 ± 0.8 2.54 32.0 ± 0.5 Cer-DIP TIN PLATING 42 ALLOY 3.0g PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 30.6 21.0 (7µm × 3000Pixels) No.1 Pixel PACKAGE STRUCTURE 4.0 ± 0.5 11 12 0.51 22pin DIP (400mil) 9.0 2.7 Unit: mm 10.0 ± 0.5 0.3 3.4 ± 0.5 Package Outline M 0° to 9° 0.25 (AT STAND OFF) 10.16 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. ILX526A