TN1504/TN1506/TN1510 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Features ► ► ► ► ► ► ► ► General Description These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors, and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Low threshold - 2.0V max. High input impedance Low input capacitance - 50pF typical Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► ► Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-source voltage BVDGS Drain-to-source voltage ±20V Operating and storage temperature O -55 C to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Ordering Information Device Order Number Die* BVDSS/ BVDGS RDS(ON) (max) VGS(th) (max) ID(ON) (min) TN1504 TN1504NW 40V 3.0Ω 2.0V 2.0A TN1506 TN1506NW 60V 3.0Ω 2.0V 2.0A TN1510 TN1510NW 100V 3.0Ω 2.0V 2.0A * Die in wafer form. 1 TN1504/TN1506/TN1510 Electrical Characteristics (@25 C unless otherwise specified) O Symbol BVDSS Parameter Min Drain-to-source breakdown voltage Typ Max Units - - V VGS= 0V, ID = 1.0mA 0.6 - 2.0 V VGS = VDS, ID = 0.5mA TN1504 40 TN1506 60 TN1510 100 Conditions VGS(th) Gate threshold voltage ∆VGS(th) Change in VGS(th) with temperature - -3.8 -5.0 mV/OC VGS = VDS, ID = 1.0mA IGSS Gate body leakage - 0.1 100 nA VGS = ±20V, VDS = 0V IDSS Zero gate voltage drain current - - VGS =0V, VDS = Max Rating 10 μA 500 ID(ON) RDS(ON) ON-state drain current Static drain-to-source ON-state resistance VGS = 0V, VDS = 0.8 Max Rating TA = 125OC - 1.4 - - 3.4 - - 2.0 4.5 - 1.6 3.0 - 0.6 1.1 %/OC VGS = 10V, ID = 0.5A 225 400 - mmho VDS = 25V, ID = 500mA ∆RDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 50 60 COSS Common source output capacitance - 25 35 CRSS Reverse transfer capacitance - 4.0 8.05 td(ON) Turn-ON delay time - 2.0 5.0 tr Rise time - 3.0 5.0 td(OFF) Turn-OFF delay time - 6.0 7.0 tf Fall time - 3.0 6.0 VSD Diode forward voltage drop - 1.0 trr Reverse recovery time - 400 A Ω VGS = 5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 250mA VGS = 10V, ID = 500mA pF VGS = 0V, VDS = 25V f = 1 MHz ns VDD = 25V, ID = 1.0A RGEN = 25Ω 1.5 V VGS = 0V, ISD = 0.5A - ns VGS = 0V, ISD = 0.5A Notes: 1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD t(OFF) tr 10% td(OFF) tF D.U.T. 10% INPUT 90% OUTPUT RGEN OUTPUT 0V RL 90% Doc.# DSFP-TN1504/TN1506/TN1510 062706 2