TP2424 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS / RDS(ON) VGS(th) BVDGS (max) (max) (min) TO-243AA* Die -240V 8.0Ω -2.4V -800mA TP2424N8 TP2424ND * Same as SOT-89. ID(ON) Product supplied on 2000 piece carrier tape reels. Product marking for TO-243AA: TP4C❋ where ❋ = 2-week alpha date code Features ❏ Low threshold ❏ High input impedance Low Threshold DMOS Technology ❏ Low input capacitance These low threshold enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. ❏ Fast switching speeds ❏ Free from secondary breakdown ❏ Low input and output leakage ❏ Complementary N- and P-channel devices Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ❏ Logic level interfaces – ideal for TTL and CMOS ❏ Solid state relays ❏ Linear Amplifiers Package Option ❏ Power Management ❏ Analog switches ❏ Telecom switches Absolute Maximum Ratings D G Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage ± 20V Operating and Storage Temperature Soldering Temperature* D S TO-243AA (SOT-89) -55°C to +150°C 300°C * Distance of 1.6 mm from case for 10 seconds. Note: See Package Outline section for dimensions. 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 TP2424 Thermal Characteristics Package ID (continuous)* TO-243AA ID (pulsed) -316mA Power Dissipation θjc θja @ TA = 25°C °C/W °C/W 1.6W† 15 78† -1.9A IDR* IDRM -316mA -1.9A * ID (continuous) is limited by max rated Tj. † Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substrate. Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min Typ BVDSS Drain-to-Source Breakdown Voltage -240 VGS(th) Gate Threshold Voltage -1.0 ∆VGS(th) Change in VGS(th) with Temperature IGSS Gate Body Leakage IDSS Zero Gate Voltage Drain Current ID(ON) ON-State Drain Current Max Unit V VGS = 0V, ID = -250µA -2.4 V VGS = VDS, ID= -1.0mA 4.5 mV/°C VGS = VDS, ID= -1.0mA -100 nA VGS = ± 20V, VDS = 0V -10.0 µA VGS = 0V, VDS = Max Rating -1.0 mA VGS = 0V, VDS = 0.8 Max Rating TA = 125°C -0.3 A -0.8 VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V Static Drain-to-Source ON-State Resistance 10.0 ∆RDS(ON) Change in RDS(ON) with Temperature 0.75 GFS Forward Transconductance CISS Input Capacitance 200 COSS Common Source Output Capacitance 100 CRSS Reverse Transfer Capacitance 40 td(ON) Turn-ON Delay Time 20 tr Rise Time 30 td(OFF) Turn-OFF Delay Time 35 tf Fall Time 25 VSD Diode Forward Voltage Drop trr Reverse Recovery Time Ω 8.0 150 VGS = -10V, ID = -500mA %/°C VGS = -10V, ID = -500mA VDS = -25V, ID = -200mA m -1.5 300 VGS = -4.5V, ID = -150mA Ω RDS(ON) Conditions pF VGS = 0V, VDS = -25V f = 1.0 MHz ns VDD = -25V, ID = -250mA, RGEN = 25Ω V VGS = 0V, ISD = -500mA ns VGS = 0V, ISD = -500mA Notes: 1.All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% PULSE GENERATOR INPUT 90% -10V t(ON) td(ON) Rgen t(OFF) td(OFF) tr tF D.U.T. 0V 90% OUTPUT INPUT 90% RL OUTPUT VDD 10% 10% VDD ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 2 11/12/01 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com