MAXIM DS3205DN+

Rev: 111607
DS3205
Hot-Swappable Bus Buffer for
I2C, SMBus, IPMI, and ATCA
Features
General Description
The DS3205 bus buffer enables hot insertion and
extraction of boards without corruption of the
backplane’s 2-wire bus (I2C, SMBus™, IPMI, etc.).
When a board is inserted, the DS3205 presents highimpedance SCL and SDA connections to the
backplane until VDD rises above 2.5V. During normal
operation, the DS3205 provides bidirectional
buffering to keep backplane and board capacitances
isolated.
Rise-time accelerators on each 2-wire bus pin enable
the use of lower current pullup resistors while still
meeting rise-time requirements.
Applications
Hot-Swappable Boards for AdvancedTCA®,
CompactPCI®, VME, and Other Backplanes in
Chassis-Oriented Telecom, Datacom,
Computing, and Storage Systems
Capacitance Buffer
Bus Extender
Fault Isolator
Ordering Information
PART
TEMP RANGE
DS3205DN+
-40°C to +85°C
PINPACKAGE
14 TDFN
PKG
CODE
T1433-1
2
♦
Compliant to PICMG 3.0 IPMI I C Requirements
♦
Bidirectional Buffer for SCL and SDA Lines
♦
Compatible with I2C, I2C Fast Mode, SMBus,
IPMI, and ATCA® Standards (Up to 400kHz)
♦
Prevents Corruption of System SCL and SDA
Lines During Live Insertion/Removal of Boards
♦
Increases Fanout by Connecting Board Bus to
Backplane Bus with < 10pF Additional Load
♦
Automatically Delays Initial Bus Connection
Until Both Bus Segments Are Idle
♦
SCL and SDA Pins High-Z When VDD = 0V
♦
1V Precharge on SCL and SDA Lines
♦
ENABLE Input Pin Connects or Isolates Buses
♦
READY Output Pin Indicates “Connected”
♦
FAULT Output Pin Indicates “Stuck Bus”
♦
Optional Rise-Time Accelerators on All Bus
Pins
♦
Configurable Rise-Time Accelerator Slew Rate
Threshold (0.8V/μs or 1.25V/μs)
♦
Supports Clock Stretching and Multiple Bus
Master Arbitration and Synchronization
♦
Optionally Disconnects Board from Backplane
When Bus is Stuck Low for ≥ 30ms
♦
Optionally Attempts to Recover a Stuck Bus by
Clocking Board SCL
♦
±15kV ESD Protection (Human Body Model) on
Bus Pins
♦
Wide Operating Voltage Range: 2.7V to 5.5V
♦
5V Tolerant I/Os
♦
Tiny 14-Pin, 3mm x 3mm TDFN Package
+Denotes a lead-free package.
SMBus is a trademark of Intel Corp.
ATCA, AdvancedTCA, and CompactPCI are registered trademarks of PCI Industrial Computer Manufacturers Group (PICMG).
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
____________________________________________________________________________________________ DS3205
Table of Contents
1.
TYPICAL ATCA APPLICATION ......................................................................................................5
2.
APPLICABLE DIAGRAMS ..............................................................................................................6
3.
PIN DESCRIPTIONS ........................................................................................................................9
4.
FUNCTIONAL DESCRIPTION .......................................................................................................11
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.
OVERVIEW ....................................................................................................................................11
STARTUP ......................................................................................................................................11
RISE-TIME ACCELERATORS ...........................................................................................................11
READY OUTPUT PIN.....................................................................................................................11
ENABLE INPUT PIN ......................................................................................................................11
STUCK BUS CONDITION .................................................................................................................11
BUS CAPACITANCE REQUIREMENTS ...............................................................................................12
PULLUP RESISTOR ........................................................................................................................12
OPERATING PARAMETERS ........................................................................................................13
5.1
ELECTRICAL CHARACTERISTICS .....................................................................................................13
6.
PIN CONFIGURATION ..................................................................................................................16
7.
PACKAGE INFORMATION ...........................................................................................................17
7.1
14-PIN TDFN WITH EXPOSED PAD (21-0137) ................................................................................17
8.
THERMAL INFORMATION ............................................................................................................19
9.
DATA SHEET REVISION HISTORY..............................................................................................20
Rev: 111607
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____________________________________________________________________________________________ DS3205
List of Figures
Figure 1-1. Typical Application (ATCA Blade) ............................................................................................................. 5
Figure 2-1. Block Diagram ........................................................................................................................................... 6
Figure 2-2. Backplane-to-Card Connection Detail....................................................................................................... 7
Figure 2-3. DS3205 State Diagram ............................................................................................................................. 8
Figure 6-1. 14-Pin TDFN with Exposed Pad Pin Configuration................................................................................. 16
Rev: 111607
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____________________________________________________________________________________________ DS3205
List of Tables
Table 3-1. Pin Descriptions.......................................................................................................................................... 9
Table 5-1. Power Supply ........................................................................................................................................... 13
Table 5-2. Startup Characteristics ............................................................................................................................. 13
Table 5-3. I2C Bus Pins Characteristics..................................................................................................................... 14
Table 5-4. Device Control Pins Characteristics ......................................................................................................... 14
Table 5-5. Timing Characteristics .............................................................................................................................. 15
Table 8-1. Thermal Properties—14-Pin TDFN Package ........................................................................................... 19
Rev: 111607
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____________________________________________________________________________________________ DS3205
1.
Typical ATCA Application
Figure 1-1 shows an ATCA blade application for the DS3205. In this application the DS3205 is used as a buffer for
the Intelligent Platform Management Bus (IPMB). The IPMB is used in ATCA for communications between and
management of all Field Replaceable Units (FRUs). The DS3205 is compliant with the ATCA IPMB requirements
as specified in PICMG 3.0 AdvancedTCA Base Requirements.
Figure 1-1. Typical Application (ATCA Blade)
Backplane
Connector
Blade connector with multiple pin lengths provides "Staged" contact.
Power and ground connect first, then SCL/SDA, then ENABLE last.
3.3V
BACKPLANE_SCL
10k
BACKPLANE_SDA
DS3205
VCC
SCLIN
SCLOUT
SDAIN
SDAOUT
10k
BOARD_SCL
10k
BOARD_SDA
READY
FAULT
ACOE
ENABLE
GND
0.01µF
ASR
ACIE
SBDIS
SBCLK
5V
10k
100k
Rev: 111607
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____________________________________________________________________________________________ DS3205
2.
Applicable Diagrams
Figure 2-1. Block Diagram
BACKPLANE-TO-CARD
CONNECTION
SCLIN
SCLOUT
ASR
ACOE
DS3205
ACIE
BACKPLANE-TO-CARD
CONNECTION
SDAIN
SDAOUT
1 VOLT
PRE-CHARGE
150K
150K
150K
150K
READY
PRE
CONNECT
FORCE
CLOCKING
+
+
-
-
+
-
STOP BIT, BUS IDLE,
AND CONNECT STATE
MACHINE
+
-
SBDIS
FAULT
SBCLK
ENABLE
VSS
UNDER VOLTAGE
DETECTION
VREF
Rev: 111607
VDD
6 of 20
____________________________________________________________________________________________ DS3205
Figure 2-2. Backplane-to-Card Connection Detail
SxIN
SxOUT
fast ena
SLEW RATE
DETECT
acc
acc
ena fast
SLEW RATE
DETECT
150k
150k
+
+
-
-
SxIN
ACIR ASR
REF REF
PRECHARGE
Rev: 111607
ACOE
SxOUT
FORCE
CLOCK
7 of 20
____________________________________________________________________________________________ DS3205
Figure 2-3. DS3205 State Diagram
INITIAL
130µs
stuck bus = 1 & SBCLK = 1
& SBDIS = 0
precharge
on
STUCK BUS
CLOCKING
BUS WAIT
(input stop +
input idle) &
output high
Hi Z off
READY = 1
FORCE 16
CLOCKS AT
SCLOUT PIN
stuck bus = 0 +
SBCLK = 0
stuck bus = 0 +
(SBCLK = 0 &
SBDIS = 0)
COMPLETED
16 FORCED
CLOCKS
STUCK BUS
DISCONNECT
ACTIVE
stuck bus = 1 &
SBCLK = 0 &
SBDIS = 1
input stop = rising edge on SDAIN while SCLIN high
input idle = SDAIN and SCLIN high for 140µs
stuck bus = SDAOUT or SCLOUT low for 30ms
Rev: 111607
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____________________________________________________________________________________________ DS3205
3.
Pin Descriptions
Table 3-1. Pin Descriptions
NAME
PIN
TYPE
FUNCTION
Enable Input. This input pin establishes the board-to-backplane connection when
driven to a level above VDD/2 (approximately) with 50mV hysteresis.
0 = Disable connection and enter low-power mode.
1 = Enable connection of backplane and board buses.
ENABLE
1
I
SCLOUT
2
I/O
Serial Clock Output. This pin is connected to the board’s SCL signal.
SDAOUT
3
I/O
Serial Data Output. This pin is connected to the board’s SDA signal.
ACIE
ACOE
4
5
I
Accelerator Current on Inputs Enable. This input pin enables/disables the risetime accelerators on the bus input pins.
0 = Disable rise-time accelerator on SCLIN and SDAIN.
1 = Enable rise-time accelerator on SCLIN and SDAIN.
I
Accelerator Current on Outputs Enable. This input pin enables/disables the risetime accelerators on the bus output pins.
0 = Disable rise-time accelerator on SCLOUT and SDAOUT.
1 = Enable rise-time accelerator on SCLOUT and SDAOUT.
ASR
6
I
Accelerator Slew Rate Threshold Select. This input pin selects the rate for the
rise-time accelerators.
0 = 0.8V/μs
1 = 1.25V/μs
VSS
7
P
Ground
READY
FAULT
SBCLK
SBDIS
Rev: 111607
8
9
10
11
Ood
Connected Status Indicator. This is an open-drain output that goes high when the
device is in the ACTIVE state. See the state diagram in Figure 2-3. This pin should
have an external 10kΩ pullup resistor.
0 = Backplane and board buses not connected.
1 (float) = Backplane and board buses connected.
Ood
Active-Low Bus Fault Indicator. This open-drain output pin indicates a “stuck bus”
condition when = 0. This pin should have an external 10kΩ pullup resistor.
0 = Either SCLOUT or SDAOUT has been low > 30ms.
1 = No stuck bus fault.
I
Stuck Bus Clocking Enable. Asserting this pin high causes the DS3205 to drive
clock pulses onto the SCLOUT pin in an attempt to free a stuck bus when a “stuck
bus” condition has been detected. See Section 4 and Figure 2-3 for more information
on the stuck bus condition.
0 = Disable automatic clocking during stuck bus fault.
1 = Enable automatic clocking during stuck bus fault.
Note: Asserting both SBDIS and SBCLK high at the same time is not valid and can
produce unwanted results.
I
Stuck Bus Disconnect Enable. Asserting this pin high causes the DS3205 to
disconnect the backplane signals from the board signals when a “stuck bus”
condition has been detected. See Section 4 and Figure 2-3 for more information on
the stuck bus condition.
0 = Disable automatic disconnect on stuck bus fault.
1 = Enable automatic disconnect on stuck bus fault.
Note: Asserting both SBDIS and SBCLK high at the same time is not valid and can
produce unwanted results.
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____________________________________________________________________________________________ DS3205
NAME
PIN
TYPE
SDAIN
12
I/O
Serial Data Input. This pin is connected to the backplane SDA signal.
SCLIN
13
I/O
Serial Clock Input. This pin is connected to the backplane SCL signal.
VDD
14
P
Power Supply. 2.7V to 5.5V
EP
—
—
Exposed Pad
I/O
I
Ood
P
=
=
=
=
Rev: 111607
FUNCTION
Input/Output
Input
Output, Open Drain
Power
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____________________________________________________________________________________________ DS3205
4.
Functional Description
4.1
Overview
See the DS3205 state diagram in Figure 2-3.
4.2
Startup
When the DS3205 is first powered on, it is in a low-power state with the SCLIN, SCLOUT, SDAIN, and SDAOUT
pins in a high-impedance state. If the ENABLE pin is pulled high, the DS3205 waits until the supply voltage rises
above approximately 2V, when the precharge circuitry becomes active and forces 1V through 150kΩ resistors into
all SCL and SDA pins. The 1V precharge minimizes bus disturbances when the backplane and card are at
opposing logic levels. The DS3205 then waits about 130μs for the external connections and internal circuitry to
settle. After this wait time, the DS3205 enters the BUS WAIT state where it looks for either a stop bit on the input
(rising edge on the SDAIN pin while SCLIN remains high) or an input bus idle condition (SDAIN and SCLIN both
high for 140μs) while both SDAOUT and SCLOUT pins are high. Once these conditions are met, the precharge
circuit is turned off and the DS3205 enters the ACTIVE state.
While in the ACTIVE state, the DS3205 establishes a bidirectional connection between the SDAIN and SDAOUT
pins and the SCLIN and SCLOUT pins. The voltage on any bus pin is buffered and offset an additional +75mV
(approximately) to the other side. Whichever side is pulled closest to ground has priority. For example, if SCLOUT
is pulled closer to ground than SCIN, SCIN is driven to a voltage 75mV higher than SCOUT.
4.3
Rise-Time Accelerators
If current acceleration is enabled through the ACIE or ACOE pins, the DS3205 pulls up more strongly, shortening
the rise time compared to using only the external bus pullup resistors. The pullup provided by the driver during
acceleration is approximately 3.5mA instead of its usual 100μA. This acceleration current on one side of the buffer
is activated when the bus voltage on the other side is greater than 0.6V and its slew rate is greater than 0.8V/μs
(ASR low) or 1.2V/μs (ASR high) and the corresponding ACIE and/or ACOE pin is pulled high. The acceleration
current is deactivated after the accelerated bus pin rises within 0.9V of VDD. For example, if the ACOE pin is high,
when the SCLIN pin rises above 0.6V with a fast slew rate, the SCLOUT pin is pulled up towards VDD with more
than 3mA of current. This current ceases when the SCLOUT pin rises to within 0.9V of VDD.
4.4
READY Output Pin
The READY pin is pulled low whenever the DS3205 is not in its ACTIVE state. An external pullup resistor brings
the READY pin high when the bidirectional connection is established.
4.5
ENABLE Input Pin
If the ENABLE pin is pulled low, the backplane side disconnects from the board side and the device enters a lowpower state with the READY pin asserted low. Also, the rise-time accelerators and precharge circuitry are disabled.
Setting ENABLE low causes the device to disconnect the board side from the backplane side and enter the lowpower mode.
4.6
Stuck Bus Condition
If the SDAOUT and SCLOUT pins remain low for 30ms the bus is assumed to be stuck. This 30ms timeout is
restarted only when the SDAOUT and SCLOUT pins are both high. The FAULT pin pulls low and remains low until
the bus is unstuck. If the SBCLK pin is high, the DS3205 attempts to unstick the bus by first disconnecting all SDA
and SCL pins for 50μs, then pulls down on the SCLOUT pin 16 times at a 8kHz rate. If the bus becomes unstuck
during this process (SDAOUT and SCLOUT both go high), the DS3205 returns to the BUS WAIT state. The
precharge circuitry becomes active, and, as soon as a stop bit or bus idle is detected on the input while both
Rev: 111607
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____________________________________________________________________________________________ DS3205
SDAOUT and SCLOUT pins are high, the DS3205 goes to the ACTIVE state, reestablishing bidirectional buffering.
If the bus remains stuck after 16 clocks, the DS3205 sits with all SDA and SCL pins precharged until SDAOUT and
SCLOUT go high. If the SBCLK pin is low and the SBDIS pin is high, the DS3205 only precharges the SDA and
SCL pins until the bus becomes unstuck. If neither SBCLK nor SBDIS are high, the DS3205 remains in its ACTIVE
state, but the FAULT pin pulls low as an alert that the bus is stuck.
If the DS3205 is in the STUCK BUS CLOCKING state, setting the SBCLK pin low forces the part into the BUS
WAIT state. If the DS3205 is in the STUCK BUS DISCONNECT state, setting the SBDIS pin low forces the part
into the BUS WAIT state. These transitions are shown in the state diagram in Figure 2-3. Returning to the BUS
WAIT state resets the 30ms stuck bus counter.
4.7
Bus Capacitance Requirements
A minimum of 47pF bus capacitance is required on 5V systems; 3.3V systems require a minimum of 22pF for
proper operation. Buses with less capacitance should be provisioned with an added capacitor to ground in order to
maintain the minimum required capacitance. The DS3205 tolerates capacitance levels slightly marginal with
respect to these requirements.
4.8
Pullup Resistor
When SCLIN, SCLOUT, SDAIN, or SDAOUT is driven to a logic-low level, that pin's corresponding output pin is
driven to a slightly higher level. For example, if SDAOUT is driven low, SDAIN is driven to a level according to the
following formula.
VSDAIN = VSDAOUT + 75mV + (VDD / R) × 20Ω
EXAMPLE:
IF R = bus pullup resistor = 10kΩ
IF VDD = 3.3V
IF VSDAOUT = 10mV
VSDAIN = 91.6mV (typical)
Rev: 111607
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____________________________________________________________________________________________ DS3205
5.
Operating Parameters
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Respect to VSS (except VDD)…….………………………………………….0.5V to 6.0V
Supply Voltage Range (VDD) with Respect to VSS…….………….……………………………………………0.5V to 6.0V
Operating Temperature Range.…………………………………………………………………….-40°C to +85°C (Note 1)
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Soldering Temperature..………………………………………………Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Ambient operating
temperature range when device is mounted on a four-layer JEDEC test board with no airflow.
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
5.1
Electrical Characteristics
Table 5-1. Power Supply
(VDD = 2.7V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDD
Supply Current
IDD
VDD = 5.5V, VSDAIN =
VSCLIN = 0V
Shutdown Current
ISD
VENABLE = 0V, all other
pins at VDD or VSS
MIN
TYP
MAX
UNITS
5.5
V
4
7
mA
200
500
μA
MIN
TYP
MAX
UNITS
0.75
1.00
1.25
V
VDD /
2
VDD x
0.7
V
2.7
Table 5-2. Startup Characteristics
(VDD = 2.7V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
Precharge Voltage
SYMBOL
VPRE
CONDITIONS
SDA, SCL floating
(Note 1)
ENABLE Threshold Rising
VTHR (EN, RISE)
Enabling
ENABLE Threshold Falling
VTHR (EN, FALL)
Disabling
VDD x
0.3
VDD /
2
V
Enable Time
tEN
ENABLE high ≥ READY
350
420
μs
Disable Time
tDIS
ENABLE low ≥ READY
25
50
ns
Bus Idle Time
tIDLE
350
430
μs
SDAIN to READY After STOP
tSTOP
0.7
1.0
μs
SCLOUT/SDAOUT to
READY
tREADY
0.6
1.0
μs
Rev: 111607
(Note 2)
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____________________________________________________________________________________________ DS3205
Table 5-3. I2C Bus Pins Characteristics
(VDD = 2.7V to 5.5V, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
Input/Output Offset Voltage
VOS
ENABLE Input Current
IEN
ENABLE between VSS and
VDD
CBUS
Applies to SCLIN, SDAIN,
SCLOUT, SDAOUT pins;
signals between -0.5V and
3.65V, VDD between 0V and
5.5V
I2C Capacitance (Note 3)
IOFF (BUS)
ENABLE = VSS or VDD <
VDD,UV
Output Low Open-Drain
Outputs
VOL (OD)
Applies to READY and
FAULT pins, IPULLUP = 3mA
I2C Bus VOUTLOW
VOL (BUS)
IIN = -3mA
I C Bus Clock
TYP
MAX
75
Leakage Current on I2C Pins
2
MIN
UNITS
mV
+1
μA
10
pF
+10
μA
0.4
V
0.3
0.5
V
30
45
ms
-1
3
-10
See Table 5-5
Bus Stuck Low Timer
tSTUCK
SDAOUT or SCLOUT = low
15
Transient-Boosted Pullup
Current
IPULL
Low to high transition on
SDA, SCL pins; VDD = 0.3V
1
mA
Table 5-4. Device Control Pins Characteristics
(VDD = 2.7V to 5.5V, TA = -40°C to +85°C)
PARAMETER
SYMBOL
Logic Input Threshold Voltage
VTHR (LOG)
Logic Input Hysteresis
VHYS
ENABLE Input Threshold
Input Leakage
Leakage Current on
Open-Drain Outputs
Lead Capacitance
Rev: 111607
IIL
IOFF (OD)
CIO
CONDITIONS
Applies to SBDIS, SBCLK,
ASR, ACOE, and ACIE
inputs
Any logic input pin except
ENABLE (Note 3)
See Table 5-2
Applies to SBDIS, SBCLK,
ASR, ACOE, ACIE, and
ENABLE
Applies to READY and
FAULT pins, ENABLE = VSS
READY, ENABLE, SBDIS,
SBCLK, ASR, ACOE, ACIE,
FAULT pins
MIN
TYP
MAX
UNITS
1.6
1.8
2.0
V
50
mV
-10
+10
μA
-10
+10
μA
10
pF
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____________________________________________________________________________________________ DS3205
Table 5-5. Timing Characteristics
(VDD = 2.7V to 5.5V, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
400
kHz
Operating Frequency
fBUS
Bus Free Time Between
START and STOP Condition
fBUF
(Note 3)
1.3
μs
Hold Time After Repeated
START Condition
tHD,START
(Note 3)
0.6
μs
Repeated START Condition
Setup Time
tSU,START
(Note 3)
0.6
μs
STOP Condition Setup Time
tSU,STOP
(Note 3)
0.8
μs
Clock Low Period
tLOW
(Note 3)
1.3
μs
Clock High Period
tHIGH
0.6
μs
Clock-Data Fall Time
tF
(Note 4)
20 +
0.1CB
Clock-Data Rise Time
tR
(Notes 3, 4)
20 +
0.1CB
Note 1:
Applies over full operational temperature range.
Note 2:
Delays that can occur after enable and/or idle time have passed.
Note 3:
Guaranteed by design. Not production tested.
Note 4:
CB = Total capacitance of one bus line (pF).
Note 5:
IPULL varies with temperature and voltage.
Rev: 111607
250
ns
ns
15 of 20
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6.
Pin Configuration
Figure 6-1. 14-Pin TDFN with Exposed Pad Pin Configuration
Rev: 111607
16 of 20
____________________________________________________________________________________________ DS3205
7.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number
provided for each package is a link to the latest package outline information. Go to www.maxim-ic.com/packages.)
7.1
14-Pin TDFN with Exposed Pad (21-0137)
Rev: 111607
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____________________________________________________________________________________________ DS3205
Rev: 111607
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8.
Thermal Information
Table 8-1. Thermal Properties—14-Pin TDFN Package
PARAMETER
VALUE
Target Ambient Temperature Range
-40°C to +85°C
Theta J (Die Junction Temperature Range)
-40°C to +125°C
Rev: 111607
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____________________________________________________________________________________________ DS3205
9.
Data Sheet Revision History
REVISION
DATE
111607
PAGES
CHANGED
DESCRIPTION
—
Initial data sheet release.
Rev: 111607
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are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.