STK14EC8 512Kx8 Autostore nvSRAM Preliminary FEATURES DESCRIPTION • 15, 25, 45 ns Read Access and R/W Cycle Time The Simtek STK14EC8 is a fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Software Control • Automatic RECALL to SRAM on Power Up The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. • Unlimited RECALL Cycles • 200K STORE Endurance • 20-Year Non-volatile Data Retention • Single 3.3V +0.3V, -0.6V Power Supply The Simtek nvSRAM is the highest performance, most reliable non-volatile memory available. • Commercial, Industrial Temperatures • 44-pin 400-mil TSOPII (RoHS-Compliant) BLOCK DIAGRAM VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER POWER CONTROL STORE STATIC RAM ARRAY 2048 X 2048 RECALL STORE/ RECALL CONTROL HSB SOFTWARE DETECT INPUT BUFFERS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VCAP Quantum Trap 2048 X 2048 A18 – A0 COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A5 A6 A7 G E W This is a product in development that has fixed target specifications that are subject to change pending characterization results. Simtek Confidential & Proprietary 1 Document Control #ML0060 Rev 1.0 April, 2007 Preliminary STK14EC8 NC 1 44 HSB NC A0 2 43 NC 3 42 NC A1 4 41 A2 A3 5 40 A18 A17 6 39 A16 A4 7 38 A15 E 8 37 G DQ0 9 36 DQ7 DQ1 VCC VSS 10 35 DQ6 34 12 33 VSS VCC DQ2 13 32 DQ5 DQ3 14 31 DQ4 W A5 15 30 16 29 VCAP A14 A6 17 28 A7 18 27 A8 19 26 A11 11 512K x8 A13 A12 A9 NC 20 25 A10 21 24 NC NC 22 23 NC 44-Pin TSOP-II (See mechanical drawing on Page 18) PIN DESCRIPTIONS Pin Name I/O Description A18-A0 Input Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCC Power Supply Power: 3.0V, +20%, -10% HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). VCAP Power Supply Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground NC No Connect This pin is not connected to the die. (Do not connect in design; reserved for future use) Document Control #ML0060 Rev 1.0 April, 2007 2 Simtek Confidential Preliminary STK14EC8 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .–0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Package Thermal Characteristics - See Website at http://www.simtek.com DC CHARACTERISTICS (VCC = 2.7V-3.6V) COMMERCIAL SYMBOL MIN ICC1 ICC2 ICC3 ICC4 ISB INDUSTRIAL PARAMETER MAX MIN UNITS NOTES tAVAV = 15ns tAVAV = 25ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. MAX Average VCC Current 70 65 50 75 70 52 mA mA mA 3 3 mA All Inputs Don’t Care, VCC = max Average current for duration of STORE cycle (tSTORE) Average VCC Current during STORE 13 13 mA W ≥ (V CC – 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. Average VCAP Current during AutoStore™ Cycle 3 3 mA All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE) VCC Standby Current (Standby, Stable CMOS Levels) 2 2 mA Average VCC Current at tAVAV = 200ns 3V, 25°C, Typical E ≥ (VCC -0.2V) All Others VIN≤ 0.2V or ≥ (VCC-0.2V) Standby current level after nonvolatile cycle complete IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V All Inputs VIL Input Logic “0” Voltage VSS –0.5 0.8 VSS –0.5 0.8 V All Inputs VOH Output Logic “1” Voltage VOL Output Logic “0” Voltage 2.4 2.4 TA Operating Temperature 0 70 V IOUT = – 2mA 0.4 V IOUT = 4mA –40 85 °C 0.4 VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V nominal VCAP Storage Capacitance 37 57 37 57 μF Between VCAP pin and VSS, 5V rated. NVC Nonvolatile STORE operations 200 200 K DATAR Data Retention 20 20 Years Note: The HSB pin has IOUT = -10 uA for VOH of 2.4 V. This parameter is characterized but not tested. Document Control #ML0060 Rev 1.0 April, 2007 3 Simtek Confidential @ 55 deg C Preliminary STK14EC8 AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2 CAPACITANCEb SYMBOL PARAMETER (TA = 25°C, f = 1.0MHz) MAX UNITS CONDITIONS CIN Input Capacitance 7 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V Note b: These parameters are guaranteed but not tested. 3.0V 577 Ohms OUTPUT 30 pF INCLUDING SCOPE AND FIXTURE 789 Ohms Figure 1: AC Output Loading 3.0V 577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ) Document Control #ML0060 Rev 1.0 April, 2007 4 Simtek Confidential Preliminary STK14EC8 SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK14EC8-15 STK14EC8-25 STK14EC8-45 MIN MIN MIN PARAMETER #1 #2 1 Alt. tELQV 2 tAVAVc tAVAV 3 tAVQVd tAVQVd tGLQV 4 tAXQXd 5 6 c tAXQX d tELQX 7 tEHQZ 8 tGLQX 9 e tGHQZ e MAX 15 Chip Enable Access Time tRC Read Cycle Time tAA Address Access Time 15 25 45 ns tOE Output Enable to Data Valid 10 12 20 ns tOH Output Hold after Address Change 3 3 3 ns tLZ Chip Enable to Output Active 3 3 3 ns tHZ Chip Disable to Output Inactive tOLZ Output Enable to Output Active 15 tOHZ Output Disable to Output Inactive 10 tELICCH tPA Chip Enable to Power Active 11 tEHICCLb tPS Chip Disable to Power Standby 25 45 25 45 7 0 10 0 7 0 10 0 25 SRAM READ CYCLE #1: Address Controlledc,d,f 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledc,f 2 tAVAV ADDRESS 1 tELQV 6 11 tEHICCL tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQX tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ACTIVE ICC STANDBY Document Control #ML0060 Rev 1.0 April, 2007 5 Simtek Confidential ns ns 15 ns 45 ns 0 15 ns ns 15 0 W must be high during SRAM READ cycles. Device is continuously selected with E and G both low Measured ± 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles. E MAX tACS b Note c: Note d: Note e: Note f: UNITS MAX ns Preliminary STK14EC8 SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. STK14EC8-15 STK14EC8-25 STK14EC8-45 MIN MIN MIN PARAMETER UNITS #1 #2 Alt. MAX MAX MAX 12 tAVAV tAVAV tWC Write Cycle Time 15 25 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 10 20 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 15 20 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 5 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 10 20 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 t WLQZ e, g tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 7 3 10 3 3 Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledg,h 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledg,h 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT Document Control #ML0060 Rev 1.0 April, 2007 16 tEHDX DATA VALID HIGH IMPEDANCE 6 Simtek Confidential 15 ns ns Preliminary STK14EC8 AutoStore™/POWER-UP RECALL SYMBOLS STK14EC8 NO. PARAMETER Standard Alternate MIN NOTES 20 ms i 15 ms j 2.65 V Power-up RECALL Duration 22 tHRECALL 23 tSTORE 24 VSWITCH Low Voltage Trigger Level 25 VCCRISE VCC Rise Time Note i: Note j: UNITS MAX tHLHZ STORE Cycle Duration μs 150 tHRECALL starts from the time VCC rises above VSWITCH If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place AutoStore™/POWER-UP RECALL STORE occurs only if a SRAM write has happened. No STORE occurs without at least one SRAM write. VCC 24 VSWITCH 25 tVCCRISE AutoStoreTM 23 tSTORE 23 tSTORE POWER-UP RECALL 22 tHRECALL 22 tHRECALL Read & Write Inhibited POWER-UP RECALL BROWN OUT TM AutoStore POWER-UP RECALL POWER DOWN TM AutoStore Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH Document Control #ML0060 Rev 1.0 April, 2007 7 Simtek Confidential Preliminary STK14EC8 SOFTWARE-CONTROLLED STORE/RECALL CYCLEk,l Symbols STK14EC8-15 NO. STK14CA8-25 STK14CA8-45 PARAMETER UNITS NOTES E Cont G Cont Alternate 26 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 15 25 45 ns 27 tAVEL tAVGL tAS Address Set-up Time 0 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 12 20 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 1 ns 30 tRECALL tRECALL RECALL Duration MIN MAX MIN 100 MAX MIN MAX 100 100 k,l μs Note k: The software sequence is clocked with E controlled READs or G controlled READs Note l: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDl ADDRESS E 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 27 tAVEL 28 tELEH 29 tEHAX G 23 tSTORE /t 30 RECALL HIGH IMPEDENCE DQ (DATA) DATA VALID DATA VALID SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDl ADDRESS 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 E 27 tAVGL 28 tGLGH G 23 tSTORE 29 / 30 tRECALL tGHAX DQ (DATA) DATA VALID Document Control #ML0060 Rev 1.0 April, 2007 DATA VALID 8 Simtek Confidential HIGH IMPEDENCE Preliminary STK14EC8 HARDWARE STORE CYCLE SYMBOLS STK14EC8 PARAMETER Standard Alternate 31 1 tDELAY tHLQZ 32 2 tHLHX MIN MAX Hardware STORE to SRAM Disabled 1 70 Hardware STORE Pulse Width 15 UNITS NOTES μs m ns Note m: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete HARDWARE STORE CYCLE 32 t HLHX HSB (IN) 23 t STORE HSB (OUT) 31 tDELAY DQ (DATA OUT) SRAM Enabled SRAM Enabled Soft Sequence Commands NO. SYMBOLS PARAMETER STK14EC8 Standard 33 MIN tSS UNITS NOTES μs n,o MAX Soft Sequence Processing Time 70 Note n: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. Note o: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. 33 tSS 33 tSS Soft Sequence Command ADDRESS ADDRESS #1 Soft Sequence Command ADDRESS #6 ADDRESS #1 Vcc Document Control #ML0060 Rev 1.0 April, 2007 9 Simtek Confidential ADDRESS #6 Preliminary STK14EC8 MODE SELECTION E W G A15-A0 Mode I/O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Output Data Output Data Output Data Output Data Output Data Output High Z 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z L L L L H H H H L Active Notes q,r,s q,r,s q,r,s ICC2 Active q,r,s Note q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note r: While there are 19 addresses on the STK14EC8, only the lower 16 are used to control software modes Note s: I/O state depends on the state of G. The I/O table shown assumes G low Document Control #ML0060 Rev 1.0 April, 2007 10 Simtek Confidential Preliminary STK14EC8 nvSRAM OPERATION nvSRAM SRAM WRITE The STK14EC8 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14EC8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. SRAM READ The STK14EC8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). The STK14EC8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-18 determine which of the 524,288 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low. vCC vCC W Figure 3: AutoStore Mode Document Control #ML0060 Rev 1.0 April, 2007 vCAP 10K Ohm 0.1µF vCAP It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. AutoStore OPERATION AutoStore operation is a unique feature of Simtek QuanumTrap technology that is enabled by default on the STK14EC8. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. This pull-up is only effective if the W signal is tri-state during power up. Many MPU’s will tristate their controls on power up. This should be verified when using the pullup. When the nvSRAM comes out on power-on-recall, the MPU must be active or the W held inactive until the MPU comes out of reset. 11 Simtek Confidential Preliminary STK14EC8 To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. HARDWARE STORE (HSB) OPERATION The STK14EC8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14EC8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected. HARDWARE RECALL (POWER-UP) During power up or after any low-power condition (VCC<VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete. SOFTWARE STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14EC8 software STORE cycle is initiated by executing sequential E controlled or G controlled Document Control #ML0060 Rev 1.0 April, 2007 READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. To initiate the software STORE cycle, the following READ sequence must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ Valid READ 5 Read Address 0x703F 6 Read Address 0x8FC0 Initiate STORE Cycle Valid READ Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle Valid READ Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements. Care must be taken so the controlling falling edge is glitch and ring free so as not to double clock the read address. 12 Simtek Confidential Preliminary STK14EC8 DATA PROTECTION LOW AVERAGE ACTIVE POWER The STK14EC8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low-voltage condition is detected when VCC<VSWITCH. CMOS technology provides the STK14EC8 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14EC8 depends on the following items: If the STK14CA8 is in a WRITE mode (both E and W low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions. NOISE CONSIDERATIONS The STK14EC8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are a short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise. 1 The duty cycle of chip enable 2 The overall cycle rate for operations 3 The ratio of READs to WRITEs 4 The operating temperature 5 The VCC Level 6 I/O Loading Figure 4 - Current vs Cycle Time Document Control #ML0060 Rev 1.0 April, 2007 13 Simtek Confidential STK14EC8 Preliminary PREVENTING AUTOSTORE The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x8B45 AutoStore Disable This is a product in development that has fixed target specifications that are subject to change pending characterization results. Simtek Confidential & Proprietary The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled, but best design practice is to set the enable or disable state during each power-up sequence and not depend on this factory default condition. Simtek recommends users configure the part completely for the specific application. 14 Document Control #ML0060 Rev 1.0 April, 2007 Preliminary STK14EC8 ORDERING INFORMATION STK14EC8-T F 45 I TR Packing Option Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) Access Time 15 = 15 ns 25 = 25 ns 45 = 45 ns Lead Finish F = 100% Sn (Matte Tin) RoHS Compliant Package T = Plastic 44-pin 400 mil TSOP-II (32 mil pitch) Document Control #ML0060 Rev 1.0 April, 2007 15 Simtek Confidential Preliminary STK14EC8 Ordering Codes STK14EC8-TF15 STK14EC8-TF25 STK14EC8-TF45 STK14EC8-TF15TR STK14EC8-TF25TR STK14EC8-TF45TR STK14EC8-TF15I STK14EC8-TF25I STK14EC8-TF45I STK14EC8-TF15ITR STK14EC8-TF25ITR STK14EC8-TF45ITR 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM Document Control #ML0060 Rev 1.0 April, 2007 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 16 Simtek Confidential Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Preliminary STK14EC8 PACKAGE DIAGRAMS 44 Pin TSOPII 22 1 0.404 0.396 ( 10.262 10.058 0.470 0.455 ) ( 11.938 11.735 ) 44 23 0.0404 0.0396 10.262 (10.058 ) 0° 5° 0.0235 0.0160 0.0315 (0.800) 0.047 0.039 0.016 0.012 BSC 0.597 ( 0.406 ) 0.400 (0.300 ) Base Plane (1.194 0.991 ) Seating Plane 0.729 0.721 18.517 ( 18.313 ) 0.150 0.050 DIM = INCHES DIM = mm MIN MAX MIN ( MAX ) Document Control #ML0060 Rev 1.0 April, 2007 17 Simtek Confidential ( 0.0059 0.0020) 0.004 (0.10) Preliminary STK14EC8 Document Revision History Rev Date Change 1.0 April 2007 Moved to Preliminary from Advance Information - made clear that nominal supply is 3.3V, not 3.0V (range 2.7V to 3.6V) - modified language on pin description of HSB and NC. - changed ISB from 1mA to 2mA. - changed Icc3 from 8mA to 13mA - clarified description language of Figure 3 - clarifed description language of Software Recall - clarified description language of Preventing Autostore - corrected typo on Industrial temp range: -45 to -40 SIMTEK STK14EC8 Datasheet, April 2007 Copyright 2007, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use, Simtek products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Simtek. Furthermore, Simtek does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Simtek products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Simtek against all charges. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0060 Rev 1.0 April, 2007 18 Simtek Confidential