SIMTEK STK11C88

STK11C88-3
32K x 8 nvSRAM
3.3V QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Deisgns
FEATURES
DESCRIPTION
• 35, 45ns and 55ns Access Times
The Simtek STK11C88-3 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data
transfers from the SRAM to the Nonvolatile Elements
(the STORE operation), or from Nonvolatile Elements
to SRAM (the RECALL operation) are initiated using a
software sequence. Data transfers from the Nonvolatile Elements to the SRAM (the RECALL operation)
also occur upon restoration of power.
• STORE to Nonvolatile Elements Initiated by
Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10 mA Typical Icc at 200 nsec Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Elements
• 100-Year Data Retention in Nonvolatile Elements
• Single 3.3V+ 0.3V Operation
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
INPUT BUFFERS
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
QUANTUM TRAP
512 x 512
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4A10
G
E
W
March 2006
A0 - A13
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
A0 - A14
Address Inputs
W
Write Enable
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
VCC
Power (+ 3.3V)
VSS
Ground
Document Control # ML0013 rev 0.2
STK11C88-3
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 4.5V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
(VCC = 3.0V-3.6V)
COMMERCIAL
INDUSTRIAL
MIN
MIN
PARAMETER
UNITS
MAX
NOTES
MAX
ICC1b
Average VCC Current
50
42
37
52
44
39
mA
mA
mA
tAVAV = 35ns
tAVAV = 45ns
tAVAV = 55ns
ICC2c
Average VCC Current During STORE
3
3
mA
All Inputs Don’t Care, VCC = max
Average VCC Current at tAVAV = 200ns
3.3V, 25°C, Typical
9
9
mA
W ≥ (VCC – 0.2V)
All Others Cycling, CMOS Levels
18
16
15
19
17
16
mA
mA
mA
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
tAVAV = 55ns, E ≥ VIH
750
750
μA
E ≥ (V CC - 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
ICC3
b
ISB1d
Average VCC Current
(Standby, Cycling TTL Input Levels)
ISB2d
VCC Standby Current
(Standby, Stable CMOS Input Levels)
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.2
VCC + .5
2.2
VCC + .5
V
All Inputs
VIL
Input Logic “0” Voltage
VSS – .5
0.8
VSS – .5
0.8
V
All Inputs
VOH
Output Logic “1” Voltage
V
IOUT = – 4mA
VOL
Output Logic “0” Voltage
0.4
V
IOUT = 8mA
TA
Operating Temperature
85
°C
2.4
2.4
0.4
0
70
–40
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) .
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
3.3V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.0V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
e
CAPACITANCE
SYMBOL
317 Ohms
OUTPUT
(TA = 25°C, f = 1.0MHz)
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
5
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
Note e: These parameters are guaranteed but not tested.
March 2006
351 Ohms
2
Document Control # ML0013 rev 0.2
STK11C88-3
SRAM READ CYCLES #1 & #2
(VCC = 3.0V-3.6V)
SYMBOLS
NO.
STK11C88-3-35
STK11C88-3-45
STK11C88-3-55
PARAMETER
#1, #2
1
tELQV
2
tAVAV
f
3
tAVQVg
4
tGLQV
UNITS
Alt.
MIN
MAX
MIN
MAX
Chip Enable Access Time
tRC
Read Cycle Time
tAA
Address Access Time
35
45
55
ns
tOE
Output Enable to Data Valid
15
20
25
ns
5
tAXQXg
tOH
Output Hold after Address Change
5
5
5
ns
6
tELQX
tLZ
Chip Enable to Output Active
5
5
5
ns
7
tEHQZh
tHZ
Chip Disable to Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZh
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
10
tELICCH
11
tEHICCLd, e
35
45
MAX
tACS
e
35
MIN
55
45
55
13
0
15
0
ns
20
0
0
13
15
0
45
ns
ns
20
0
35
ns
ns
ns
55
ns
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
tAVAV
ADDRESS
1
11
tELQV
E
tEHICCL
6
tELQX
7
tEHQZ
G
9
tGHQZ
4
8
tGLQV
tGLQX
DQ (DATA
DATA VALID
10
tELICCH
ICC
March 2006
ACTIVE
STANDBY
3
Document Control # ML0013 rev 0.2
STK11C88-3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)
SYMBOLS
STK11C88-3-35 STK11C88-3-45 STK11C88-3-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
12
tAVAV
tAVAV
tWC
Write Cycle Time
35
45
55
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
25
30
40
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
25
30
40
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
12
15
25
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
25
30
40
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
0
ns
20
tWLQZh, i
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
Note i:
Note j:
MIN
MAX
MIN
MAX
13
5
MIN
15
5
MAX
20
5
ns
ns
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
15
16
tDVWH
DATA IN
tWHDX
DATA VALID
20
tWLQZ
DATA OUT
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
tAVAV
ADDRESS
18
19
14
tAVEL
tEHAX
tELEH
E
17
tAVEH
13
tWLEH
W
15
16
tDVEH
DATA IN
DATA OUT
March 2006
tEHDX
DATA VALID
HIGH IMPEDANCE
4
Document Control # ML0013 rev 0.2
STK11C88-3
STORE INHIBIT/POWER-UP RECALL
(VCC = 3.0V-3.6V)
SYMBOLS
STK11C88-3
NO.
PARAMETER
Standard
MIN
22
tRESTORE
Power-up RECALL Duration
23
tSTORE
STORE Cycle Duration
24
VSWITCH
Low Voltage Trigger Level
25
VRESET
Low Voltage Reset Level
2.7
UNITS
NOTES
550
μs
k
g
MAX
10
ms
2.95
V
2.4
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
VCC
3.3V
24
VSWITCH
25
VRESET
STORE INHIBIT
POWER-UP RECALL
22
tRESTORE
DQ (DATA OUT)
POWER-UP
RECALL
March 2006
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
5
Document Control # ML0013 rev 0.2
STK11C88-3
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A13 - A0 (hex)
MODE
I/O
NOTES
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l, m
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l, m
L
L
Note l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK11C88-3, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEn, o
NO.
SYMBOLS
(VCC = 3.0V-3.6V)
STK11C88-3-35
STK11C88-3-45
STK11C88-3-55
MIN
MIN
MIN
PARAMETER
UNITS
MAX
MAX
MAX
26
tAVAV
STORE/RECALL Initiation Cycle Time
35
45
55
ns
27
tAVELn
Address Set-up Time
0
0
0
ns
28
tELEHn
Clock Pulse Width
25
30
45
ns
29
tELAXn
Address Hold Time
20
20
20
ns
30
tRECALL
n
RECALL Duration
20
20
20
μs
Note n: The software sequence is clocked with E controlled READs.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
26
26
tAVAV
ADDRESS
tAVAV
ADDRESS #1
27
tAVEL
ADDRESS #6
28
tELEH
E
29
tELAX
23
tSTORE
DQ (DATA
March 2006
DATA VALID
DATA VALID
6
30
/ tRECALL
HIGH IMPEDANCE
Document Control # ML0013 rev 0.2
STK11C88-3
DEVICE OPERATION
SOFTWARE NONVOLATILE STORE
The STK11C88-3 is a versatile 3.3V VCC memory
chip that provides several modes of operation. The
STK11C88-3 can operate as a standard 32K x 8
SRAM. It has a 32K x 8 Nonvolatile Elements
shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode.
The STK11C88-3 software STORE cycle is initiated
by executing sequential READ cycles from six specific address locations. During the STORE cycle an
erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile
elements. The program operation copies the SRAM
data into nonvolatile memory. Once a STORE cycle
is initiated, further input and output are disabled until
the cycle is completed.
NOISE CONSIDERATIONS
Note that the STK11C88-3 is a high-speed memory
and so must have a high frequency bypass capacitor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
Because a sequence of reads from specific
addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
SRAM READ
The STK11C88-3 performs a READ cycle whenever
E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768
data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
1.
2.
3.
4.
5.
6.
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence is clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
March 2006
Read address
Read address
Read address
Read address
Read address
Read address
1.
2.
3.
4.
5.
6.
7
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Document Control # ML0013 rev 0.2
STK11C88-3
HARDWARE PROTECT
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
The STK11C88-3 offers hardware protection
against inadvertent STORE operation during lowvoltage conditions. When VCC < VSWITCH, all software
STORE operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for WRITE cycles.If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C88-3 depends on the following
items: 1) CMOS vs. TTL input levels; 2) the duty
cycle of chip enable; 3) the overall cycle rate for
accesses; 4) the ratio of READs to WRITEs; 5) the
operating temperature; 6) the VCC level; and 7) I/O
loading.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET ), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C88-3 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
50
Average Active Current (mA)
Average Active Current (mA)
50
40
30
20
TTL
10
40
30
TTL
20
CMOS
10
CMOS
0
0
50
100
150
Cycle Time (ns)
200
50
Figure 2: ICC (max) Reads
March 2006
100
150
Cycle Time (ns)
200
Figure 3: ICC (max) Writes
8
Document Control # ML0013 rev 0.2
STK11C88-3
ORDERING INFORMATION
STK11C88-3 W F 25 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W=Plastic 28-pin 600 mil DIP
P=Plastic 28-pin 300 mil DIP
S=Plastic 28-pin 350 mil SOIC
N=Plastic 28-pin 300 mil SOIC
March 2006
9
Document Control # ML0013 rev 0.2
STK11C88-3
Document Revision History
Revision
Date
Summary
0.0
December 2002
Added 35 nsec device; changed Vcc min. to 3.0 volts
0.1
September 2003
Added lead free lead finish
0.2
March 2006
Marked as Obsolete, Not recommended for new design.
March 2006
10
Document Control # ML0013 rev 0.2