STATSCHIP QFN

QFN
Quad Flat No-Lead Package
• Punch or Saw singulated formats
• Body sizes from 2 x 2mm to 12 x 12mm
• Pin counts from 4L to 156L
• Square or rectangular body sizes
• Leads on four sides of the body (QFN)
• Leads on two opposing sides of the
body (DFN)
• Dual row lead design options
• Thin package thickness options
FEATURES
DESCRIPTION
• Body sizes: 2 x 2 to 12 x 12mm
STATS ChipPAC’s Quad Flat No-Lead (QFN) and Dual Flat
No-Lead (DFN) package offering includes the QFNs (saw
singulated), QFNp (punch singulated), XQFN, UQFN, WQFN,
and QFN-dr. These are leadframe based, plastic encapsulated,
chip scale packages in single mold cavity format (punch
singulated) or molded array format (saw singulated).
• Lead pitch: 0.40, 0.50, 0.65 and 0.80mm
• Custom lead/pitch configurations available
• Package profile heights: 0.45, 0.50, 0.75, 0.85 and
0.90mm
• Option for non-exposed die pad
• Green materials set
• Option for PbSn, 100% matte Sn or PPF
• Small chip scale design offers 50% reduction in board
space (16L TSSOP vs. 16L QFN)
• 33% weight reduction (in 16L TSSOP vs. 16L QFN)
• Excellent thermal & electrical performance
• Full in-house package and leadframe design capability
• Full in-house assembly and test capability
• Full in-house electrical, thermal and mechanical
simulation and measurement capability
• Wide range of open tool leadframe and die pad sizes
available
• JEDEC standard compliant (XQFN, UQFN, WQFN, VQFN)
An exposed die pad coupled with extremely low RLC
provides excellent electrical and thermal performance
enhancements which are ideal for high frequency and high
power applications, and are especially suited for wireless
and handheld portable applications such as cell phones.
QFN-dr with staggered dual row leads offers higher I/O
counts. STATS ChipPAC’s QFN packages are currently
available in various body sizes and thicknesses, offered in
standard and green/lead-free bill of materials and can be
processed by conventional SMT equipment, benefiting
surface mount operations downstream.
APPLICATIONS
• RF
• Power management
• Discretes
• Analog/Linear
• Logic
• Applications requiring enhanced electrical and thermal
performance and reduced package size, thickness and
weight
www.statschippac.com
QFN
Quad Flat No-Lead Package
SPECIFICATIONS
Die Thickness
Gold Wire
Lead finish
Marking
Packing Options
RELIABILITY
150-350µm
20-33µm (0.8-1.3mils) diameter
Matte Tin, preplated Ni/Pd/Au or Sn/Pb
Laser
Tape & reel, tube, JEDEC tray
Moisture Sensitivity Level
Temperature Cycling
High Temp Storage
Pressure Cooker Test
Temperature/Humidity Test
JEDEC MSL 3/2/1
(depending on package)
–65°C/150°C, 1000 cycles
150°C, 1000 hrs
121°C, 100% RH, 2 atm, 168 hrs
85°C/85% RH, 1000 hrs
THERMAL PERFORMANCE, θja (°C/W)
Package
Body Size
(mm)
Pad Size
(mm)
Die Size
(mm)
*Thermal Performance
θja(°C/W)
Thermal Vias
(on test board)
48L UQFN
7 x 7 x 0.50
5.1 x 5.1
2.26 x 2.26
26.3
25
64L QFN
9 x 9 x 0.85
7.3 x 7.3
4.52 x 4.52
19.2
36
76L QFN-dr
8 x 8 x 0.85
5.28 x 5.28
4.52 x 4.52
26.6
16
Notes: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-7) under natural convection as defined in JESD51-2.
ELECTRICAL PERFORMANCE
Package
Body Size (mm)
Frequency
Length
Inductance (nH)
Capacitance (pF)
48L UQFN
7 x 7 x 0.50
100 MHz
Self (short)
Mutual
Self (long)
Mutual
0.88
0.20
0.98
0.27
0.191
0.032
0.223
0.064
76L QFN-dr
8 x 8 x 0.85
100 MHz
Self (short)
Mutual
Self (long)
Mutual
1.33
0.45
1.68
0.53
0.180
0.080
0.270
0.110
Note: Results are simulated values per JEDEC EIA/JEP123 standards.
CROSS-SECTIONS
PACKAGE CONFIGURATIONS
Pkg Size (mm) Lead Pitch (mm)
QFNs
QFNs-dr
QFNp
2x2
2x3
3x3
4x4
5x5
6x5
6x6
7x7
8x8
9x9
10 x 10
10 x 10
12 x 12
0.65/0.50
0.50
0.80/0.65/0.50/0.40
0.80/0.65/0.50/0.40
0.80/0.65/0.50/0.40
0.80/0.65/0.50
0.80/0.65/0.50/0.40
0.80/0.65/0.50/0.40
0.80/0.65/0.50/0.40
0.65/0.50/0.40
0.50/0.40
0.50 dual row
0.50 dual row
Lead Count
4/8
6/8
4/8/12/16/20
12/14/16/20/24/28
14/16/20/28/32/40
18/20/22/32
20/24/28/32/36/38/40/48
28/32/36/40/44/48/56
28/32/36/40/44/48/52/56/64
44/48/56/60/64/72
64/68/72/88
124
156
QFNp-dr
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of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information
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©Copyright 2006. STATS ChipPAC Ltd. All rights reserved.
May 2006