SUPERTEX HV732

Supertex inc.
HV732
Initial Release
High Speed ±100V 2A
Integrated Ultrasound Pulser
Features
►
►
►
►
►
►
►
►
►
►
General Description
HVCMOS technology for high performance
0 to ±100V output voltage
±2A source and sink current
Built-in damping for RTZ waveform capability
Gate-clamp for quick output amplitude ramping
Up to 40MHz operation frequency
±3ns matched delay times
Second harmonic is less than -40dB
1.8V to 3.3V CMOS logic interface
7x7 thermally-enhanced 44-lead QFN MCM
The Supertex HV732 is a single, complete, high-voltage,
high-speed, ultrasound transmitter pulser. It is designed for
medical ultrasound imaging applications.
The HV732 has built-in damping for faster RTZ waveform
capability and high voltage MOSFET gate-clamping function
for quick ramping of the output voltage amplitude.
The HV732 consists of a control logic circuit, level translators,
MOSFET gate drive buffers, clamp circuits, and high current,
high voltage MOSFETs as the ultrasound transmitter pulser
output stage.
Application
In the output stage there are two pairs of MOSFETs. Each
pair consists of a P-channel and an N-channel MOSFET.
They are designed to have the same impedance, and can
provide peak currents of over ±2 amps. The built-in MOSFET
gate driver outputs swing 0 to 12V on PDR and NDR pins. The
P-channel damp output swings 0 to –5V on the DMPO pin.
► Medical ultrasound imaging
Typical Application Circuit
10nF
PDR
PGATE
VPP
+12V
PIN
Level
Trans.
0 to +100V
Buffer
TXP
VSUB
Substrate, PAD1
Clamp
Circuit
CLAMP
VLL
+1.8 to 3.3V
VLN
-5V
EN
VDD
PAD3
PAD2
on/off
GND
+5 to 12V
0V
NIN
Level
Trans.
TXN
VNN
0 to -100V
HVOUT
+12V
AVDD
AGND
DAMP
OUTN
Buffer
OUTP
Bias
RGNDP
Level
Trans.
RGNDN
NDR
NGATE
10nF
DMPO DMPI
10nF
NR040506
Supertex inc.
· 1235 Bordeaux Drive, Sunnyvale, CA 94089 · Tel: (408) 222-8888 · FAX: (408) 222-4895 · www.supertex.com
1
HV732
Power-Up Sequence
Ordering Information
Device
HV732
Package Options
1
VPP and VSUB
44-Lead QFN
2
VNN
3
VLN
4
VDD
5
VLL
HV732K6
HV732K6-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Value
VLL, logic supply
-0.5V to +5.5V
VDD, positive gate drive supply
-0.5V to +15V
AVDD, positive gate drive supply
-0.5V to +15V
VLN, Negative gate drive supply
-5.5V to +0.5V
VPP-VNN, differential high voltage supply
+220V
VPP, high voltage positive supply
-0.5V to +200V
VNN, high voltage negative supply
+0.5V to -200V
Storage temperature
-65°C to 150°C
Thermal enhanced package power
dissipation
1.5W
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Operating Supply Voltages and Current
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VLL
Logic supply
1.8
3.3
3.6
V
---
AVDD
Positive analog supply
9.0
-
12.6
V
---
VDD
Positive drive supply
9.0
-
12.6
V
---
VPP
High voltage positive supply for HVOUTP1
0
-
100
V
---
VNN
High voltage negative supply for HVOUTN1
-100
-
0
V
---
VLN
High voltage negative supply for HVOUTN2
-4.75
-5.0
-5.25
V
---
VSUB
High voltage positive supply for to bias
substrate
-
-
100
V
Need to be the most positive supply on the
device
IDDQ
VDD current EN = Low
-
175
290
μA
---
IDDEN
VDD current EN = High
-
1.7
2.8
mA
PIN = NIN = Low
IDDEN
VDD current at 5MHz PW
-
7.5
-
mA
f = 5.0MHz, PW D% = 1.0%
No cap on PDR, NDR
IPPQ
VDD current EN = Low
-
2.0
5.0
μA
VPP = +100V, VNN = -100V
IPPEN
VDD current EN = High
-
140
180
μA
PIN = NIN = Low, VPP = +100V, VNN = -100V
INNQ
VDD current EN = Low
-
-1.0
-3.0
μA
VPP = +100V, VNN = -100V
NR040506
2
HV732
Operating Supply Voltages and Current (cont.)
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
INNEN
VDD current EN = High
-
-140
-180
μA
PIN = NIN = Low, VPP = +100V, VNN = -100V
ILLQ
VDD current EN = Low
-
1.0
5.0
μA
---
ILLEN
VDD current EN = High
-
16
25
μA
PIN = NIN = Low
ILNQ
VDD current EN = Low
-
-1.0
-5.0
μA
---
ILNEN
VDD current EN = High
-
-230
-320
μA
PIN = NIN = Low
DC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C)
Output P-Channel MOSFET, TXP
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IOUT
Output saturation current
-2.0
-
-
A
VGS = -10V, VDS = -25V
RON
Channel resistance
-
-
8
Ω
VGS = -10V, IDS = -1.0A
RGS
Gate to source resistor
10
-
50
KΩ
IGS = -100μA
VGS
Source to gate zener voltage
-13.2
-
-25
V
IGS = -2.0μA
VGSF
Gate zener forward voltage
-0.5
-
-0.8
V
---
VGS(th)
Gate threshold voltage
-1.0
-
-2.4
V
IDS = -1.0mA
CISS
Input capacitance
-
-
200
pF
COSS
Output capacitance
-
25
55
pF
Parameter
Min
Typ
Max
Units
IOUT
Output saturation current
2.0
-
-
A
VGS = -10V, VDS = -25V
RON
Channel resistance
-
7.0
Ω
VGS = -10V, IDS = -1.0A
RGS
Gate to source resistor
10
-
50
KΩ
IGS = -100μA
VGS
Source to gate zener voltage
13.2
-
25
V
IGS = -2.0μA
VGSF
Gate zener forward voltage
0.5
-
0.8
V
---
VGS(th)
Gate threshold voltage
1.0
-
2.0
V
IDS = -1.0mA
VGS = 0V, VDS = -25V, f = 1Mhz
Output N-Channel MOSFET, TXN
Symbol
CISS
Input capacitance
-
-
110
pF
COSS
Output capacitance
-
28
60
pF
Min
Typ
Max
Units
Conditions
VGS = 0V, VDS = -25V, f = 1Mhz
Output P-Channel Damp MOSFET, OUTP
Symbol
Parameter
Conditions
IOUT
Output saturation current
-
-1.0
-
A
VGS = -10V, VDS = -25V
RON
Channel resistance
-
-
30
Ω
VGS = -10V, IDS = -1.0A
RGS
Gate to source resistor
-
75
100
KΩ
IGS = -100μA
VGS
Source to gate zener voltage
-13.2
-
-25
V
IGS = -2.0μA
VGSF
Gate zener forward voltage
0.5
-
0.8
V
---
VGS(th)
Gate threshold voltage
-1.0
-
-2.6
V
IDS = -1.0mA
CISS
Input capacitance
-
-
200
pF
COSS
Output capacitance
-
-
60
pF
VGS = 0V, VDS = -25V, f = 1Mhz
NR040506
3
HV732
Output N-Channel Damp MOSFET, OUTN
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IOUT
Output saturation current
1.0
-
-
A
VGS = 10V, VDS = 25V
RON
Channel resistance
-
-
22
Ω
VGS = 10V, IDS = 0.5A
VGS
Source to gate zener voltage
1.0
-
2.6
V
IDS = 1.0μA
CISS
Input capacitance
-
-
110
pF
COSS
Output capacitance
-
-
60
pF
Min
Typ
Max
Units
Conditions
Output sink resistance
-
10
15
Ω
IPDR = 100mA
RSOURCE
Output source resistance
-
8.0
13
Ω
IPDR = -100mA
IPDR
Peak output sink current
-
2.0
-
A
---
IPDR
Peak output source current
-
-2.0
-
A
---
Min
Typ
Max
Units
Conditions
Output sink resistance
-
8.0
13
Ω
INDR = 100mA
RSOURCE
Output source resistance
-
9.0
14
Ω
INDR = -100mA
INDR
Peak output sink current
-
1.0
-
A
---
INDR
Peak output source current
-
-1.0
-
A
---
VGS = 0V, VDS = 25V, f = 1Mhz
P-Channel Gate Driver Output, PDR
Symbol
RSINK
Parameter
N-Channel Gate Driver Output, NDR
Symbol
RSINK
Parameter
P-Channel Gate Driver Output, DMPO
Symbol
Min
Typ
Max
Units
Output sink resistance
-
26
30
Ω
IDMPO = 100mA
RSOURCE
Output source resistance
-
15
30
Ω
IDMPO = -100mA
IDMPO
Peak output sink current
-
0.3
-
A
---
IDMPO
Peak output source current
-
-0.3
-
A
---
Min
Typ
Max
Units
RSINK
Parameter
Conditions
P-Channel Gate Clamp MOSFET
Symbol
Parameter
Conditions
IOUT
Output saturation current
-
100
-
A
---
RON
Channel resistance
-
60
80
Ω
---
COSS
Output capacitance
-
40
-
pF
VGS = 0V, VDS = 25V, f = 1Mhz
Min
Typ
Max
Units
N-Channel Gate Clamp MOSFET
Symbol
Parameter
Conditions
IOUT
Output saturation current
-
50
-
A
---
RON
Channel resistance
-
25
50
Ω
---
COSS
Output capacitance
-
40
-
pF
VGS = 0V, VDS = 25V, f = 1Mhz
NR040506
4
HV732
Logic Inputs
Symbol
Parameter
Min
Typ
Max
Units
Conditions
tirf
Inputs rise and fall time
-
-
10
ns
Logic input edge speed requirement
VIH
Input logic high voltage
0.8VLL
-
VLL
V
---
VIL
Input logic low voltage
0
-
0.2VLL
V
---
IIH
Input logic high current
-
-
1.0
μA
---
IIL
Input logic low current
-1.0
-
-
μA
---
AC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C)
Symbol
Min
Typ
Max
Units
Conditions
fout
Output frequency range
-
-
40
MHz
See test curcuit and timing diagram
tr
Output rise time
-
10
-
ns
tf
Output fall time
-
10
-
ns
tdr
Delay time on rise time
-
12
-
ns
tdf
Delay time on fall time
-
12
-
ns
Δtdelay
Delay time matching
-
-
±3.0
ns
From device to device
HD2
Second harmonic distortion
-
-40
-
dB
100Ω resistor load
tjitter
Output jitter
-
80
-
ps
Standard deviation of td samples (1k)
tEN
Enable time
-
30
50
μs
See timing diagram
tDMPON(P)
Damp switch on delay (P)
-
17
22
ns
tDMPOFF(P)
Damp switch off delay (P)
-
20
26
ns
OUTP 50Ω to -15V, 10nF from DMPO to
DMPI. See timing diagram.
tDMPON(N)
Damp switch on delay (N)
-
13
17
ns
tDMPOFF(N)
Damp switch off delay (N)
-
13
17
ns
tCLPON(P)
Clamp switch on delay (P)
-
430
1000
ns
tCLPOFF(P)
Clamp switch off delay (P)
-
490
1000
ns
tCLPON(N)
Clamp switch on delay (N)
-
330
550
ns
tCLPOFF(N)
Clamp switch off delay (N)
-
316
500
ns
NGATE 75Ω to 0V, 10nF to NDR, VNN = -12V.
See timing diagram.
Device power-up delay
-
150
200
μs
All power supplies up and stable
tPWRUP
Parameter
See relevant test circuit and timing diagram.
Load = 1.0kΩ/220pF
OUTN 50Ω to +15V.
See timing diagram.
PGATE 75Ω to 0V, 10nF to PDR, VPP = +12V.
See timing diagram.
Truth Table
Logic Control Inputs
Gate Drive Output
HV Output
Damp Output
EN
PIN
NIN
CLAMP
DAMP
PDR
NDR
DMPO
TXP
TXN
OUTP
OUTN
1
0
0
0
0
H
L
H
OFF
OFF
OFF
OFF
1
1
0
0
0
L
L
H
ON
OFF
OFF
OFF
1
0
1
0
0
H
H
H
OFF
ON
OFF
OFF
1
X
X
1
0
H
L
H
OFF
OFF
OFF
OFF
1
0
0
0
1
H
L
L
OFF
OFF
ON
ON
0
X
X
X
X
H
L
H
OFF
OFF
OFF
OFF
NR040506
5
HV732
HV732 Test Circuit
10nF
PDR
PGATE
VPP
+12V
Level
Trans.
PIN
Buffer
TXP
VSUB
Substrate, PAD1
Clamp
Circuit
CLAMP
VLL
+1.8 to 3.3V
VLN
-5V
PAD3
PAD2
on/off
EN
VDD
TXN
VNN
+5 to 12V
0V
HVOUT
+12V
GND
OUTN
Level
Trans.
NIN
Buffer
AVDD
OUTP
RLOAD
100
Bias
AGND
RGNDP
Level
Trans.
DAMP
RGNDN
NDR
NGATE
DMPO DMPI
10nF
10nF
HV732 TX Switching Time Test
+3.3V
+100V
+12V
0 to +100V
10nF
10Ω
VLL
20MHz
3V0-P
AVDD
VDD
PDR
PGATE
VPP
VSUB
EN
TXP
PIN
TXN
NIN
OUTN
HV732
OUTP
CLAMP
HVOUT
RL
CL
1K
220pF
DAMP
RGNDP
RGNDN
VLN
AGND
-5V
to Oscilloscope
GND
NDR
NGATE
DMPO DMPI
VNN
0Ω
10nF
10nF
0 to -100V
NR040506
6
HV732
HV732 Timing Diagram
30Us
30Us
EN
PIN
NIN
PDR
NDR
VPP
HVout
0V
1us
VNN
DAMP
CLAMP
1us
VPP
2mA
IAVDD
1.5mA
0.175mA
NR040506
7
HV732
HV732 TX Switching Time Diagram
NIN
50%
50%
PIN
tr
tdr
VPP
90%
90%
tdf
10%
90%
10%
10%
HVOUT
VNN
tf
HV732 DAMP Switching Time Diagram
50%
50%
50%
tDMPON(N)
DAMP
50%
tDMPON(P)
0V
VPP
90%
tDMPOFF(N)
90%
DAMPOUT
10%
tDMPOFF(P)
10%
0V
VNN
HV732 Clamp Switching Time Diagram
50%
50%
CLAMP
50%
tCLPON(P)
tCLPOFF(P)
VPP
50%
tCLPOFF(N)
tCLPON(N)
90%
90%
0V
HVOUT
0V
10%
10%
VNN
NR040506
8
HV732
Pin Description
Pin
Function
Description
1
DMPO
Output of low voltage drive buffer for P-channel damp, 10nF external cap to pin 34 (DMPI)
2
GND
Drive power ground
3
NDR
Output of low voltage drive buffer for N-DMOS, 10nF external cap to pin 9 (NGATE)
4
VDD
Positive voltage supply for drive circuitry (+12V)
5
VDD
Positive voltage supply for drive circuitry (+12V)
6
VSUB
Substrate connection of control / driver die chip (connected to the most positive supply, VPP)
7
RGNDN
Ground return of damp N-DMOS source
8
OUTN
Output of damp N-DMOS drain (open drain output)
9
NGATE
Gate input of the high voltage N-DMOS, 10nF external cap from pin 3 (NDR)
10
VNN
Negative high voltage power supply (-100V)
11
VNN
Negative high voltage power supply (-100V)
12
VNN
Negative high voltage power supply (-100V)
13
VNN
Negative high voltage power supply (-100V)
14
VNN
Negative high voltage power supply (-100V)
15
TXN
Output of the high voltage N-DMOS drain (open drain output)
16
TXN
Output of the high voltage N-DMOS drain (open drain output)
17
NC
No connection
18
TXP
Output of the high voltage P-DMOS drain (open drain output)
19
TXP
Output of the high voltage P-DMOS drain (open drain output)
20
VPP
Positive high voltage power supply (+100V)
21
VPP
Positive high voltage power supply (+100V)
22
VPP
Positive high voltage power supply (+100V)
23
VPP
Positive high voltage power supply (+100V)
24
VPP
Positive high voltage power supply (+100V)
25
PGATE
Gate input of the high voltage P-DMOS, 10nF external cap from pin 31 (PDR)
26
OUTP
Damp P-DMOS drain (open drain output)
27
RGNDP
Ground return of damp P-DMOS
28
VSUB
Substrate connection of control / driver die chip (connected to the most positive supply, VPP)
29
VDD
Positive voltage supply for drive circuitry (+12V)
30
VDD
Positive voltage supply for drive circuitry (+12V)
31
PDR
Output of low voltage drive buffer for P-DMOS, 10nF external cap to pin 25 (PGATE)
32
GND
Drive power ground
33
GND
Drive power ground
34
DMPI
Connects to damp power P-DMOS gate, 10nF cap to pin 1 (DMPO)
35
PIN
Input logic control of the high voltage P-DMOS pin 18 &19 (TXP), Hi = on, Low = off
36
VLN
Negative low voltage power supply (–5V)
37
AVDD
Positive analog voltage power supply (+12V)
38
AGND
Analog signal ground (0V)
39
VSUB
Substrate connection of control / driver chip (connected to the most positive supply)
40
EN
Control / drive chip power enable Hi = on, Low = off
41
DAMP
Input of damp control on both pin 26 (OUTP) and pin 8 (OUTN), Hi = on, Low = off
42
CLAMP
Input of clamp switches on both gates of output P-DMOS and N-DMOS, Hi = on, Low = off
43
VLL
Positive voltage supply of low voltage logic (+1.8V to +5V)
44
NIN
Input logic control of the high voltage N-DMOS pin 15 & 16 (TXN), Hi = on, Low = off
Note: The three thermal slabs on the bottom of the package must be externally connected PAD1 to VSUB, PAD2 to TXN, and PAD3 to TXP.
NR040506
9
HV732
44-Lead QFN (K6) Package Outline
4.40 [.173]
4.20 [.165]
0.38 [.015]
0.28 [.011]
0.45 [.018]
0.35 [.014]
44
0.28 [.011]
0.23 [.009]
3.35 [.141]
3.37 [.133]
7.13 [.281]
6.87 [.271]
1
0.53 [.021]
0.48 [.019]
PAD1
0.36 [.014]
0.26 [.010]
0.74 [.029]
0.69 [.027]
PAD2
PAD3
(N)
(P)
1.77 [.070]
1.57 [.062]TYP
11
12
0.51 [.020]
0.41 [.016]
1.77 [.070]
1.57 [.062]TYP
22
7.13 [.281]
6.87 [.271]
Top View
1.00 [.039]
0.85 [.033]
0.05 [.002]
0.00 [.000]
Note:
1. Dimensions in mm. [Inch]
2. Radius is 0.127mm
3. Three thermal slabs on the bottom of the package
must be externally connected PAD1 to VSUB,
PAD2 to TXN, and PAD3 to TXP.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate
"product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices
determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest
product specifications, refer to the Supertex website: http//www.supertex.com.
©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 222-8888 / FAX: (408) 222-4895
Doc.# DSFP - HV732
NR040506
www.supertex.com
10