HV738 DATA SHEET (04/13/2009) DOWNLOAD

Supertex inc.
HV738
Four-Channel, High Speed, ±65V 750mA
Ultrasound Pulser
Features
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HVCMOS technology for high performance
High density integration ultrasound transmitter
0 to ±65V output voltage
±750mA source and sink current in Pulse mode
±110mA source and sink current in CW mode
Up to 20MHz operating frequency
Matched delay times
1.2 to 5.0V CMOS logic interface
Built-in output drain bleed resistors
The Supertex HV738 is a four-channel, monolithic, high voltage, high
speed pulse generator. It is designed for portable medical ultrasound
applications. This high voltage and high speed integrated circuit
can also be used for piezoelectric, capacitive or MEMS sensing in
ultrasonic nondestructive detection and sonar ranger applications.
The HV738 consists of a controller logic interface circuit, level
translators, MOSFET gate drivers and high power P-channel and
N-channel MOSFETs as the output stage for each channel.
The output stages of each channel are designed to provide peak
output currents over ±1.1A for pulsing, when in mode 4, with up to
±65 volt swings. When in mode 1, all the output stages drop the
peak current to ±140mA for low-voltage CW mode operation to
decrease the power consumption of the IC. The P and N type of
power FETs gate drivers are supplied by two floating 8.0VDC power
supplies referenced to VPP and VNN. This direct coupling topology
of the gate drivers not only eliminates two high voltage capacitors
per channel, but also makes the PCB layout easier.
Application
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General Description
Portable medical ultrasound imaging
Piezoelectric transducer drivers
NDT ultrasound transmission
Pulse waveform generator
Typical Application Circuit
+1.5 to 2.5V
+8.0V
C2
C1
C3
+65V VPP -8.0V
C4
0 to +65V
VPF
VPP
VSUB
VLL VDD
OTP
EN
C5
SUB
RGND
EN_PWR
MC0
Level
Translator
MC1
+1.5 to 2.5V
Logic
PIN1
RP1
P-Driver
TXP1
D1
HVOUT1
TXN1
Level
Translator
NIN1
D2
N-Driver
RN1
X1
RGND
1 of 4 Channels
GREF
Supertex inc.
VSS
HV738
VNF
C7
VNN +8V
VNN
C6
0 to -65V
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV738
Ordering Information
48-Lead QFN
Device
7.00x7.00mm body
1.00mm height (max)
0.50mm pitch
HV738
HV738K6-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Absolute Maximum Ratings
Parameter
48
Value
VSS, Power supply reference
1
0V
VLL, Positive logic supply
-0.5V to +7V
VDD, Positive logic and level translator supply
-0.5V to +14V
(VPP -VPF) Positive floating gate drive supply
-0.5V to +14V
(VNF- VNN) Negative gate floating drive supply
-0.5V to +14V
(VPP-VNN) Differential high voltage supply
48-Lead QFN
+140V
VPP, High voltage positive supply
-0.5V to +70V
VNN, High voltage negative supply
+0.5V to -70V
OTP, Over Temperature Protection output
-0.5V to +7V
All logic input PINX, NINX and EN voltages
-0.5V to +7V
(VSUB - VSS) Substrate to VSS voltage difference
+140V
(VPP –TXPX) VPP to TXPX voltage difference
+140V
(VSUB- TXPX) Substrate to TXPX voltage difference
+140V
(TXNX-VNN ) TXNX to VNN voltage difference
+140V
Operating temperature
-40°C to 125°C
Storage temperature
-65°C to 150°C
Thermal resistance, θJA
29°C/W
Thermal resistance, θJC (Junction to thermal pad)
0.5°C/W
(top view)
Package Marking
HV738K6
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Package may or may not include the following marks: Si or
48-Lead QFN
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Power-Up Sequence
Power-Down Sequence
Step
Description
Step
Description
1
VSUB
1
All logic signals go to low
2
VLL with logic signal low
2
VPP and VNN
3
VDD
3
(VPP -VPF) and (VNF –VNN)
4
(VPP -VPF) and (VNF –VNN)
4
VDD
5
VPP and VNN
5
VLL
6
Logic control signals
6
VSUB
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
HV738
Operating Supply Voltages and Current (4 Channel Active)
(Operating conditions, unless otherwise specified, VSS = 0V, VLL = +2.5V, VDD = +8V, VPP-VPF = +8V, VNN-VNF = -8V, VPP =+65V, VNN = -65V, TA = 25°C)
Sym
Parameter
Min
Typ
Max
VLL
Logic voltage reference
1.2
2.5
5.0
V
---
VDD
Internal voltage supply
7.5
8.0
10
V
---
VPF
Positive gate driver supply
(VPP -10)
(VPP -8.0)
(VPP -7.5)
V
VNF
Negative gate drive supply
(VNN +7.5) (VNN +8.0)
(VNN +10)
V
VSUB
IC substrate voltage
VDD
VPP
+65
V
Must be the most positive potential
of the IC.
VPP
Positive HV supply
0
-
+65
V
---
VNN
Negative HV supply
-65
-
0
V
---
Slew rate limit of VPP, VNN
-
-
25
V/μs
ILL
VLL Current EN = Low
-
35
120
μA
---
IDDQ
VDD Current EN = Low
-
10
-
μA
---
IDDEN
VDD Current EN = High
-
0.75
2.0
mA
f = 0MHz
IDDEN
VDD Current MODE = 4
-
2.0
-
mA
IDDENCW
VDD Current MODE = 1
-
5.0
-
mA
IPPQ
VPP Current EN = Low
-
10
20
μA
IPPEN
VPP Current MODE = 4
-
200
-
mA
IPPENCW
VPP Current MODE = 1
-
140
-
mA
INNQ
VNN Current EN = Low
-
10
20
μA
INNEN
VNN Current MODE = 4
-
170
-
mA
INNENCW
VNN Current MODE = 1
-
140
-
mA
IPFQ
VPF Current EN = Low
-
8.0
20
μA
IPFEN
VPF Current MODE = 4
-
30
-
mA
IPFENCW
VPF Current MODE = 1
-
10
-
mA
INFQ
VNF Current EN = Low
-
10
20
μA
INFEN
VNF Current MODE = 4
-
12
-
mA
INFENCW
VNF Current MODE = 1
-
5.0
-
mA
SRMAX
Units Conditions
Floating driver voltage supplies.
Built-in slew rate detection protection.
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
f = 0MHz
f = 5.0MHz, continuous, no loads
Under Voltage and Over Temperature Protection
Sym
Parameter
VPULL_UP Open drain pull-up voltage
Min
Typ
Max
Units Conditions
-
-
5.0
V
---
VUVDD
VDD threshold
3.5
-
6.5
V
---
VUVLL
VLL threshold
0.7
-
1.0
V
---
VUVVF
VPF, VNF threshold
3.5
-
6.5
V
---
OTP flag output low voltage
-
-
1.0
V
VLL = 2.5V, OTP = Active,
IPULL_UP = 1.0mA.
IOTP
Max. open drain output
current
-
1.0
-
mA
---
TOTP
Over temperature threshold
95
110
125
THYS
OTP output reset hysteresis
-
7.0
-
°C
If over temperature occurred, OTP
low and all TX outputs will be HiZ.
VOL_OTP
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV738
DC Electrical Characteristics
(Operating conditions, unless otherwise specified, VSS = 0V, VLL= +2.5V, VDD = +8V, VPP-VPF = +8V, VNN-VNF = -8V, VPP = +65V, VNN = -65V,TA = 25°C)
Output P-Channel MOSFET, TXP (Mode 4)
Sym
Parameter
Min
Typ
Max
Units Conditions
IOUT
Output saturation current
0.75
1.2
-
A
---
RON
Channel resistance
-
13
-
Ω
ISD = 100mA
COSS
Output capacitance
-
50*
-
pF
VDS = 25V, f = 1.0MHz
Output N-Channel MOSFET, TXN (Mode 4)
Sym
Parameter
Min
Typ
Max
Units Conditions
IOUT
Output saturation current
0.75
1.1
-
A
---
RON
Channel resistance
-
12.5
-
Ω
ISD = 100mA
COSS
Output capacitance
-
20*
-
pF
VDS = 25V, f = 1.0MHz
Min
Typ
Max
10
20
30
kΩ
---
-
-
40
mW
---
Min
Typ
Max
MOSFET Drain Bleed Resistor
Sym
Parameter
RP/N1~4
Output bleed resistance
PRO
Bleed resistors power limit
Units Conditions
Logic Inputs
Sym
Parameter
VIH
Input logic high voltage
(VLL -0.4)
-
VLL
VIL
Input logic low voltage
0
-
IIH
Input logic high current
-
-
IIL
Input logic low current
-10
CIN
Input logic capacitance
-
Units Conditions
V
---
0.4
V
---
10
μA
---
-
-
μA
---
-
5.0*
pF
---
AC Electrical Characteristics
(Operating conditions, unless otherwise specified, VSS = 0V, VLL = +2.5V, VDD = +8V, VPP - VPF = +8V, VNN - VNF= -8V, VPP = +65V, VNN = -65V, TA= 25°C)
Sym
Parameter
Min
Typ
Max
Units Conditions
tr
Output rise time
-
35
-
ns
tf
Output fall time
-
43
-
ns
fOUT
Output frequency range
-
-
20
MHz
HD2
Second harmonic distortion
-
-35*
-
dB
tEN
Enable time
-
180
500
μs
tDIS
Disable time
-
2.8
10
μs
tdr
Delay time on inputs rise
-
22
-
ns
tdf
Delay time on inputs fall
-
22
-
ns
7.5Ω resistor load
(see timing diagram)
Delay time matching
-
±3.0
-
ns
P to N, channel to channel
tdm
Delay on mode change
-
2.5
10
μs
100Ω resistor load
tj
Delay jitter on rise or fall
-
13*
-
ps
VPP/VNN = ±25V, input tr 50% to HVOUT
tr or tf 50%, with 330pF//2.5kΩ load
ΔtDELAY
330pF//2.5kΩ load
100Ω resistor load
* Guaranteed by design.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
HV738
Switch AC Test Timing Diagram
NINx
50%
50%
PINx
tdf
tdr
Output
90%
VPP
10%
0
tr
tr
10%
VNN
VLL
OTP
EN
90%
VSUB
VDD
VPF
VPP
SUB
RGND
EN_PWR
MC0
Level
Translator
MC1
PIN1
RP1
P-Driver
TXP1
TXN1
Level
Translator
NIN1
N-Driver
RN1
1of n Channels
GREF
R1
RGND
VSS
VNF
50%
PINx
R2
tdfp
tdrp
IOUT
NINx
VNN
50%
tdfn
tdrn
50%
TXPx
0A
TXNx 0A
50%
IOUT
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
HV738
Truth Table (All Modes)
Logic Inputs
Output
EN
PINX
NINX
TXPX
TXNX
1
0
0
OFF
OFF
1
1
0
ON
OFF
1
0
1
OFF
ON
1
1
1
†
ON
ON†
0
X
X
OFF
OFF
† Not allowed, may damage IC.
Drive Mode Control Table
ISC
RONP
RONR
(A)
(Ω)
(Ω)
0
0.28
56.0
54.0
0
1
0.38
41.0
39.5
3
1
0
0.65
24.0
23.0
4
1
1
1.20
13.0
12.5
Mode
MC1
MC0
1
0
2
Notes:
1. VPP/VNN = +/-65V, VDD = (VPP – VPF) = (VNF – VNN) = +8.0V
2. ISC is current into 1.0Ω to GND
3. RON calculated from VOUT into 100Ω load
Pin Description
Pin #
Name
Function
1
VDD
Positive internal voltage supply (+8.0V).
2
VSS
Power supply return (0V).
3
PIN1
Input logic control of high voltage output P-FET of channel 1, Hi = on, Low = off.
4
NIN1
Input logic control of high voltage output N-FET of channel 1, Hi = on, Low = off.
5
PIN2
Input logic control of high voltage output P-FET of channel 2, Hi = on, Low = off.
6
NIN2
Input logic control of high voltage output N-FET of channel 2, Hi = on, Low = off.
7
PIN3
Input logic control of high voltage output P-FET of channel 3, Hi = on, Low = off.
8
NIN3
Input logic control of high voltage output N-FET of channel 3, Hi = on, Low = off.
9
PIN4
Input logic control of high voltage output P-FET of channel 4, Hi = on, Low = off.
10
NIN4
Input logic control of high voltage output N-FET of channel 4, Hi = on, Low = off.
11
VSS
Power supply return (0V).
12
VDD
Positive internal voltage supply (+8.0V).
13
OTP
Over temperature protection output, open N-FET drain, active low if IC temperature >110°C.
14
MC1
15
MC0
16
Thermal Pad
(VSUB)
17
VPF
Output current mode control pins, see Drive Mode Control Table.
Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on
the bottom of package.
It must be connected to VSUB, the most positive potential of the IC externally.
P-FET drive floating power supply, (VPP- VPF) = +8.0V.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
6
HV738
Pin Description (cont.)
Pin #
Name
Function
18
19
VPP
Positive high voltage power supply (+65V).
VNN
Negative high voltage power supply (-65V).
24
VNF
N-FET drive floating power supply, (VNF- VNN) = +8.0V.
25
Thermal Pad
(VSUB)
26
RGND
Bleed resistors common return ground. (Both pins must be used)
27
TXN4
Output N-FET drain (open drain output) for channel 4.
28
TXP4
Output P-FET drain (open drain output) for channel 4.
29
TXN3
Output N-FET drain (open drain output) for channel 3.
30
TXP3
Output P-FET drain (open drain output) for channel 3.
31
TXN2
Output N-FET drain (open drain output) for channel 2.
20
21
22
23
Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on
the bottom of package.
It must be connected to VSUB, the most positive potential of the IC externally.
32
TXP2
Output P-FET drain (open drain output) for channel 2.
33
TXN1
Output N-FET drain (open drain output) for channel 1.
34
TXP1
Output P-FET drain (open drain output) for channel 1.
35
RGND
Bleed resistors common return ground. (Both pins must be used)
36
Thermal Pad
(VSUB)
37
VNF
N-FET drive floating power supply, (VNF- VNN) = +8.0V.
VNN
Negative high voltage power supply (-65V).
VPP
Positive high voltage power supply (+65V).
44
VPF
P-FET drive floating power supply, (VPP- VPF) = +8.0V.
45
Thermal Pad
(VSUB)
Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on
the bottom of package.
It must be connected to VSUB, the most positive potential of the IC externally.
38
39
40
41
42
43
Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on
the bottom of package.
It must be connected to VSUB, the most positive potential of the IC externally.
46
EN
47
GREF
Chip power enable Hi = on, Low = off.
Logic Low reference, logic ground (0V).
48
VLL
Logic Hi voltage reference input (+2.5V).
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
HV738
48-Lead QFN Package Outline (K6)
7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch
D2
D
48
48
Note 1
(Index Area
D/2 x E/2)
1
1
Note 1
(Index Area
D/2 x E/2)
e
E
E2
b
View B
Top View
Bottom View
Note 3
θ
A3
A
A1
L
Seating
Plane
L1
Note 2
View B
Side View
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
Dimension
(mm)
A
A1
MIN
0.80
0.00
NOM
0.90
0.02
MAX
1.00
0.05
A3
0.20
REF
b
D
D2
E
E2
e
0.18
6.85*
1.25
6.85*
1.25
0.25
7.00
-
7.00
-
0.30
7.15*
5.45
7.15*
5.45
0.50
BSC
L
L1
θ
0.00
0O
0.40†
-
-
0.50
0.15
14O
0.30
†
†
JEDEC Registration MO-220, Variation VKKD-6, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc.#: DSPD-48QFNK67X7P050, Version C041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV738
C041309
8
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com