Supertex inc. HV7360 High Speed, ±100V 2.5A, Two or Three Level Ultrasound Pulser Features General Description ►► HVCMOS technology for high performance ►► High density integration AC coupled pulser ►► 0 to ±100V output voltage ►► ±2.5A source and sink minimum pulse current ►► Up to 35MHz operating frequency ►► 2.0ns matched delay times ►► 2.5, 3.3 or 5.0V CMOS logic interface ►► Low power consumption and very simple to use The Supertex HV7360 is a high voltage, high-speed, pulse generator with built-in, fast return to zero damping FETs. This high voltage and high-speed integrated circuit is designed for portable medical ultrasound image devices, but can also can be used for NDT and test equipment applications. ® The HV7360 consists of a controller logic interface circuit, level translators, AC coupled MOSFET gate drivers and high voltage and high current P-channel and N-channel MOSFETs as the output stage. Application The peak output currents of each channel are guaranteed to be over ±2.5A with up to ±100V of pulse swing. The AC coupling topology for the gate drivers not only saves two floating voltage supplies, it also makes the PCB layout easier. ►► Medical ultrasound imaging ►► Piezoelectric transducer drivers ►► NDT ultrasound transmission ►► Pulse waveform generator Typical RTZ Application Circuit +10V +10V VDD VH SP1 +2.5/3.3V VLL PE DP1 HVOUT DN1 INA 2.5/3.3V Logic Input VPP 0 to +100V VL3 VNN 0 to -100V INB SN1 SP2 INC DP2 IND DN2 GND Supertex inc. VSS VL1 VL2 SN2 ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV7360 Ordering Information Part Number Package Option Packing HV7360LA-G 22-Lead LFGA 364/Tray -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VDD – VSS Logic supply voltage -0.5 to +12.5V VH Output high supply voltage VL -0.5 to VDD +0.5V VL Output low supply voltage 9 8 7 VSS -0.5V to VH +0.5V 6 -6.0 to +0.5V 5 +220V 4 VSS Low side supply voltage (VSPx - VSNx) Differential high voltage VSPx Positive high voltage -0.5 to +110V VSNx Negative high voltage +0.5 to -110V All logic input voltages Pad Configuration 3 2 1 VSS -0.5V to GND +5.5V Coupling capacitor breakdown voltage ±110V Maximum junction temperature 125°C Operating temperature -20 to +85°C A 22-Lead LFGA 106OC/W Power-Up Sequence D E F G H J K L 22-Lead LFGA (LA) M N P Package Marking HV7360 LLLLLL YYWW AAACCC Typical Thermal Resistance θja C (top view) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Package B L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 22-Lead LFGA (LA) Logic Control Table Step Description 1 VLL 2 VDD, VH, VSS, VL with signal logic low 3 VPP and VNN 4 PE active Input Pulse PE Power-Down Sequence Step Description 1 PE inactive 2 VPP and VNN off 3 VDD, VH, VSS, VL off 4 VLL off Note: Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in order to minimize possible inrush current. Supertex inc. 1 0 Output MOSFETs INA INB INC IND SP1 to DP1 DN1 to SN1 SP2 to DP2 DN2 to SN2 1 X X X ON X X X X 1 X X X ON X X X X 1 X X X ON X X X X 1 X X X ON 0 X X X OFF X X X X 0 X X X OFF X X X X 0 X X X OFF X X X X 0 X X X OFF X X X X OFF OFF OFF OFF ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 HV7360 Operating Supply Voltages and Current (Operating conditions, unless otherwise specified, GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = -100V, TA = 25°C) Sym Parameter VDD – VSS Supply voltage Min Typ Max Unit 4.75 - 11.50 V 4.0 ≤ VDD ≤ 11.5V -5.5 - 0 V --- VSS Low side supply voltage VH Output high supply voltage VSS +4.0 - VDD V VL Output low supply voltage VSS - VDD -4.0 V IDDQ VDD quiescent current - 50 - μA IHQ VH quiescent current - 2.0 - μA IDDQ VDD quiescent current - 1.0 - mA IHQ VH quiescent current - 2.0 - μA IDD VDD average current - 4.0 - mA IH VH average current - 10 - mA VIH Input logic voltage high VPE -0.3 - VPE V VIL Input logic voltage low 0 - 0.3 V IIH Input logic current high - - 1.0 μA IIL Input logic current low - - 1.0 μA VPEH PE input logic voltage high 1.70 3.30 5.25 V VPEL PE input logic voltage low 0 - 0.3 V RINPE PE input impedance to GND 100 - - kΩ Conditions VH - VL ≥ 4.0V No input transitions, PE = 0 No input transitions, PE = 1 One channel ON at 5.0Mhz, No load For logic inputs INA, INB, INC, and IND For logic input PE AC Electrical Characteristics (Operating conditions, unless otherwise specified, GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = -100V, TA = 25°C) Sym Min Typ Max Unit Input or PE rise & fall time - - 10 ns Logic input edge speed requirement td1-4 Input to output delay - 7.5 - ns RLOAD = 1.0Ω tr/f1-2 Output rise/fall time - 9.5 - ns CLOAD = 330pF, RLOAD = 2.5kΩ Δtrf Rise and fall time matching - 2.0 - ΔtdC2C Propagation matching - 1.0 - ns Channel to channel ΔtdD2D Propagation delay matching - ±2.0 - ns Device to device delay match tPE-ON PE ON-time - - 5.0 tPE –OFF PE OFF-time - - 4.0 µs VPE = 1.7 ~ 5.25V VDD = 7.5 ~ 11.5V -20 ~ 85OC COG Output to MOSFET gate cap - 10 - nF 100V X7S CVH VH to VL3 decoupling cap - 0.22 - µF 16V X7R tirf Parameter Supertex inc. Conditions ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 HV7360 Pulser & Damping P-Channel MOSFET Sym Parameter Min Typ Max Unit BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA - - 4.5 ΔVGS(th) Change in VGS(th) with temperature Conditions mV/ C VGS = VDS, ID = -1.0mA O RGS Gate-to-source shunt resistor 10 - 50 kΩ IGS = 100µA, if applied VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2.0mA, if applied - - -10 μA IDSS Zero gate voltage drain current VDS = max rating, VGS = 0V - - -1.0 mA VDS = 0.8max rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current -1.2 - - -2.3 -2.5 - - - 8.5 - - 7.0 - - 1.0 400 - - RDS(ON) ΔRDS(ON) Static drain-to-source ON-state resistance Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 75 - COSS Common source output capacitance - 21 - CRSS Reverse transfer capacitance - 6.5 - VSBD Diode forward voltage drop and reverse recovery time of body-diode - - - trrBD A Ω %/ C O VGS = -5.0V, VDS = -25V VGS = -10V, VDS = -50V VGS = -5.0V, ID = -150mA VGS = -10V, ID = -1.0A VGS = -10V, ID = -1.0mA mmho VDS = -25V, ID = -500mA pF VGS = 0V, VDS = -25V, f = 1.0MHz 1.8 V VGS = 0V, ISD = 500mA 300 - ns --- Pulser & Damping N-Channel MOSFET Sym Parameter Min Typ Max Unit BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA - - -4.5 ΔVGS(th) Change in VGS(th) with temperature Conditions mV/OC VGS = VDS, ID = 1.0mA RGS Gate-to-source shunt resistor 10 - 50 kΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA - - 10 μA VDS = max rating, VGS = 0V - - 1.0 mA VDS = 0.8max rating, VGS = 0V, TA = 125OC 1.3 - - 2.3 2.5 - - - 6.5 - - 6.0 - - 1.0 400 - - IDSS Zero gate voltage drain current ID(ON) ON-state drain current RDS(ON) ΔRDS(ON) Static drain-to-source ON-state resistance Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 56 - COSS Common source output capacitance - 13 - CRSS Reverse transfer capacitance - 2.0 - VSBD Diode forward voltage drop and reverse recovery time of body-diode - - - 300 trrBD Supertex inc. A Ω %/ C O VGS = 5.0V, VDS = 25V VGS = 10V, VDS = 50V VGS = 5.0V, ID = 150mA VGS = 10V, ID = 1.0A VGS = 10V, ID = 1.0A mmho VDS = 25V, ID = 500mA pF VGS = 0V, VDS = 25V, f = 1.0MHz 1.8 V VGS = 0V, ISD = 500mA - ns --- ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4 HV7360 Switch Timing and Delay Test +10V +10V VDD VH +100V VL3 +2.5/3.3V VLL SP1 PE DP1 DN1 INA 2.5/3.3V Logic Input -100V INB SN1 SP2 INC DP2 IND DN2 GND VSS SN2 VL 50% INA INB 50% INB td3 td1 IOUT INA td4 td2 50% tf2 tr1 TX + DMP 90% tr2 tf1 TX + DMP 10% 0A 0A 50% IOUT 10% 90% Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 5 HV7360 Typical Unipolar 2-Channel Application Circuit +10V +10V VDD VH VL3 SP1 +2.5/3.3V VLL PE DP1 TX1 DN1 INA 2.5/3.3V Logic Input VPP = 0 to +100V INB SN1 INC SP2 DP2 IND VPP DN2 GND VSS VL1 VL2 TX2 SN2 Pad Description Pad Location Name Function A1 GND Driver and level translator circuit ground return (0V) A2 IND Damping N-FET control signal logic Input, controlling N-FET2 A3 INC Damping P-FET control signal logic Input, controlling P-FET2 A4 VSS Negative voltage power supply (0V) A6 VDD Positive voltage supply (+10V), should connect to an external decoupling cap to VSS (0V) A7 INB Pulsing N-FET control signal logic Input, controlling N-FET1 A8 INA Pulsing P-FET control signal logic Input, controlling P-FET1 A9 PE Drive power enable Hi = ON, Low = OFF , logic “1” voltage reference input (+1.8 to +3.3V) B2 VL2 Gate-Drive negative voltage power supply (0V) B8 VL1 Gate-Drive negative voltage power supply (0V) F4 VH Gate driver positive voltage power supply (+10V) F7 VL3 VH to VL decoupling cap, should connect to VL1 & VL2 (0V) ground plane as short as possible G4 NC Do not connect P1 SP2 Source of P-FET2, positive high voltage power supply (0 to +100V) or GND P2 DP2 Drain of P-FET2, transmit pulser output P3 DN2 Drain of N-FET2, transmit pulser output Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 6 HV7360 Pad Description (cont.) Pad Location Name P4 SN2 Source of N-FET2, negative high voltage power supply (0 to -100V) or GND P5 NC Do not connect P6 SP1 Source of P-FET1, positive high voltage power supply (0 to +100V) P7 DP1 Drain of P-FET1, transmit pulser output P8 DN1 Drain of N-FET1, transmit pulser output P9 SN1 Source of N-FET1, negative high voltage power supply (0 to -100V) Function Pad Configuration 0.50mm 2.00mm 7.0mm 0.50mm 3.50mm 9 0.50mm 8 7 5.0mm 6 5 4.0mm 4 3 2 1 A B C D E F G H J K L M N P (Top View) Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 7 HV7360 22-Lead LFGA Package Outline (LA) 5.00x7.00mm body, 0.85mm height (max), 0.50mm pitch e D 9 8 7 6 5 4 3 2 1 A e B C e1 D E Note 1 (Index Area D1/4 x E1/4) F e G E H J K e2 L M N P e3 Top View Bottom View View A b A b Side View View A Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A b D E MIN 0.75 0.20 4.925 6.925 NOM 0.80 0.25 5.000 7.000 MAX 0.85 0.30 5.075 7.075 e e1 e2 e3 0.50 BSC 2.00 BSC 3.50 BSC 4.00 BSC Drawings not to scale. Supertex Doc. #: DSPD-22LFGALA, Version A052511. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV7360 A040512 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com