MAXIM MAX8733A

19-3711; Rev 0; 5/05
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
The MAX8732A/MAX8733A/MAX8734A dual step-down,
switch-mode power-supply (SMPS) controllers generate
logic-supply voltages in battery-powered systems. The
MAX8732A/MAX8733A/MAX8734A include two pulsewidth modulation (PWM) controllers, adjustable from 2V to
5.5V or fixed at 5V and 3.3V. These devices feature two
linear regulators providing 5V and 3.3V always-on outputs. Each linear regulator provides up to 100mA output
current with automatic linear-regulator bootstrapping to
the main SMPS outputs. The MAX8732A/MAX8733A/
MAX8734A include on-board power-up sequencing, a
power-good (PGOOD) output, digital soft-start, and internal soft-stop output discharge that prevents negative voltages on shutdown. Additionally, the outputs are high
impedance when VCC falls below its UVLO set point while
the outputs are enabled.
Maxim’s proprietary Quick-PWM™ quick-response, constant on-time PWM control scheme operates without
sense resistors and provides 100ns response to load transients while maintaining a relatively constant switching frequency. The unique ultrasonic pulse-skipping mode
maintains the switching frequency above 25kHz, which
eliminates noise in audio applications. Other features
include pulse skipping, which maximizes efficiency in
light-load applications, and fixed-frequency PWM mode,
which reduces RF interference in sensitive applications.
The MAX8732A features a 200kHz/5V and 300kHz/3.3V
SMPS for highest efficiency, while the MAX8733A features a 400kHz/5V and 500kHz/3.3V SMPS for “thin and
light” applications. The MAX8734A provides a pinselectable switching frequency, allowing either 200kHz/
300kHz or 400kHz/500kHz operation of the 5V/3.3V
SMPSs, respectively. The MAX8732A/MAX8733A/
MAX8734A are available in 28-pin QSOP packages and
operate over the extended temperature range
(-40°C to +85°C).
The MAX8732A/MAX8733A/MAX8734A are pin-for-pin
upgrades to the MAX1777/MAX1977/MAX1999.
The MAX1999 evaluation kit (EV kit) can be used to
evaluate the MAX8732A/MAX8733A/MAX8734A.
Applications
Features
♦ No Current-Sense Resistor Needed (MAX8734A)
♦ Accurate Current Sense with Current-Sense
Resistor (MAX8732A/MAX8733A)
♦ 1.5% Output Voltage Accuracy
♦ 3.3V and 5V 100mA Bootstrapped Linear
Regulators
♦ Internal Soft-Start and Soft-Stop Output
Discharge
♦ Quick-PWM with 100ns Load Step Response
♦ 3.3V and 5V Fixed or Adjustable Outputs
(Dual Mode™)
♦ 4.5V to 24V Input Voltage Range
♦ Enhanced Ultrasonic Pulse-Skipping Mode
(25kHz min)
♦ Power-Good (PGOOD) Signal
♦ Overvoltage Protection Enable/Disable
Ordering Information
PART
PINTEMP RANGE
PACKAGE
MAX8732AEEI+ -40°C to +85°C 28 QSOP
MAX8732AEEI
-40°C to +85°C 28 QSOP
200/300
MAX8733AEEI+ -40°C to +85°C 28 QSOP
400/500
MAX8733AEEI
400/500
-40°C to +85°C 28 QSOP
Ordering Information continued at end of data sheet.
+Denotes lead-free package.
Pin Configurations
TOP VIEW
N.C. 1
28 BST3
PGOOD 2
27 LX3
ON3 3
26 DH3
ON5 4
25 LDO3
ILIM3 5
SHDN 6
24 DL3
MAX8734A
23 GND
FB3 7
22 OUT3
REF 8
21 OUT5
FB5 9
20 V+
PDAs and Mobile Communication Devices
PRO 10
19 DL5
3- and 4-Cell Li+ Battery-Powered Devices
ILIM5 11
18 LDO5
SKIP 12
17 VCC
TON 13
16 DH5
BST5 14
15 LX5
Notebook and Subnotebook Computers
Quick-PWM and Dual Mode are trademarks of Maxim
Integrated Products, Inc.
5V/3.3V
SWITCHING
FREQUENCY
(kHz)
200/300
QSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8732A/MAX8733A/MAX8734A
General Description
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
V+, SHDN to GND ..................................................-0.3V to +25V
BST_ to GND ..........................................................-0.3V to +30V
LX_ to BST_ ..............................................................-6V to +0.3V
CS_ to GND (MAX8732A/MAX8733A only) .................-2V to +6V
VCC, LDO5, LDO3, OUT3, OUT5, ON3, ON5, REF,
FB3, FB5, SKIP, PRO, PGOOD to GND ...............-0.3V to +6V
DH3 to LX3 ..............................................-0.3V to (VBST3 + 0.3V)
DH5 to LX5 ..............................................-0.3V to (VBST5 + 0.3V)
ILIM3, ILIM5 to GND...................................-0.3V to (VCC + 0.3V)
DL3, DL5 to GND....................................-0.3V to (VLDO5 + 0.3V)
TON to GND (MAX8734A only) ................................-0.3V to +6V
LDO3, LDO5, REF Short Circuit to GND ....................Momentary
LDO3 Current (internal regulator) Continuous................+100mA
LDO3 Current (switched over to OUT3) Continuous ......+200mA
LDO5 Current (internal regulator) Continuous................+100mA
LDO5 Current (switched over to OUT5) Continuous ......+200mA
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN SMPS CONTROLLERS
V+ Input Voltage Range
3.3V Output Voltage in
Fixed Mode
5V Output Voltage in Fixed Mode
LDO5 in regulation
V+ = LDO5, VOUT5 < 4.43V
V+ = 6V to 24V, FB3 = GND, V SKIP = 5V
V+ = 6V to 24V, FB5 = GND, V SKIP = 5V,
MAX8732A/MAX8734A (TON = VCC)
6
24
4.5
5.5
V
3.285
3.330
3.375
V
4.975
5.050
5.125
V
1.975
2.00
2.025
V
V+ = 7V to 24V, FB5 = GND, V SKIP = 5V,
MAX8733A/MAX8734A (TON = GND)
Output Voltage in
Adjustable Mode
V+ = 6V to 24V, either SMPS
Output Voltage Adjust Range
Either SMPS
2.0
5.5
V
FB3, FB5 Adjustable-Mode
Threshold Voltage
Dual-Mode comparator
0.1
0.2
V
DC Load Regulation
Either SMPS, V SKIP = 5V, 0 to 5A
-0.1
Either SMPS, SKIP = GND, 0 to 5A
-1.5
Either SMPS, V SKIP = 2V, 0 to 5A
-1.7
Line Regulation
Either SMPS, 6V < V+ < 24V
Current-Limit Threshold
(Positive, Default)
ILIM_ = VCC, GND - CS_ (MAX8732A/MAX8733A),
GND - LX_ (MAX8734A)
Current-Limit Threshold
(Positive, Adjustable)
GND - CS_
(MAX8732A/MAX8733A),
GND - LX_ (MAX8734A)
%
0.005
VILIM_ = 0.5V
%/V
93
100
107
40
50
60
VILIM_ = 1V
93
100
107
VILIM_ = 2V
185
200
215
mV
mV
Zero-Current Threshold
SKIP = GND, ILIM_ = VCC, GND - CS_
(MAX8732A/MAX8733A), GND - LX_ (MAX8734A)
3
mV
Current-Limit Threshold
(Negative, Default)
SKIP = ILIM_ = VCC, GND - CS_
(MAX8732A/MAX8733A), GND - LX_ (MAX8734A)
-120
mV
Soft-Start Ramp Time
Zero to full limit
1.7
ms
2
_______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Operating Frequency
CONDITIONS
MAX8732A or MAX8734A
(VTON = 5V), SKIP = VCC
3.3V SMPS
300
MAX8733A or MAX8734A
(VTON = 0), SKIP = VCC
5V SMPS
400
3.3V SMPS
500
MAX
25
36
VOUT5 = 5.05V
1.895
2.105
2.315
VOUT3 = 3.33V
0.833
0.925
1.017
MAX8733A or MAX8734A
(VTON = 0)
VOUT5 = 5.05V
0.895
1.052
1.209
VOUT3 = 3.33V
0.475
0.555
0.635
250
300
350
MAX8732A or MAX8734A
(VTON = 5V)
VOUT5 = 5.05V
94
VOUT3 = 3.33V
91
MAX8733A or MAX8734A
(VTON = 0)
VOUT5 = 5.05V
88
VOUT3 = 3.33V
INTERNAL REGULATOR AND REFERENCE
LDO5 Output Voltage
ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO5 < 100mA
UNITS
kHz
MAX8732A or MAX8734A
(VTON = 5V)
Minimum Off-Time
Maximum Duty Cycle
TYP
200
SKIP = REF
On-Time Pulse Width
MIN
5V SMPS
µs
ns
%
85
4.90
5.00
5.10
LDO5 Short-Circuit Current
LDO5 = GND
LDO5 Undervoltage-Lockout
Fault Threshold
Falling edge of LDO5, hysteresis = 1%
3.7
4.0
4.3
V
LDO5 Bootstrap Switch Threshold
Falling edge of OUT5, rising edge at OUT5 regulation
point
4.43
4.56
4.69
V
LDO5 Bootstrap
Switch Resistance
LDO5 to OUT5, VOUT5 = 5V
1.4
3.2
Ω
3.35
3.42
LDO3 Output Voltage
ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO3 < 100mA
LDO3 Short-Circuit Current
LDO3 = GND
LDO3 Bootstrap Switch Threshold
Falling edge of OUT3, rising edge at OUT3 regulation
point
LDO3 Bootstrap Switch
Resistance
LDO3 to OUT3, VOUT3 = 3.2V
REF Output Voltage
No external load
REF Load Regulation
0 < ILOAD < 50µA
REF Sink Current
REF in regulation
190
V
3.28
mA
180
2.80
1.980
V
mA
2.91
3.02
V
1.5
3.5
Ω
2.000
2.020
V
10
mV
10
µA
V+ Operating Supply Current
LDO5 switched over to OUT5, 5V SMPS
25
50
µA
V+ Standby Supply Current
V+ = 6V to 24V, both SMPSs off, includes ISHDN
150
250
µA
V+ Shutdown Supply Current
V+ = 4.5V to 24V
6
15
µA
Quiescent Power Consumption
Both SMPSs on, FB3 = FB5 = SKIP = GND, VOUT3 =
3.5V, VOUT5 = 5.3V
3
4.5
mW
+11
+14
%
FAULT DETECTION
Overvoltage Trip Threshold
FB3 or FB5 with respect to nominal regulation point
+8
_______________________________________________________________________________________
3
MAX8732A/MAX8733A/MAX8734A
ELECTRICAL CHARACTERISTICS (continued)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
Overvoltage Fault
Propagation Delay
FB3 or FB5 delay with 50mV overdrive
PGOOD Threshold
FB3 or FB5 with respect to nominal output, falling edge,
typical hysteresis = 1%
PGOOD Propagation Delay
Falling edge, 50mV overdrive
PGOOD Output Low Voltage
ISINK = 4mA
PGOOD Leakage Current
High state, forced to 5.5V
MIN
TYP
MAX
10
-12
-9.5
µs
-7
10
Thermal-Shutdown Threshold
UNITS
%
µs
0.3
V
1
µA
o
+160
C
Output Undervoltage
Shutdown Threshold
FB3 or FB5 with respect to nominal output voltage
65
70
75
%
Output Undervoltage
Shutdown Blanking Time
From ON_ signal
10
22
35
ms
-200
+40
+200
nA
INPUTS AND OUTPUTS
Feedback Input Leakage Current
PRO Input Voltage
VFB3 = VFB5 = 2.2V
Low level
High level
0.6
1.5
Low level
SKIP Input Voltage
TON Input Voltage
0.8
Float level
1.7
High level
2.4
2.3
Low level
High level
0.8
2.4
Clear fault level/SMPS off level
ON3, ON5 Input Voltage
Input Leakage Current
SHDN Input Trip Level
1.7
SMPS on level
2.4
V PRO or VTON = 0 or 5V
-1
2.3
-2
+2
V SKIP = 0 or 5V
-1
+1
V SHDN = 0 or 24V
-1
+1
VCS_ = 0 or 5V
-2
+2
VILIM3, VILIM5 = 0 or 2V
-0.2
Rising edge
1.2
1.6
2.0
Falling edge
0.96
1.00
1.04
DL_ Gate-Driver Source Current
V
V
+1
VON_ = 0 or 5V
DH3, DH5 forced to 2V
V
0.8
Delay start level
DH_ Gate-Driver
Sink/Source Current
V
µA
+0.2
V
2
A
DL3 (source), DL5 (source), forced to 2V
1.7
A
DL_ Gate-Driver Sink Current
DL3 (sink), DL5 (sink), forced to 2V
3.3
DH_ Gate-Driver On-Resistance
BST - LX_ forced to 5V
1.5
4.0
DL_, high state (pullup)
2.2
5.0
DL_, low state (pulldown)
0.6
1.5
DL_ Gate-Driver On-Resistance
4
_______________________________________________________________________________________
A
Ω
Ω
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
OUT3, OUT5 Discharge-Mode
On-Resistance
OUT3, OUT5 Discharge-Mode
Synchronous Rectifier
Turn-On Level
0.2
TYP
MAX
UNITS
12
40
Ω
0.3
0.4
V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = V CC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN SMPS CONTROLLERS
V+ Input Voltage Range
3.3V Output Voltage in
Fixed Mode
5V Output Voltage in Fixed Mode
LDO5 in regulation
6
24
V+ = LDO5, VOUT5 < 4.41V
4.5
5.5
V+ = 6V to 24V, FB3 = GND, V SKIP = 5V
3.27
3.39
V
4.95
5.15
V
V+ = 6V to 24V, FB5 = GND, V SKIP = 5V,
MAX8732A/MAX8734A (TON = VCC)
V
V+ = 7V to 24V, FB5 = GND, V SKIP = 5V,
MAX8733A/MAX8734A (TON = GND)
Output Voltage in
Adjustable Mode
V+ = 6V to 24V, either SMPS
1.97
2.03
V
Output Voltage Adjust Range
Either SMPS
2.0
5.5
V
FB3, FB5 Adjustable-Mode
Threshold Voltage
Dual-Mode comparator
0.1
0.2
V
Current-Limit Threshold
(Positive, Default)
ILIM_ = VCC, GND - CS_ (MAX8732A/MAX8733A),
GND - LX_ (MAX8734A)
90
110
mV
GND - CS_
(MAX8732A/MAX8733A),
GND - LX_ (MAX8734A)
40
60
Current-Limit Threshold
(Positive, Adjustable)
VILIM_ = 1V
90
110
VILIM_ = 2V
180
220
On-Time Pulse Width
VILIM_ = 0.5V
mV
MAX8732A or MAX8734A
(VTON = 5V)
VOUT5 = 5.05V
1.895
2.315
VOUT3 = 3.33V
0.833
1.017
MAX8733A or MAX8734A
(VTON = 0)
VOUT5 = 5.05V
0.895
1.209
VOUT3 = 3.33V
0.475
0.635
200
400
ns
Minimum Off-Time
µs
INTERNAL REGULATOR AND REFERENCE
LDO5 Output Voltage
ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO5 < 100mA
4.90
5.10
V
LDO5 Undervoltage-Lockout
Fault Threshold
Falling edge of LDO5, hysteresis = 1%
3.7
4.3
V
_______________________________________________________________________________________
5
MAX8732A/MAX8733A/MAX8734A
ELECTRICAL CHARACTERISTICS (continued)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12.0.V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.69
V
3.2
Ω
LDO5 Bootstrap Switch Threshold
Falling edge of OUT5, rising edge at OUT5 regulation
point
LDO5 Bootstrap Switch
Resistance
LDO5 to OUT5, VOUT5 = 5V
LDO3 Output Voltage
ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO3 < 100mA
3.27
3.43
V
LDO3 Bootstrap Switch Threshold
Falling edge of OUT3, rising edge at OUT3 regulation
point
2.80
3.02
V
LDO3 Bootstrap
Switch Resistance
LDO3 to OUT3, VOUT3 = 3.2V
3.5
Ω
REF Output Voltage
No external load
REF Load Regulation
0 < ILOAD < 50µA
4.43
1.975
2.025
V
10
mV
REF Sink Current
REF in regulation
V+ Operating Supply Current
LDO5 switched over to OUT5, 5V SMPS
10
50
µA
µA
V+ Standby Supply Current
V+ = 6V to 24V, both SMPSs off, includes ISHDN
300
µA
V+ Shutdown Supply Current
V+ = 4.5V to 24V
15
µA
Quiescent Power Consumption
Both SMPSs on, FB3 = FB5 = SKIP = GND, VOUT3 =
3.5V, VOUT5 = 5.3V
4.5
mW
FAULT DETECTION
Overvoltage Trip Threshold
FB3 or FB5 with respect to nominal regulation point
+8
+14
%
PGOOD Threshold
FB3 or FB5 with respect to nominal output, falling edge,
typical hysteresis = 1%
-12
-7
%
PGOOD Output Low Voltage
ISINK = 4mA
PGOOD Leakage Current
High state, forced to 5.5V
Output Undervoltage Shutdown
Threshold
FB3 or FB5 with respect to nominal output voltage
Output Undervoltage Shutdown
Blanking Time
From ON_ signal
0.3
V
1
µA
65
75
%
10
40
ms
-200
+200
nA
INPUTS AND OUTPUTS
Feedback Input Leakage Current
PRO Input Voltage
VFB3 = VFB5 = 2.2V
Low level
High level
0.6
1.5
Low level
SKIP Input Voltage
TON Input Voltage
6
0.8
Float level
1.7
High level
2.4
Low level
High level
V
2.3
0.8
2.4
_______________________________________________________________________________________
V
V
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12.0.V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
Clear fault level/SMPS off level
ON3, ON5 Input Voltage
Input Leakage Current
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
MAX
1.7
SMPS on level
2.4
V PRO or VTON = 0 or 5V
-1
2.3
-1
+1
V SKIP = 0 or 5V
-2
+2
V SHDN = 0 or 24V
-1
+1
-2
+2
VILIM3, VILIM5 = 0 or 2V
-0.2
+0.2
Rising edge
1.2
2.0
Falling edge
0.96
1.04
BST - LX_ forced to 5V
4.0
DL_, high state (pullup)
5.0
DL_, low state (pulldown)
1.5
OUT3, OUT5 Discharge-Mode
On-Resistance
0.2
V
+1
VON_ = 0 or 5V
OUT3, OUT5 Discharge-Mode
Synchronous Rectifier
Turn-On Level
UNITS
0.8
Delay start level
VCS_ = 0 or 5V
SHDN Input Trip Level
TYP
µA
V
Ω
Ω
40
Ω
0.4
V
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
_______________________________________________________________________________________
7
MAX8732A/MAX8733A/MAX8734A
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
MAX8732A
MAX8732A
MAX8732A
5V OUTPUT EFFICIENCY
5V OUTPUT EFFICIENCY
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
vs. LOAD CURRENT
vs. LOAD CURRENT
40
30
PWM MODE
60
50
ULTRASONIC MODE
40
20
VIN = 7V
ON5 = VCC
ON3 = GND
10
1
10
0.01
LOAD CURRENT (A)
MAX8733A
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
90
80
60
ULTRASONIC MODE
50
40
30
20
PWM MODE
10
ON5 = VCC
ON3 = VCC
VIN = 7V
VIN = 12V
VIN = 24V
0.01
0.1
1
PFM MODE
7
10
188
186
184
MAX8732A
182
180
178
176
MAX8733A
174
8.5
19
INPUT VOLTAGE (V)
22
25
MAX8732A/3A/4A toc03
PWM MODE
10
ULTRASONIC MODE
1
PFM MODE
0.1
25
10
7
13
16
19
22
INPUT VOLTAGE (V)
SHUTDOWN INPUT CURRENT
vs. INPUT VOLTAGE
MAX8732A
5V OUTPUT SWITCHING FREQUENCY
vs. LOAD CURRENT MAX8732A
MAX8732A
MAX8733A
7.5
7.0
6.5
6.0
5.0
16
22
8.0
170
13
19
9.0
5.5
10
16
9.5
172
7
13
10.0
SHUTDOWN INPUT CURRENT (µA)
MAX8732A/3A/4A toc07
190
8
100
INPUT VOLTAGE (V)
LOAD CURRENT (A)
STANDBY INPUT CURRENT
vs. INPUT VOLTAGE
10
MAX8733A
NO-LOAD BATTERY CURRENT
vs. INPUT VOLTAGE
1
10
1
MAX8732A
NO-LOAD BATTERY CURRENT
vs. INPUT VOLTAGE
250
225
SWITCHING FREQUENCY (kHz)
0.001
0.1
LOAD CURRENT (A)
0.1
0
0.01
LOAD CURRENT (A)
ULTRASONIC MODE
10
0.001
10
MAX8732A/3A/4A toc08
EFFICIENCY (%)
70
1
PWM MODE
BATTERY CURRENT (mA)
PFM MODE
0.1
100
MAX8732A/3A/4A toc04
100
VIN = 24V
ON5 = VCC
ON3 = GND
0
0.001
BATTERY CURRENT (mA)
0.1
MAX8732A/3A/4A toc05
0.01
ULTRASONIC MODE
40
10
0
0.001
50
20
VIN = 12V
ON5 = VCC
ON3 = GND
10
0
PWM MODE
60
30
30
20
70
MAX8732A/3A/4A toc06
ULTRASONIC MODE
50
70
PFM MODE
80
VIN = 7V
200
175
25
MAX8732A/3A/4A toc09
60
90
EFFICIENCY (%)
PWM MODE
80
EFFICIENCY (%)
EFFICIENCY (%)
80
PFM MODE
90
100
MAX8732A/3A/4A toc02
PFM MODE
90
70
100
MAX8732A/3A/4A toc01
100
STANDBY INPUT CURRENT (µA)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
PWM MODE
150
125
100
75
50
ULTRASONIC MODE
25
7
10
13
16
19
INPUT VOLTAGE (V)
22
25
0
0.001
PFM MODE
0.01
0.1
LOAD CURRENT (A)
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
1
10
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
160
120
ULTRASONIC MODE
40
0.01
0.1
1
500
0.01
0.1
1
0
0.1
PWM MODE
450
10
350
300
250
200
150
0.001
0.01
0.1
1
1
0
0.001
10
450
10
350
PWM MODE
300
250
200
150
100
ULTRASONIC MODE
50
PFM MODE
0.01
VIN = 24V
400
ULTRASONIC MODE
50
PFM MODE
0.01
VIN = 7V
400
100
ULTRASONIC MODE
50
0.1
PFM MODE
0
1
0.001
10
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
MAX8733A
3.3V OUTPUT SWITCHING
FREQUENCY vs. LOAD CURRENT
MAX8732A
OUT5 VOLTAGE REGULATION
vs. LOAD CURRENT
MAX8732A
OUT3 VOLTAGE REGULATION
vs. LOAD CURRENT
350
300
250
200
150
ULTRASONIC
5.17
5.15
5.13
IDLE MODE
5.11
5.09
50
5.07
PFM MODE
0.01
0.1
LOAD CURRENT (A)
1
10
5.05
0.001
ULTRASONIC
3.40
3.39
3.38
IDLE MODE
3.37
3.36
FORCED-PWM
3.35
FORCED-PWM
ULTRASONIC MODE
3.41
10
MAX8732A/3A/4A toc18
PWM MODE
5.19
OUTPUT VOLTAGE (V)
VIN = 24V
OUTPUT VOLTAGE (V)
MAX8732A/3A/4A toc16
550
MAX8732A/3A/4A toc12
PFM MODE
0
SWITCHING FREQUENCY (kHz)
100
550
SWITCHING FREQUENCY (kHz)
MAX8732A/3A/4A toc13
SWITCHING FREQUENCY (kHz)
150
SWITCHING FREQUENCY (kHz)
ULTRASONIC MODE
MAX8733A
5V OUTPUT SWITCHING
FREQUENCY vs. LOAD CURRENT
200
0
0.001
80
MAX8733A
3.3V OUTPUT SWITCHING
FREQUENCY vs. LOAD CURRENT
250
100
120
MAX8733A
5V OUTPUT SWITCHING
FREQUENCY vs. LOAD CURRENT
300
400
160
LOAD CURRENT (A)
PWM MODE
450
200
40
PFM MODE
0.001
10
240
LOAD CURRENT (A)
350
500
ULTRASONIC MODE
PWM MODE
280
LOAD CURRENT (A)
VIN = 7V
0.001
75
50
0
450
400
100
25
PFM MODE
0
0.001
125
MAX8732A/3A/4A toc14
80
150
VIN = 24V
320
MAX8732A/3A/4A toc15
200
PWM MODE
175
360
SWITCHING FREQUENCY (kHz)
240
200
MAX8732A/3A/4A toc11
PWM MODE
VIN = 24V
225
MAX8732A/3A/4A toc17
280
250
SWITCHING FREQUENCY (kHz)
VIN = 7V
320
SWITCHING FREQUENCY (kHz)
MAX8732A/3A/4A toc10
360
3.34
0.01
0.1
LOAD CURRENT (A)
1
10
3.33
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
_______________________________________________________________________________________
9
MAX8732A/MAX8733A/MAX8734A
Typical Operating Characteristics (continued)
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
MAX8732A
MAX8732A
3.3V OUTPUT SWITCHING FREQUENCY
5V OUTPUT SWITCHING
3.3V OUTPUT SWITCHING
vs. LOAD CURRENT (MAX8732A)
FREQUENCY vs. LOAD CURRENT
FREQUENCY vs. LOAD CURRENT
Typical Operating Characteristics (continued)
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
LDO5 REGULATOR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
LDO3 REGULATOR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
4.97
4.96
4.95
2.005
3.346
3.344
3.342
3.340
2.004
2.003
2.002
2.001
2.000
3.338
1.999
3.336
1.998
3.334
1.997
3.332
1.996
3.330
0
10 20 30 40 50 60 70 80 90 100
MAX8732A/3A/4A toc21
3.348
VREF (V)
4.98
REFERENCE VOLTAGE
vs. OUTPUT CURRENT
MAX8732A/3A/4A toc20
4.99
3.350
LDO3 OUTPUT VOLTAGE (V)
MAX8732A/3A/4A toc19
5.00
LDO5 OUTPUT VOLTAGE (V)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
1.995
0
10 20 30 40 50 60 70 80 90 100
-10 0 10 20 30 40 50 60 70 80 90 100
LDO5 OUTPUT CURRENT (mA)
LDO3 OUTPUT CURRENT (mA)
IREF (µA)
REF, LDO3, AND LDO5 POWER-UP
DELAYED-START WAVEFORMS
(ON3 = REF)
DELAYED-START WAVEFORMS
(ON5 = REF)
MAX8732A/3A/4A toc22
10V
LDO5
2V/div
0
MAX8732A/3A/4A toc24
MAX8732A/3A/4A toc23
V+
10V/div
5V
0
LDO3
2V/div
ON5
5V/div
5V
OUT5
2V/div
0
ON3
5V/div
OUT5
2V/div
0
0
REF
1V/div
0
OUT3
2V/div
400µs/div
SOFT-START WAVEFORMS
100µs/div
100µs/div
SHUTDOWN WAVEFORMS
MAX8732A/MAX8734A (TON = VCC)
5V PWM-MODE
LOAD TRANSIENT RESPONSE
MAX8732A/3A/4A toc25
5A
MAX8732A/3A/4A toc26
IL5
5A/div
0
IL3
5A/div
5A
0
3.3V
OUT3
5V/div
0
5V
OUT5
5V/div
0
200µs/div
10
OUT3
2V/div
0
0
0
0
5V
MAX8732A/3A/4A toc27
ON3
5V/div
0
3.3V
0
OUT3
5V/div
5V
OUT5
5V/div
0
5V
SWITCHING
VOUT,
ACCOUPLED
100mV/div
5V
4A
INDUCTOR
CURRENT
2A/div
1A
5V
DL3
5V/div
0
10ms/div
DL5
5V/div
0
20µs/div
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
VOUT,
ACCOUPLED
100mV/div
4A
VOUT,
ACCOUPLED
100mV/div
3.3V
4A
INDUCTOR
CURRENT
2A/div
1A
MAX8732A/3A/4A toc30
MAX8732A/3A/4A toc29
MAX8732A/3A/4A toc28
5V
MAX8733A/MAX8734A (TON = GND)
3.3V PWM-MODE
LOAD TRANSIENT RESPONSE
MAX8732A/MAX8734A (TON = VCC)
3.3V PWM-MODE
LOAD TRANSIENT RESPONSE
MAX8733A/MAX8734A (TON = GND)
5V PWM-MODE
LOAD TRANSIENT RESPONSE
INDUCTOR
CURRENT
2A/div
1A
DL5
5V/div
0
DL3
5V/div
0
DL3
5V/div
10µs/div
MAX8733A
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
60
50
ULTRASONIC
MODE
40
30
20
0
0.001
PWM MODE
0.01
0.1
LOAD CURRENT (A)
ON5 = VCC
ON3 = GND
VIN = 7V
VIN = 12V
VIN = 24V
1
MAX8732A/3A/4A toc32
PFM MODE
90
80
EFFICIENCY (%)
90
10
100
MAX8732A/3A/4A toc31
100
EFFICIENCY (%)
1A
0
MAX8733A
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
70
INDUCTOR
CURRENT
2A/div
20µs/div
10µs/div
80
4A
5V
5V
5V
VOUT,
ACCOUPLED
100mV/div
3.3V
70
PFM MODE
60
50
ULTRASONIC
MODE
40
30
20
10
10
0
0.001
PWM MODE
0.01
0.1
ON5 = VCC
ON3 = VCC
VIN = 7V
VIN = 12V
VIN = 24V
1
10
LOAD CURRENT (A)
______________________________________________________________________________________
11
MAX8732A/MAX8733A/MAX8734A
Typical Operating Characteristics (continued)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
Pin Description
PIN
MAX8732A
MAX8734A
MAX8733A
12
1
—
—
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
NAME
FUNCTION
3.3V SMPS Current-Sense Input. Connect CS3 to a current-sensing resistor from the source
of the synchronous rectifier to GND. The voltage at ILIM3 determines the current-limit
threshold (see the Current-Limit Circuit (ILIM_) section).
N.C.
No Connection. Not internally connected.
Power-Good Output. PGOOD is an open-drain output that is pulled low if either output is
PGOOD
disabled or is more than 10% below its nominal value.
3.3V SMPS Enable Input. The 3.3V SMPS is enabled if ON3 is greater than the SMPS on level
and disabled if ON3 is less than the SMPS off level. If ON3 is connected to REF, the 3.3V
ON3
SMPS starts after the 5V SMPS reaches regulation (delay start). Drive ON3 below the clear
fault level to reset the fault latches.
5V SMPS Enable Input. The 5V SMPS is enabled if ON5 is greater than the SMPS on level and
disabled if ON5 is less than the SMPS off level. If ON5 is connected to REF, the 5V SMPS
ON5
starts after the 3.3V SMPS reaches regulation (delay start). Drive ON5 below the clear fault
level to reset the fault latches.
3.3V SMPS Current-Limit Adjustment. The GND-LX current-limit threshold defaults to 100mV if
ILIM3 is connected to VCC. In adjustable mode, the current-limit threshold is 1/10 the voltage
ILIM3
seen at ILIM3 over a 0.5V to 3V range. The logic threshold for switchover to the 100mV
default value is approximately VCC - 1V. Connect ILIM3 to REF for a fixed 200mV threshold.
Shutdown Control Input. The device enters its 6µA supply current shutdown mode if
V SHDN is less than the SHDN input falling-edge trip level and does not restart until V SHDN is
SHDN greater than the SHDN input rising-edge trip level. Connect SHDN to V+ for automatic
startup. SHDN can be connected to V+ through a resistive voltage-divider to implement a
programmable undervoltage lockout.
3.3V SMPS Feedback Input. Connect FB3 to GND for fixed 3.3V operation. Connect FB3 to a
FB3
resistive voltage-divider from OUT3 to GND to adjust the output from 2V to 5.5V.
2V Reference Output. Bypass to GND with a 0.22µF (min) capacitor. REF can source up to
REF
100µA for external loads. Loading REF degrades FB_ and output accuracy according to the
REF load-regulation error.
5V SMPS Feedback Input. Connect FB5 to GND for fixed 5V operation. Connect FB5 to a
FB5
resistive voltage-divider from OUT5 to GND to adjust the output from 2V to 5.5V.
Overvoltage and Undervoltage Fault Protection Enable/Disable. Connect PRO to VCC to
disable undervoltage, overvoltage protection, and discharge mode (DL = low in shutdown).
PRO
Connect PRO to GND to enable undervoltage and overvoltage protection (see the Fault
Protection section), and output discharge mode.
5V SMPS Current-Limit Adjustment. The GND-LX current-limit threshold defaults to 100mV if
ILIM5 is connected to VCC. In adjustable mode, the current-limit threshold is 1/10 the voltage
ILIM5
seen at ILIM5 over a 0.5V to 3V range. The logic threshold for switchover to the 100mV
default value is approximately VCC - 1V. Connect ILIM5 to REF for a fixed 200mV threshold.
Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping)
SKIP
operation or to VCC for PWM mode (fixed frequency). Connect to REF or leave floating for
ultrasonic mode (pulse skipping, 25kHz min).
CS3
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
PIN
MAX8732A
MAX8734A
MAX8733A
NAME
13
—
CS5
—
13
TON
14
14
BST5
15
15
LX5
16
16
DH5
17
17
VCC
18
18
LDO5
19
19
DL5
20
20
V+
21
21
OUT5
22
22
OUT3
23
24
23
24
GND
DL3
25
25
LDO3
26
26
DH3
27
27
LX3
28
28
BST3
FUNCTION
5V SMPS Current-Sense Input. Connect CS5 to a current-sensing resistor from the source of
the synchronous rectifier to GND. The voltage at ILIM5 determines the current-limit threshold
(see the Current-Limit Circuit (ILIM_) section).
Frequency Select Input. Connect to VCC for 200kHz/300kHz operation and to GND for
400kHz/500kHz operation (5V/3.3V SMPS switching frequencies, respectively).
Boost Flying Capacitor Connection for 5V SMPS. Connect to an external capacitor and diode
according to the typical application circuits (Figure 1 and Figure 2). See the MOSFET Gate
Drivers (DH_, DL_) section.
Inductor Connection for 5V SMPS. LX5 is the internal lower supply rail for the DH5 high-side
gate driver. LX5 is the current-sense input for the 5V SMPS (MAX8734A only).
High-Side MOSFET Floating Gate-Driver Output for 5V SMPS. DH5 swings from LX5 to BST5.
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage with a
series 50Ω resistor. Bypass to GND with a 1µF ceramic capacitor.
5V Linear-Regulator Output. LDO5 is the gate-driver supply for the external MOSFETs. LDO5
can provide a total of 100mA, including MOSFET gate-drive requirements and external loads.
The internal load depends on the choice of MOSFET and switching frequency (see the
Reference and Linear Regulators (REF, LDO5, and LDO3) section). If OUT5 is greater than
the LDO5 bootstrap switch threshold, the LDO5 regulator shuts down and the LDO5 pin
connects to OUT5 through a 1.4Ω switch. Bypass LDO5 with a minimum of 4.7µF. Use an
additional 1µF per 5mA of load.
5V SMPS Synchronous Rectifier Gate-Drive Output. DL5 swings between GND and LDO5.
Power-Supply Input. V+ powers the LDO5/LDO3 linear regulators and is also used for the
Quick-PWM on-time, one-shot circuits. Connect V+ to the battery input and bypass with a
0.1µF capacitor.
5V SMPS Output Voltage-Sense Input. Connect to the 5V SMPS output. OUT5 is an input to
the Quick-PWM on-time, one-shot circuit. It also serves as the 5V feedback input in fixedvoltage mode. If OUT5 is greater than the LDO5 bootstrap-switch threshold, the LDO5 linear
regulator shuts down and LDO5 connects to OUT5 through a 1.4Ω switch.
3.3V SMPS Output Voltage-Sense Input. Connect to the 3.3V SMPS output. OUT3 is an input
to the Quick-PWM on-time, one-shot circuit. It also serves as the 3V feedback input in fixedvoltage mode. If OUT3 is greater than the LDO3 bootstrap-switch threshold, the LDO3 linear
regulator shuts down and LDO3 connects to OUT3 through a 1.5Ω switch.
Analog and Power Ground
3.3V SMPS Synchronous-Rectifier Gate-Drive Output. DL3 swings between GND and LDO5.
3.3V Linear-Regulator Output. LDO3 powers up after REF is in regulation. LDO3 can provide
a total of 100mA to external loads. If OUT3 is greater than the LDO3 bootstrap-switch
threshold, the LDO3 regulator shuts down and the LDO3 pin connects to OUT3 through a
1.5Ω switch. Bypass LDO3 with a minimum of 4.7µF. Use an additional 1µF per 5mA of load.
High-Side MOSFET Floating Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to
BST3.
Inductor Connection for 3.3V SMPS. LX3 is the current-sense input for the 3.3V SMPS
(MAX8734A only).
Boost Flying Capacitor Connection for 3.3V SMPS. Connect to an external capacitor and
diode according to the typical application circuits (Figure 1 and Figure 2). See the MOSFET
Gate Drivers (DH_, DL_) section.
______________________________________________________________________________________
13
MAX8732A/MAX8733A/MAX8734A
Pin Description (continued)
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
Typical Application Circuits
Table 1. Component Suppliers
The typical application circuits (Figures 1 and 2) generate the 5V/5A and 3.3V/5A main supplies in a notebook
computer. The input supply range is 7V to 24V. Table 1
lists component suppliers.
Detailed Description
The MAX8732A/MAX8733A/MAX8734A dual-buck,
BiCMOS, switch-mode power-supply controllers generate logic supply voltages for notebook computers. The
MAX8732A/MAX8733A/MAX8734A are designed primarily for battery-powered applications where high efficiency and low-quiescent supply current are critical.
The MAX8732A is optimized for highest efficiency with a
5V/200kHz SMPS and a 3.3V/300kHz SMPS, while the
MANUFACTURER
PHONE
FAX
Central Semiconductor
516-435-1110
516-435-1824
Dale-Vishay
402-564-3131
402-563-6418
Fairchild
408-721-2181
408-721-1635
International Rectifier
310-322-3331
310-322-3332
NIEC (Nihon)
805-843-7500
847-843-2798
Sanyo
619-661-6835
619-661-1055
Sprague
603-224-1961
603-224-1430
Sumida
847-956-0666
847-956-0702
Taiyo Yuden
408-573-4150
408-573-4159
TDK
847-390-4461
847-390-4405
VIN 7V TO 24V
5V ALWAYS ON
1µF
4.7µF
50Ω
VCC
LDO5
ILIM3
1µF
VCC
0.1µF
10µF
10µF
CMPSH-3A
1/2
D1
BST5
10Ω
N1
FDS6612A
DH5
0.1µF
L5
N3
FDS6612A
DH3
MAX8732A
MAX8733A
0.1µF
LX5
L3
LX3
C5
3.3V
C3
D3
EP10QY03
DL5
N2
IRF7811AV
DL3
CS5
CS3
OUT3
OUT5
RCS5
20mΩ
FB5
N4
IRF7811AV
VCC
FB3
100kΩ
ON
SHDN
OFF
VCC
ON5
REF
ON3
D2
EP10QY03
RCS3
20mΩ
PGOOD
SKIP
FREQUENCY-DEPENDENT COMPONENTS
5V/3.3V SMPS
SWITCHING FREQUENCY
MAX8732A
MAX8733A
200kHz/300kHz
400kHz/500kHz
L3
4.7µH
3.0µH
GND
REF
PRO
LDO3
1MΩ
3.3V ALWAYS ON
L5
7.6µH
5.6µH
C3
470µF
220µF
C5
330µF
150µF
0.22µF
4.7µF
Figure 1. MAX8732A/MAX8733A Typical Application Circuit
14
10µF
BST3
10Ω
5V
1/2
D1
ILIM5
V+
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
MAX8732A/MAX8733A/MAX8734A
VIN 7V TO 24V
5V ALWAYS ON
1µF
50Ω
4.7µF
VCC
LDO5
ILIM3
1µF
VCC
1/2
D1
ILIM5
V+
0.1µF
10µF
BST5
BST3
DH5
DH3
10Ω
MAX8734A
N3
FDS6612A
0.1µF
0.1µF
L5
LX5
L3
LX3
470pF*
C5
10µF
10Ω
N1
FDS6612A
5V
10µF
CMPSH-3A
1/2
D1
TON
D3
EP10QY03
N2
IRF7811AV
DL5
DL3
OUT5
OUT3
FB5
470pF*
SEE
TABLE
N4
IRF7811AV
3.3V
C3
D2
EP10QY03
VCC
FB3
100kΩ
ON
SHDN
OFF
VCC
ON5
REF
ON3
PGOOD
SKIP
GND
REF
PRO
LDO3
1MΩ
3.3V ALWAYS ON
0.22µF
*OPTIONAL CAPACITANCE BETWEEN
LX AND PGND (CLOSE TO THE IC) ONLY
REQUIRED FOR ULTRASONIC MODE
4.7µF
FREQUENCY-DEPENDENT COMPONENTS
5V/3.3V SMPS
SWITCHING FREQUENCY
TON = VCC
TON = GND
200kHz/300kHz
400kHz/500kHz
L3
4.7µH
3.0µH
L5
7.6µH
5.6µH
C3
470µF
220µF
C5
330µF
150µF
Figure 2. MAX8734A Typical Application Circuit
______________________________________________________________________________________
15
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
MAX8733A is optimized for “thin and light” applications with
a 5V/400kHz SMPS and a 3.3V/500kHz SMPS. The
MAX8734A provides a pin-selectable switching frequency,
allowing either 200kHz/300kHz or 400kHz/500kHz operation
of the 5V/3.3V SMPSs, respectively.
Light-load efficiency is enhanced by automatic IdleMode operation, a variable-frequency pulse-skipping
mode that reduces transition and gate-charge losses.
Each step-down, the power-switching circuit consists of
two n-channel MOSFETs, a rectifier, and an LC output filter. The output voltage is the average AC voltage at the
switching node, which is regulated by changing the duty
cycle of the MOSFET switches. The gate-drive signal to
the n-channel, high-side MOSFET must exceed the
battery voltage, and is provided by a flying-capacitor
boost circuit that uses a 100nF capacitor connected
to BST_.
V+
PGOOD
MAX8732A
MAX8733A
MAX8734A
PGOOD3
PGOOD5
TON
(MAX8734 ONLY)
BST3
BST5
DH3
DH5
LX3
3.3V
SMPS PWM
CONTROLLER
LDO5
LX5
5V
SMPS PWM
CONTROLLER
LDO5
DL5
DL3
CS3
(MAX8732A/
MAX8733A)
CS5
(MAX8732A/
MAX8733A)
ILIM5
ILIM3
FB3
FB5
OUT3
OUT5
EN3
LDO3
4.56V
2.91V
EN5
5V
LINEAR
REG
3V
LINEAR
REG
LDO5
VCC
ON3
ON5
POWER-ON SEQUENCE/
CLEAR FAULT LATCH
THERMAL
SHUTDOWN
SHDN
2V
REFERENCE
PRO
REF
GND
Figure 3. Detailed Functional Diagram
16
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
block controls the power-up timing of the main PWMs and
monitors the outputs for undervoltage faults. The
MAX8732A/MAX8733A/MAX8734A include 5V and 3.3V
linear regulators. Bias generator blocks include the 5V
(LDO5) linear regulator, 2V precision reference, and automatic bootstrap switchover circuit.
V+
OUT
TON (MAX8734A)
ON-TIME
COMPUTE
tOFF
Q
TRIG
ONE SHOT
tON
TRIG
Q
R
TO DH_ DRIVER
ONE SHOT
Q
REF
S
ERROR
AMPLIFIER
ILIM_
CURRENT
LIMIT
Σ
TO DL_ DRIVER
CS_ (MAX8732A/8733A)
LX_ (MAX8734A)
ZERO
CROSSING
S
Q
R
SKIP
OUT_
PGOOD
0.9 x VREF
FB_
OV_FAULT
UV_FAULT
FAULT
LATCH
1.1 x VREF
0.15V
PRO
20ms
BLANKING
0.7 x VREF
Figure 4. PWM Controller (One Side Only)
______________________________________________________________________________________
17
MAX8732A/MAX8733A/MAX8734A
Each PWM controller consists of a Dual-Mode feedback
network and multiplexer, a multi-input PWM comparator,
high-side and low-side gate drivers, and logic. The
MAX8732A/MAX8733A/MAX8734A contain fault-protection
circuits that monitor the main PWM outputs for undervoltage and overvoltage conditions. A power-on sequence
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
These internal blocks are not powered directly from the
battery. Instead, the 5V (LDO5) linear regulator steps
down the battery voltage to supply both internal circuitry and the gate drivers. The synchronous-switch gate
drivers are directly powered from LDO5, while the highside switch gate drivers are indirectly powered from
LDO5 through an external diode-capacitor boost circuit. An automatic bootstrap circuit turns off the 5V linear regulator and powers the device from OUT5 when
OUT5 is above 4.56V.
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode type with
voltage feed-forward. The Quick-PWM control architecture relies on the output ripple voltage to provide the
PWM ramp signal; thus, the output filter capacitor’s
ESR acts as a current-feedback resistor. The high-side
switch on-time is determined by a one-shot whose period is inversely proportional to input voltage and directly
proportional to output voltage. Another one-shot sets a
minimum off-time (300ns typ). The on-time, one-shot
triggers when the following conditions are met: the error
comparator is low, the synchronous rectifier current is
below the current-limit threshold, and the minimum offtime one-shot has timed out.
On-Time, One-Shot (tON)
Each PWM core includes a one-shot that sets the highside switch on-time for each controller. Each fast, lowjitter, adjustable one-shot includes circuitry that varies
the on-time in response to battery and output voltage.
The high-side switch on-time is inversely proportional to
the battery voltage as measured by the V+ input, and
proportional to the output voltage. This algorithm results
in a nearly constant switching frequency despite the
lack of a fixed-frequency clock generator. The benefit
of a constant switching frequency is the frequency can
be selected to avoid noise-sensitive frequency regions:
t ON =
K(VOUT + 0.075V )
V+
See Table 2 for approximate K-factors. The constant
0.075V is an approximation to account for the expected
drop across the synchronous-rectifier switch. Switching
frequency increases as a function of load current due
to the increasing drop across the synchronous rectifier,
which causes a faster inductor-current discharge ramp.
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical
Characteristics are influenced by switching delays in
the external high-side power MOSFET. Also, the deadtime effect increases the effective on-time, reducing the
switching frequency. It occurs only in PWM mode (SKIP
= VCC) and during dynamic output voltage transitions
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the
inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DHrising dead time.
For loads above the critical conduction point, the actual
switching frequency is:
f=
VOUT + VDROP1
t ON ( V + + VDROP2 )
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the parasitic voltage drops in the charging
path, including high-side switch, inductor, and PC
board resistances, and tON is the on-time calculated by
the MAX8732A/MAX8733A/MAX8734A.
Automatic Pulse-Skipping Switchover
(Idle Mode)
In Idle Mode (SKIP = GND), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
Table 2. Approximate K-Factor Errors
SMPS
MAX8732A/MAX8734A (tON = VCC), 5V
MAX8732A/MAX8734A (tON = VCC), 3.3V
MAX8733A/MAX8734A (tON = GND), 5V
MAX8733A/MAX8734A (tON = GND), 3.3V
18
SWITCHING FREQUENCY
(kHz)
200
300
400
500
K-FACTOR (µs)
5.0
3.3
2.5
2.0
APPROXIMATE KFACTOR ERROR (%)
±10
±10
±10
±10
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
ILOAD(SKIP) =
K × VOUT _  V + − VOUT _ 


2×L
V+


where K is the on-time scale factor (see the On-Time
One-Shot (tON) section). The load-current level at which
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2
the peak-to-peak ripple current, which is a function of the
inductor value (Figure 5). For example, in the MAX8732A
Typical Application Circuit with VOUT2 = 5V, V+ = 12V,
L = 7.6µH, and K = 5µs, switchover to pulse-skipping
operation occurs at ILOAD = 0.96A or about 1/5 full load.
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-transient response (especially at low input-voltage levels).
DC output accuracy specifications refer to the trip level of
the error comparator. When the inductor is in continuous
conduction, the output voltage has a DC regulation higher
than the trip level by 50% of the ripple. In discontinuous
conduction (SKIP = GND, light load), the output voltage
has a DC regulation higher than the trip level by approximately 1.5% due to slope compensation.
Forced-PWM Mode
The low-noise, forced-PWM (SKIP = VCC) mode disables the zero-crossing comparator, which controls the
∆i
=
V+ - VOUT
L
-IPEAK
INDUCTOR CURRENT
∆t
ILOAD = IPEAK / 2
0 ON-TIME
TIME
low-side switch on-time. Disabling the zero-crossing
detector causes the low-side, gate-drive waveform to
become the complement of the high-side, gate-drive
waveform. The inductor current reverses at light loads
as the PWM loop strives to maintain a duty ratio of
VOUT/V+. The benefit of forced-PWM mode is to keep
the switching frequency fairly constant, but it comes at
a cost: the no-load battery current can be 10mA to
50mA, depending on switching frequency and the
external MOSFETs.
Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response,
providing sink-current capability for dynamic output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback transformer or coupled inductor.
Enhanced Ultrasonic Mode
(25kHz (min) Pulse Skipping)
Leaving SKIP unconnected or connecting SKIP to REF
activates a unique pulse-skipping mode with a minimum switching frequency of 25kHz. This ultrasonic
pulse-skipping mode eliminates audio-frequency modulation that would otherwise be present when a lightly
loaded controller automatically skips pulses. In ultrasonic mode, the controller automatically transitions to
fixed-frequency PWM operation when the load reaches
the same critical conduction point (ILOAD(SKIP)) that
occurs when normally pulse skipping.
An ultrasonic pulse occurs when the controller detects
that no switching has occurred within the last 28µs.
Once triggered, the ultrasonic controller pulls DL high,
turning on the low-side MOSFET to induce a negative
inductor current. After the inductor current reaches the
negative ultrasonic current threshold, the controller
turns off the low-side MOSFET (DL pulled low) and triggers a constant on-time (DH driven high). When the ontime has expired, the controller reenables the low-side
MOSFET until the controller detects that the inductor
current dropped below the zero-crossing threshold.
Starting with a DL pulse greatly reduces the peak output voltage when compared to starting with a DH pulse.
The output voltage at the beginning of the ultrasonic
pulse determines the negative ultrasonic current threshold, resulting in the following equation:
VISONIC = IL RON = ( VREF − VFB ) × 0.58
where VFB > VREF and RON is the on-resistance of the
synchronous rectifier (MAX8734A) or the current-sense
resistor value (MAX8732A/MAX8733A).
Figure 5. Pulse-Skipping/Discontinuous Crossover Point
______________________________________________________________________________________
19
MAX8732A/MAX8733A/MAX8734A
tinuous and discontinuous inductor-current operation
(also known as the critical conduction point):
Reference and Linear Regulators
(REF, LDO5, and LDO3)
The 2V reference (REF) is accurate to ±1% over temperature, making REF useful as a precision system
reference. Bypass REF to GND with a 0.22µF (min)
capacitor. REF can supply up to 100µA for external
loads. However, if extremely accurate specifications for
both the main output voltages and REF are essential,
avoid loading REF. Loading REF reduces the LDO5,
LDO3, OUT5, and OUT3 output voltages slightly
because of the reference load-regulation error.
Two internal regulators produce 5V (LDO5) and 3.3V
(LDO3). LDO5 provides gate drive for the external
MOSFETs and powers the PWM controller, logic, reference, and other blocks within the device. The LDO5
regulator supplies a total of 100mA for internal and
external loads, including MOSFET gate drive, which
typically varies from 10mA to 50mA, depending on
switching frequency and the external MOSFETs. LDO3
powers up when the reference (REF) is in regulation,
and supplies up to 100mA for external loads. Bypass
LDO5 and LDO3 with a minimum 4.7µF load; use an
additional 1µF per 5mA of internal and external load.
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold, an internal 1.4Ω p-channel MOSFET switch connects OUT5 to LDO5 while simultaneously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above the
LDO3 bootstrap-switchover threshold, an internal 1.5Ω
p-channel MOSFET switch connects OUT3 to LDO3 while
simultaneously shutting down the LDO3 linear regulator.
These actions bootstrap the device, powering the internal
circuitry and external loads from the output SMPS voltages, rather than through linear regulators from the bat-
40µs (MAX)
tery. Bootstrapping reduces power dissipation due to
gate charge and quiescent losses by providing power
from a 90%-efficient switch-mode source, rather than
from a much-less-efficient linear regulator.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-sensing algorithm. The MAX8734A uses the on-resistance of
the synchronous rectifier, while the MAX8732A/
MAX8733A use a discrete resistor in series with the
source of the synchronous rectifier as a current-sensing
element. If the magnitude of the current-sense signal at
CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) is above
the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 7). The actual peak current is
greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are a function of the current-limit threshold, inductor
value, and input and output voltage.
For the MAX8732A/MAX8733A, connect CS_ to the
junction of the synchronous rectifier source and a current-sense resistor to GND. With a current-limit threshold
of 100mV, the accuracy is approximately ±7%. Using a
lower current-sense threshold results in less accuracy.
The current-sense resistor only dissipates power when
the synchronous rectifier is on.
For lower power dissipation, the MAX8734A uses the
on-resistance of the synchronous rectifier as the current-sense element. Use the worst-case maximum
value for RDS(ON) from the MOSFET data sheet, and
add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional
resistance for each °C of temperature rise. The current
limit varies with the on-resistance of the synchronous
rectifier. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the
INDUCTOR
CURRENT
-IPEAK
ILOAD
ZERO-CROSSING
DETECTION
0
INDUCTOR CURRENT
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
ILIMIT
ISONIC
ON-TIME (tON)
0
TIME
Figure 7. “Valley” Current-Limit Threshold Point
Figure 6. Ultrasonic Current Waveforms
20
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
A negative current limit prevents excessive reverse
inductor currents when VOUT sinks current. The negative current-limit threshold is set to approximately 120%
of the positive current limit and therefore tracks the
positive current limit when ILIM_ is adjusted.
The current-limit threshold is adjusted with an external
voltage-divider at ILIM_. The current-limit threshold
adjustment range is from 50mV to 300mV. In the
adjustable mode, the current-limit threshold voltage is
precisely 1/10th the voltage at ILIM_. The threshold
defaults to 100mV when ILIM_ is connected to VCC.
V+
MAX8732A
MAX8733A
MOSFET Gate Drivers (DH_, DL_)
DH_
LX_
OUT_
DL_
CS_
Figure 8. Current Sensing Using Sense Resistor
(MAX8732A/MAX8733A)
V+
MAX8732A
MAX8733A
The logic threshold for switchover to the 100mV default
value is approximately VCC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signals at CS_. Mount or place the device
close to the synchronous rectifier or sense resistor
(whichever is used) with short, direct traces, making a
Kelvin-sense connection to the sense resistor. The current-sense accuracy of Figure 8 is degraded if the
Schottky diode conducts during the synchronous rectifier on-time. To ensure that all current passes through
the sense resistor, connect the Schottky diode in parallel with only the synchronous rectifier (Figure 9) if the
voltage drop across the synchronous rectifier and
sense resistor exceeds the Schottky diode’s forward
voltage. Note that at high temperatures, the on-resistance of the synchronous rectifier increases and the
forward voltage of the Schottky diode decreases.
The DH_ and DL_ gate drivers sink 2.0A and 3.3A,
respectively, of gate drive, ensuring robust gate drive for
high-current applications. The DH_ floating high-side
MOSFET drivers are powered by diode-capacitor charge
pumps at BST_. The DL_ synchronous-rectifier drivers are
powered by LDO5.
The internal pulldown transistors that drive DL_ low
have a 0.6Ω typical on-resistance. These low on-resistance pulldown transistors prevent DL_ from being
pulled up during the fast rise time of the inductor nodes
due to capacitive coupling from the drain to the gate of
the low-side synchronous-rectifier MOSFETs. However,
for high-current applications, some combinations of
high- and low-side MOSFETS may cause excessive
gate-drain coupling, which leads to poor efficiency and
EMI-producing shoot-through currents. Adding a resistor in series with BST_ increases the turn-on time of the
DH_
LX_
5V
VIN
OUT_
BST
10Ω
DL_
DH
CS_
LX
MAX8732A
MAX8733A
MAX8734A
Figure 9. More Accurate Current Sensing with Adjusted
Schottky Connection
Figure 10. Reducing the Switching-Node Rise Time
______________________________________________________________________________________
21
MAX8732A/MAX8733A/MAX8734A
undervoltage-protection circuit, this current-limit
method is effective in almost every circumstance.
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
high-side MOSFETs at the expense of efficiency, without
degrading the turn-off time (Figure 10).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. This algorithm allows operation without
shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be
low-resistance, low-inductance paths from the gate drivers to the MOSFET gates for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry
interprets the MOSFET gate as “off” when there is actually charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50 mils to 100 mils wide if
the MOSFET is 1in from the device).
POR, UVLO, and Internal Digital
Soft-Start
Power-on reset (POR) occurs when V+ rises above
approximately 2.4V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. LDO5
undervoltage-lockout (UVLO) circuitry inhibits switching
when LDO5 is below 4V (typ). DL_ is low if PRO is disabled; DL_ is high if PRO is enabled. The output voltages begin to ramp up once VCC exceeds its 3.25V
(typ) UVLO threshold and REF is in regulation. The
internal digital soft-start timer begins to ramp up the
maximum-allowed current limit during startup. The
1.7ms ramp occurs in five steps: 20%, 40%, 60%, 80%,
and 100%.
When LD05 falls below its 4V (typ) UVLO threshold,
DH_ and DL_ are immediately forced low, and the outputs are high impedance. REF is turned off when VCC
falls below 3.25V (typ). DL_ is forced high again when
VCC falls below its 1V (typ) POR threshold.
Power-Good Output (PGOOD)
The PGOOD comparator continuously monitors both output voltages for undervoltage conditions. PGOOD is
actively held low in shutdown, standby, and soft-start.
PGOOD releases and digital soft-start terminates when
both outputs reach the error-comparator threshold.
PGOOD goes low if EITHER output turns off or is 10%
below its nominal regulation point. PGOOD is a true
open-drain output. Note that PGOOD is independent of
the state of PRO.
Fault Protection
The MAX8732A/MAX8733A/MAX8734A provide
over/undervoltage fault protection. Drive PRO low to
activate fault protection. Drive PRO high to disable fault
protection. Once activated, the devices continuously
monitor for both undervoltage and overvoltage conditions.
22
Overvoltage Protection
When the output voltage is 11% above the set voltage,
the overvoltage fault protection activates. The synchronous rectifier turns on 100% and the high-side MOSFET
turns off. This rapidly discharges the output capacitors,
decreasing the output voltage. The output voltage may
dip below ground. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the
output to act as a reverse-polarity clamp. In practical
applications, there is a fuse between the power source
(battery) and the external high-side switches. If the
overvoltage condition is caused by a short in the highside switch, turning the synchronous rectifier on 100%
creates an electrical short between the battery and
GND, blowing the fuse and disconnecting the battery
from the output. Once an overvoltage fault condition is
set, it can only be reset by toggling SHDN, ON_, or
cycling V+ (POR).
Undervoltage Protection
When the output voltage is 30% below the set voltage for
over 22ms (undervoltage shutdown blanking time), the
undervoltage fault protection activates. Both SMPSs stop
switching. The two outputs start to discharge (see the
Discharge Mode (Soft-Stop) section). When the output
voltage drops to 0.3V, the synchronous rectifiers turn on,
clamping the outputs to GND. Toggle SHDN or ON_, or
cycle V+ (POR) to clear the undervoltage fault latch.
Thermal Protection
The MAX8732A/MAX8733A/MAX8734A have thermal
shutdown to protect the devices from overheating.
Thermal shutdown occurs when the die temperature
exceeds +160°C. All internal circuitry shuts down during
thermal shutdown. The MAX8732A/MAX8733A/
MAX8734A may trigger thermal shutdown if LDO_ is not
bootstrapped from OUT_ while applying a high input
voltage on V+ and drawing the maximum current
(including short circuit) from LDO_. Even if LDO_ is bootstrapped from OUT_, overloading the LDO_ causes
large power dissipation on the bootstrap switches, which
may result in thermal shutdown. Cycling SHDN, ON3,
ON5, or a V+ (POR) ends the thermal-shutdown state.
Discharge Mode (Soft-Stop)
When PRO is low and a transition to standby or shutdown mode occurs, or the output undervoltage fault
latch is set, the outputs discharge to GND through an
internal 12Ω switch, until the output voltages decrease
to 0.3V. The reference remains active to provide an
accurate threshold and to provide overvoltage protection. When both SMPS outputs discharge to 0.3V, the
DL_ synchronous rectifier drivers are forced high. The
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
MODE
CONDITION
COMMENT
LDO5 < UVLO threshold
Transitions to discharge mode after a V+ POR and after REF becomes valid.
LDO5, LDO3, and REF remain active. DL_ is active if PRO is low.
SHDN = high, ON3 or ON5
enabled
Normal operation.
Overvoltage
Protection
Either output > 111% of
nominal level, PRO = low
DL_ is forced high. LDO3, LDO5 active. Exited by a V+ POR or by toggling
SHDN, ON3, or ON5.
Undervoltage
Protection
Either output < 70% of
nominal after 22ms timeout expires and output is
enabled, PRO = low
If PRO is low, DL_ is forced high after discharge mode terminates. LDO3,
LDO5 active. Exited by a V+ POR or by toggling SHDN, ON3, or ON5.
PRO is low and either
SMPS output is still high in
either standby mode or
shutdown mode
Discharge switch (12Ω) connects OUT_ to PGND. One output may still run
while the other is in discharge mode. Activates when LDO_ is in UVLO, or
transition to UVLO, standby, or shutdown has begun. LDO3, LDO5 active.
ON5, ON3 < startup
threshold, SHDN = high
DL_ stays high if PRO is low. LDO3, LDO5 active.
Shutdown
SHDN = low
All circuitry off.
Thermal Shutdown
TJ > +160°C
All circuitry off. Exited by V+ POR or cycling SHDN, ON3, or ON5.
Power-Up
Run
Discharge
Standby
synchronous rectifier drivers clamp the SMPS outputs
to GND. When PRO is high, the SMPS outputs do not
discharge and the DL_ synchronous rectifier drivers
remain low.
Shutdown Mode
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX8732A/MAX8733A/MAX8734A
in their low-power shutdown state. The MAX8732A/
MAX8733A/MAX8734A consume only 6µA of quiescent
current while in shutdown mode. When shutdown mode
activates, the reference turns off, making the threshold
to exit shutdown inaccurate. To guarantee startup,
drive SHDN above 2V (SHDN input rising-edge trip
level). For automatic shutdown and startup, connect
SHDN to V+. If PRO is low, both SMPS outputs are discharged to 0.3V through a 12Ω switch before entering
true shutdown. The accurate 1V falling-edge threshold
on SHDN can be used to detect a specific analog voltage level and shut down the device. Once in shutdown,
the 1.6V rising-edge threshold activates, providing sufficient hysteresis for most applications. For additional
hysteresis, the undervoltage threshold can be made
dependent on REF or LDO_, which go to 0V in shutdown.
Table 4. Power-Up Sequencing
SHDN
(V)
VON3
(V)
VON5
(V)
LDO5
LDO3
5V SMPS
3V SMPS
Low
X
X
Off
Off
Off
Off
Off
“> 2.4” => High
Low
Low
On
On (after REF powers up)
Off
“> 2.4” => High
High
High
On
On (after REF powers up)
On
On
“> 2.4” => High
High
Low
On
On (after REF powers up)
Off
On
“> 2.4” => High
Low
High
On
On (after REF powers up)
On
Off
“> 2.4” => High
High
REF
On
On (after REF powers up)
On (after 3V SMPS is up)
On
“> 2.4” => High
REF
High
On
On (after REF powers up)
On
On (after 5V SMPS is up)
______________________________________________________________________________________
23
MAX8732A/MAX8733A/MAX8734A
Table 3. Operating-Mode Truth Table
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
Power-Up Sequencing and
On/Off Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs.
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation and
starts after that output regulates. The second SMPS
remains on until the first SMPS turns off, the device shuts
down, a fault occurs, or LDO5 goes into undervoltage
lockout. Both supplies begin their power-down sequence
immediately when the first supply turns off. Driving ON_
below 0.8V clears the overvoltage, undervoltage, and
thermal fault latches.
Adjustable-Output Feedback
(Dual-Mode FB)
Connect FB_ to GND to enable the fixed, preset SMPS
output voltages (3.3V and 5V). Connect a resistive voltage-divider at FB_ between OUT_ and GND to adjust
the respective output voltage between 2V and 5.5V
(Figure 11). Choose R2 to be approximately 10kΩ, and
solve for R1 using the equation:
V

OUT _
R1 = R2 × 
− 1
 V

 FB

where VFB = 2V nominal.
V+
DH_
VOUT_
MAX8732A
MAX8733A
MAX8734A
DL_
GND
R1
OUT_
FB_
R2
Figure 11. Setting VOUT_ with a Resistor-Divider
24
When using the adjustable-output mode, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to OUT5
through an internal switch only when OUT5 is above the
LDO5 bootstrap-switch threshold (4.56V). LDO3 connects to OUT3 through an internal switch only when
OUT3 is above the LDO3 bootstrap switch threshold
(2.91V). Bootstrapping is most effective when the fixed
output voltages are used. Once LDO_ is bootstrapped
from OUT_, the internal linear regulator turns off. This
reduces internal power dissipation and improves efficiency when LDO_ is powered with a high input voltage.
Design Procedure
Establish the input voltage range and maximum load
current before choosing an inductor and its associated
ripple-current ratio (LIR). The following four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value (V+(MAX))
must accommodate the maximum AC adapter voltage. The minimum value (V+(MIN)) must account for
the lowest input voltage after drops due to connectors, fuses, and battery selector switches. Lower input
voltages result in better efficiency.
2) Maximum Load Current. The peak load current
(ILOAD(MAX)) determines the instantaneous component stress and filtering requirements, and thus drives output capacitor selection, inductor saturation
rating, and the design of the current-limit circuit.
The continuous load current (ILOAD) determines the
thermal stress and drives the selection of input
capacitors, MOSFETs, and other critical heat-contributing components.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage and MOSFET switching losses. The
MAX8732A has a nominal switching frequency of
200kHz for the 5V SMPS and 300kHz for the 3.3V
SMPS. The MAX8733A has a nominal switching frequency of 400kHz for the 5V SMPS and 500kHz for
the 3.3V SMPS. The MAX8734A has a pin-selectable switching frequency.
4) Inductor Ripple Current Ratio (LIR). LIR is the
ratio of the peak-to-peak ripple current to the average inductor current. Size and efficiency trade-offs
must be considered when setting the inductor ripple current ratio. Low inductor values cause large
ripple currents, resulting in the smallest size, but
poor efficiency and high output noise. The minimum
practical inductor value is one that causes the circuit to operate at critical conduction (where the
inductor current just touches zero with every cycle
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
The MAX8732A/MAX8733A/MAX8734As’ pulse-skipping algorithm (SKIP = GND) initiates skip mode at the
critical conduction point, so the inductor’s operating
point also determines the load current at which
PWM/PFM switchover occurs. The optimum point is
usually found between 20% and 50% ripple current.
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as follows:
L =
(
VOUT_ V + − VOUT_
)
V + × f × LIR × ILOAD(MAX)
Example: ILOAD(MAX) = 5A, V+ = 12V, VOUT5 = 5V, f =
200kHz, 35% ripple current or LIR = 0.35:
L=
(
5V 12V − 5V
)
12V × 200kHz × 0.35 × 5A
= 8.3µH
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice. The core must be large enough
not to saturate at the peak inductor current (IPEAK):
IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)]
The inductor ripple current also impacts transientresponse performance, especially at low V+ - VOUT_
differences. Low inductor values allow the inductor current to slew faster, replenishing charge removed from
the output filter capacitors by a sudden load step. The
peak amplitude of the output transient (VSAG) is also a
function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
VSAG =
(∆ILOAD(MAX) )
2
 V

OUT _
× L K
+ t OFF(MIN) 


V+


  V+− V


OUT _
− t OFF(MIN) 
2 × COUT × VOUT _ K


 

V+



where minimum off-time = 0.350µs (max) and K is from
Table 2.
Determining the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
ILIMIT(LOW) > ILOAD(MAX) - [(LIR / 2) x ILOAD(MAX)]
where ILIMIT(LOW) = minimum current-limit threshold
voltage divided by the RDS(ON) of N2/N4 (MAX8734A).
For the MAX8732A/MAX8733A/MAX8734A, the minimum current-limit threshold voltage is 93mV (ILIM_ =
VCC). Use the worst-case maximum value for RDS(ON)
from the MOSFET N2/N4 data sheet and add some
margin for the rise in RDS(ON) with temperature. A good
general rule is to allow 0.5% additional resistance for
each °C of temperature rise.
Examining the 5A circuit example with a maximum
RDS(ON) = 12mΩ at high temperature reveals the following:
ILIMIT(LOW) = 93mV / 12mΩ > 5A - (0.35 / 2) 5A
7.75A > 4.125A
7.75A is greater than the valley current of 4.125A, so
the circuit can easily deliver the full-rated 5A using the
fixed 100mV nominal current-limit threshold voltage.
Connect the source of the synchronous rectifier to a
current-sense resistor to GND (MAX8732A/MAX8733A),
and connect CS_ to that junction to set the current limit
for the device. The MAX8732A/MAX8733A/MAX8734A
limit the current with the sense resistor instead of the
RDS(ON) of N2/N4. The maximum value of the sense
resistor can be calculated with the equation:
ILIM_ = 93mV / RSENSE
Output-Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. The output capacitance must also be high enough to absorb the inductor
energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault latch. In
applications where the output is subject to large load
transients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag
due to finite capacitance:
RESR ≤
VDIP
ILOAD(MAX)
where VDIP is the maximum-tolerable transient voltage
drop. In non-CPU applications, the output capacitor’s
size depends on how much ESR is needed to maintain
an acceptable level of output voltage ripple:
______________________________________________________________________________________
25
MAX8732A/MAX8733A/MAX8734A
at maximum load).Inductor values lower than this
grant no further size-reduction benefit.
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
RESR ≤
VP−P
LIR × ILOAD(MAX)
where VP-P is the peak-to-peak output voltage ripple.
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalum, OS-CON, and other electrolytic-type capacitors).
When using low-capacity filter capacitors such as
polymer types, capacitor size is usually determined by
the capacity required to prevent VSAG and VSOAR from
tripping the undervoltage and overvoltage fault latches
during load transients in ultrasonic mode.
For low input-to-output voltage differentials (VIN / VOUT
< 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode.
The amount of overshoot due to stored inductor energy
can be calculated as:
VSOAR =
IPEAK 2 L
2COUT VOUT _
where IPEAK is the peak inductor current.
Stability Considerations
Stability is determined by the value of the ESR zero
(fESR) relative to the switching frequency (f). The point
of instability is given by the following equation:
f
fESR ≤
π
where:
Input-Capacitor Selection
fESR =
1
2π RESR COUT
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Low-ESR capacitors (especially polymer or tantalum),
in widespread use at the time of publication, typically
have ESR zero frequencies lower than 30kHz. In the
design example used for inductor selection, the ESR
needed to support a specified ripple voltage is found
by the equation:
ESR =
26
where LIR is the inductor ripple current ratio and ILOAD
is the average DC load. Using LIR = 0.35 and an average load current of 5A, the ESR needed to support
50mVP-P ripple is 28mΩ.
Do not place high-value ceramic capacitors directly
across the fast-feedback inputs (OUT_ to GND for internal feedback, FB_ divider point for external feedback)
without taking precautions to ensure stability. Large
ceramic capacitors can have a high-ESR zero frequency
and cause erratic, unstable operation. Adding a discrete
resistor or placing the capacitors a couple of inches
downstream from the junction of the inductor and OUT_
may improve stability.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feedback loop instability. Noise on the output or insufficient
ESR may cause double pulsing. Insufficient ESR does
not allow the amplitude of the voltage ramp in the output
signal to be large enough. The error comparator mistakenly triggers a new cycle immediately after the 350ns
minimum off-time period has expired. Double pulsing
results in increased output ripple, and can indicate the
presence of loop instability caused by insufficient ESR.
Loop instability results in oscillations or ringing at the
output after line or load perturbations, causing the output voltage to fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX8734A EV kit data sheet) and observe the output
voltage-ripple envelope for overshoot and ringing.
Monitoring the inductor current with an AC current
probe can also provide some insight. Do not allow
more than one cycle of ringing of under- or overshoot
after the initial step response.
The input capacitors must meet the input-ripple-current
(IRMS) requirement imposed by the switching current.
The MAX8732A/MAX8733A/MAX8734A dual switching
regulators operate at different frequencies. This interleaves the current pulses drawn by the two switches and
reduces the overlap time where they add together. The
input RMS current is much smaller in comparison than
with both SMPSs operating in phase. The input RMS current varies with load and the input voltage.
VRIPPLE(P−P)
LIR × ILOAD
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
(

 VOUT _ V + − VOUT _
IRMS ≈ ILOAD 
V+


) 



When V+ = 2 x VOUT_(D = 50%), IRMS has a maximum
current of ILOAD / 2.
The ESR of the input capacitor is important for determining capacitor power dissipation. All the power
(IRMS2 x ESR) heats up the capacitor and reduces efficiency. Nontantalum chemistries (ceramic or OS-CON)
are preferred due to their low ESR and resilience to
power-up surge currents. Choose input capacitors that
exhibit less than +10°C temperature rise at the RMS
input current for optimal circuit longevity. Place the
drains of the high-side switches close to each other to
share common input bypass capacitors.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(> 5A) when using high-voltage (> 20V) AC adapters.
Low-current applications usually require less attention.
Choose a high-side MOSFET (N1/N3) that has conduction losses equal to the switching losses at the typical
battery voltage for maximum efficiency. Ensure that the
conduction losses at the minimum input voltage do not
exceed the package thermal limits or violate the overall
thermal budget. Ensure that conduction losses plus
switching losses at the maximum input voltage do not
exceed the package ratings or violate the overall thermal budget.
Choose a synchronous rectifier (N2/N4) with the lowest
possible RDS(ON). Ensure the gate is not pulled up by the
high-side switch turning on due to parasitic drain-to-gate
capacitance, causing crossconduction problems.
Switching losses are not an issue for the synchronous
rectifier in the buck topology since it is a zero-voltage
switched device when using the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to the MOSFET’s RDS(ON)
occurs at the minimum battery voltage:

 V
2
OUT _
 ILOAD RDS(ON)
PD (NH Re sis tan ce) = 
 VIN(MIN) 


(
)
Generally, a small high-side MOSFET reduces switching losses at high input voltage. However, the RDS(ON)
required to stay within package power-dissipation limits
often limits how small the MOSFET can be. The optimum situation occurs when the switching (AC) losses
equal the conduction (RDS(ON)) losses.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum battery voltage is applied, due to the squared term in the CV2 ✕ f
switching-loss equation. Reconsider the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages if it becomes extraordinarily hot when subjected to V+(MAX).
Calculating the power dissipation in NH (N1/N3) due to
switching losses is difficult since it must allow for quantifying factors that influence the turn-on and turn-off
times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for bench evaluation, preferably including verification using a thermocouple mounted on NH (N1/N3):
PD(NH Switching) =
COSS (VIN(MAX) )2 fSW
2
+
VIN(MAX)ILOADQG(SW)fSW
IGATE
where COSS is the output capacitance of NH (N1/N3),
QG(SW) is the switch gate charge of NH, and IGATE is
the peak gate-drive source/sink current.
For the synchronous rectifier, the worst-case power dissipation always occurs at maximum battery voltage:

VOUT _ 
2
PD (NL ) = 1−
 ILOAD RDS(ON)
V
IN(MAX) 

The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
ILOAD(MAX) but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to
tolerate:
ILOAD = ILIMIT(HIGH) + (LIR / 2 ) x ILOAD(MAX)
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and resistance variation.
______________________________________________________________________________________
27
MAX8732A/MAX8733A/MAX8734A
The maximum input capacitor RMS current for a single
SMPS is given by:
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
Rectifier Selection
Current circulates from ground to the junction of both
MOSFETs and the inductor when the high-side switch is
off. As a consequence, the polarity of the switching
node is negative with respect to ground. This voltage is
approximately -0.7V (a diode drop) at both transition
edges while both switches are off (dead time). The drop
is IL x RDS(ON) when the low-side switch conducts.
The rectifier is a clamp across the synchronous rectifier
that catches the negative inductor swing during the dead
time between turning the high-side MOSFET off and the
synchronous rectifier on. The MOSFETs incorporate a
high-speed silicon body diode as an adequate clamp
diode if efficiency is not of primary importance. Place a
Schottky diode in parallel with the body diode to reduce
the forward-voltage drop and prevent the N2/N4 MOSFET
body diodes from turning on during the dead time.
Typically, the external diode improves the efficiency by
1% to 2%. Use a Schottky diode with a DC current rating
equal to 1/3 of the load current. For example, use an
MBR0530 (500mA-rated) type for loads up to 1.5A, a
1N5819 type for loads up to 3A, or a 1N5822 type for
loads up to 10A. The rectifier’s rated reverse-breakdown
voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor.
Boost Supply Diode
A signal diode, such as a 1N4148, works well in most
applications. Use a small (20mA) Schottky diode for
slightly improved efficiency and dropout characteristics, if the input voltage can go below 6V. Do not use
large power diodes, such as 1N5817 or 1N4001, since
high-junction capacitance can force LDO5 to excessive
voltages.
Applications Information
(∆IUP). The ratio h = ∆IUP/∆IDOWN indicates the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current is less able to increase during each
switching cycle and VSAG greatly increases unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this can
be adjusted up or down to allow tradeoffs between
V SAG , output capacitance, and minimum operating
voltage. For a given value of h, the minimum operating
voltage can be calculated as:
V + (MIN) =
(VOUT _ + VDROP1)

t
OFF (MIN) × h

1− 


K


+ VDROP2 − VDROP1
where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths (see the OnTime, One-Shot section), tOFF(MIN) is from the EC table,
and K is taken from Table 2. The absolute minimum
input voltage is calculated with h = 1.
Operating frequency must be reduced or h must be
increased and output capacitance added to obtain an
acceptable VSAG if calculated V+(MIN) is greater than
the required minimum input voltage. Calculate VSAG to
be sure of adequate transient response if operation
near dropout is anticipated.
Dropout Design Example
MAX8733A: With VOUT5 = 5V, fsw = 400kHz, K = 2.25µs,
tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and h = 1.5,
Dropout Performance
The output voltage-adjust range for continuous-conduction operation is restricted by the nonadjustable 350ns
(max) minimum off-time, one-shot. Use the slower 5V
SMPS for the higher of the two output voltages for best
dropout performance in adjustable feedback mode. The
duty-factor limit must be calculated using worst-case values for on- and off-times, when working with low input
voltages. Manufacturing tolerances and internal propagation delays introduce an error to the tON K-factor. Also,
keep in mind that transient-response performance of
buck regulators operated close to dropout is poor, and
bulk output capacitance must often be added (see the
VSAG equation in the Output-Capacitor Selection section).
The absolute point of dropout occurs when the inductor
current ramps down during the minimum off-time
(∆IDOWN) as much as it ramps up during the on-time
28
MAX1658/
MAX1659
V+
LDO
DH_
MAX8732A
MAX8733A
MAX8734A
DL_
T1
10µH
1:2.2
T1 = TRANSPOWER TECHNOLOGIES TTI-5870
Figure 12. Transformer-Coupled Secondary Output
______________________________________________________________________________________
12V
POSITIVE
SECONDARY
OUTPUT
5V
MAIN
OUTPUT
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
V + (MIN) =
(5V + 0.1V)
LPRIMARY =
 0.35µs × 1.5 
1− 

2.25µs 

+ 0.1V − 0.1V = 6.65V
Calculating with h = 1 yields:
V + (MIN) =
(5V + 0.1V)
 0.35µs × 1
1− 

 2.25µs 
+ 0.1V − 0.1V = 6.04 V
Therefore, V+ must be greater than 6.65V. A practical
input voltage with reasonable output capacitance
would be 7.5V.
Use of Coupled Inductors to Create
Auxiliary Outputs
A coupled inductor or transformer can be substituted for
the inductor in the 5V or 3.3V SMPS to create an auxiliary
output (Figure 12). The MAX8732A/MAX8733A/
MAX8734A are particularly well suited for such applications because they can be configured in ultrasonic or
forced-PWM mode to ensure good load regulation when
the main supplies are lightly loaded. An additional
postregulation circuit can be used to improve load regulation and limit output current.
The power requirements of the auxiliary supply must be
considered in the design of the main output. The transformer must be designed to deliver the required current
in both the primary and the secondary outputs with the
proper turns ratio and inductance. The power ratings of
the synchronous-rectifier MOSFETs and the current limit
in the MAX8732A/MAX8733A/MAX8734A must also be
adjusted accordingly. Extremes of low input-output differentials, widely different output loading levels, and high
turns ratios can further complicate the design due to parasitic transformer parameters such as interwinding
capacitance, secondary resistance, and leakage inductance. Power from the main and secondary outputs is
combined to get an equivalent current referred to the
main output. Use this total current to determine the current limit (see the Determining the Current Limit section):
I TOTAL = PTOTAL / VOUT
where ITOTAL is the equivalent output current referred
to the main output and PTOTAL is the sum of the output
power from both the main output and the secondary
output:
N=
VOUT (VIN(MAX) − VOUT
VIN(MAX) × ƒ × I TOTAL × LIR
VSEC + VFWD
VOUT(MIN) + VRECT
where LPRIMARY is the primary inductance, N is the
transformer turns ratio, VSEC is the minimum-required
rectified secondary voltage, VFWD is the forward drop
across the secondary rectifier, VOUT(MIN) is the minimum
value of the main output voltage, and VRECT is the onstate voltage drop across the synchronous rectifier
MOSFET. The transformer secondary return is often connected to the main output voltage instead of ground to
reduce the necessary turns ratio. In this case, subtract
VOUT from the secondary voltage (VSEC - VOUT) in the
transformer turns-ratio equation above.
The secondary diode in coupled-inductor applications
must withstand flyback voltages greater than 60V, which
usually rules out most Schottky rectifiers. Common silicon rectifiers, such as the 1N4001, are also prohibited
because they are too slow. This often makes fast silicon
rectifiers such as the MURS120 the only choice. The flyback voltage across the rectifier is related to the VIN VOUT difference, according to the transformer turns ratio:
VFLYBACK = VSEC + (VIN - VOUT) ✕ N
where N is the transformer turns ratio (secondary windings/primary windings), VSEC is the maximum secondary
DC output voltage, and VOUT is the primary (main) output voltage. If the secondary winding is returned to VOUT
instead of ground, subtract VOUT from VFLYBACK in the
equation above. The diode’s reverse breakdown voltage
rating must also accommodate any ringing due to leakage inductance. The diode’s current rating should be at
least twice the DC load current on the secondary output.
The optional linear postregulator must be selected to
deliver the required load current from the transformer’s
rectified DC output. The linear regulator should be configured to run close to dropout to minimize power dissipation and should have good output accuracy under
those conditions. Input and output capacitors are chosen to meet line regulation, stability, and transient
requirements. There is a wide variety of linear regulators
appropriate for this application; consult the specific linear-regulator data sheet for details.
Widely different output loads affect load regulation. In
particular, when the secondary output is left unloaded
while the main output is fully loaded, the secondary output capacitor may become overcharged by the leakage
inductance, reaching voltages much higher than intended. In this case, a minimum load or overvoltage protec-
______________________________________________________________________________________
29
MAX8732A/MAX8733A/MAX8734A
the minimum V+ is:
USE PGND PLANE TO:
USE AGND PLANE TO:
- BYPASS LDO_
- BYPASS VCC AND REF
- TERMINATE EXTERNAL FB
- CONNECT PGND TO THE TOPSIDE STAR GROUND
DIVIDER (IF USED)
OUT5
VIA BETWEEN POWER
- TERMINATE RILIM
AND ANALOG GROUND
(IF USED)
AGND
VIA TO OUT5
- PIN-STRAP CONTROL
INPUTS
PGND
L1
C3
C4
VIA TO OUT3
C1
N4
C2
N3
VIAS TO GROUND
VIA TO LX5
OUT3
N2
D2
ANALOG GROUND
PLANE ON INNER LAYER
VIA TO PGND
GROUND
D1
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
L2
N1
V+
VIA TO LX3
CONNECT PGND TO AGND
BENEATH THE CONTROLLER AT NOTE: EXAMPLE SHOWN IS FOR DUAL I.C. n-CHANNEL MOSFET.
ONE POINT ONLY AS SHOWN.
Figure 13. PC Board Layout Example
tion may be required on the secondary output to protect
any device connected to this output.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal
switching losses and clean, stable operation. This is
especially true when multiple converters are on the
same PC board where one circuit can affect the other.
The switching power stages require particular attention
(Figure 13). Refer to the MAX1999 EV kit I.C. data sheet
for a specific layout example.
Mount all of the power components on the top side of
the board with their ground terminals flush against one
another, if possible. Follow these guidelines for good
PC board layout:
• Isolate the power components on the top side from
the sensitive analog components on the bottom side
with a ground shield. Use a separate PGND plane
under the OUT3 and OUT5 sides (called PGND3 and
PGND5). Avoid the introduction of AC currents into
the PGND3 and PGND5 ground planes. Run the
power plane ground currents on the top side only, if
possible.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT3 and OUT5.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
30
full-load efficiency by 1% or more. Correctly routing
PC board traces must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable efficiency penalty.
• CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) and
GND connections to the synchronous rectifiers for
current limiting must be made using Kelvin-sense
connections to guarantee the current-limit accuracy.
With 8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
copper layer, while connecting CS_/LX_ traces inside
(underneath) the MOSFETs.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example, it
is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the synchronous rectifier or between the inductor and the
output filter capacitor.
• Ensure that the OUT_ connection to COUT_ is short and
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the
OUT_ connector node and the output filter capacitor
(see the Stability Considerations section).
• Route high-speed switching nodes (BST_, DH_, LX_,
and DL_) away from sensitive analog areas (REF,
ILIM_, and FB_). Use PGND3 and PGND5 as an EMI
shield to keep radiated switching noise away from the
IC’s feedback divider and analog bypass capacitors.
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
very close to the device. Connect the AGND and
PGND planes together at the GND pin of the device.
Layout Procedure
5) On the board’s top side (power planes), make a
star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection
of the input capacitors and synchronous rectifiers.
Keep the resistance low between the star ground
and the source of the synchronous rectifiers for
accurate current limit. Connect the top-side star
ground (used for MOSFET, input, and output
capacitors) to the small island with a single short,
wide connection (preferably just a via).
1) Place the power components first with ground terminals adjacent (N2/N4 source, CIN_, COUT_, D1
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronousrectifier MOSFETs, preferably on the back side to
keep DH_, GND, and the DL_ gate drive lines short
and wide. The DL_ gate trace must be short and
wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1in from the controller device.
3) Group the gate-drive components (BST_ diode and
capacitor, V+ bypass capacitor) together near the
controller device.
4) Make the DC-DC controller ground connections as
follows: near the device, create a small analog
ground plane. Connect the small analog ground
plane to GND (Figure 13) and use the plane for the
ground connection for the REF and VCC bypass
capacitors, FB dividers, and ILIM resistors (if any).
Create another small ground island for PGND, and
use the plane for the V+ bypass capacitor, placed
Create PGND islands on the layer just below the
top-side layer (refer to the MAX1999 EV kit for an
example) to act as an EMI shield if multiple layers
are available (highly recommended). Connect each
of these individually to the star ground via, which
connects the top side to the PGND plane. Add one
more solid ground plane under the device to act as
an additional shield, and also connect the solid
ground plane to the star ground via.
6) Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor
positive and negative terminals with multiple vias.
Table 5. MAX8732A/MAX8733A/MAX8734A and MAX1777/MAX1977/MAX1999 Differences
MAX8732A/MAX8733A/MAX8734A
MAX1777/MAX1977/MAX1999
Line Transient Behavior
Improved line transient behavior requires only
a 0.1µF filter capacitor on V+. Allows fast
rising-edge line transients of 10V/µs and
falling-edge line transients of 5V/µs.
A 4Ω/4.7µF filter capacitor is required on V+ to
limit the dV/dt on the V+ pin.
Ultrasonic Mode
Simplified Z pattern offers better efficiency
and smoother transition into continuousconduction mode.
Original “W” pattern conducts through the highside MOSFET’s body diode, reducing efficiency.
Transition between ultrasonic mode and
continuous-conduction mode is not as smooth.
LDO3 and LDO5 Sequencing
LDO3 starts only after LDO5 is in regulation,
reducing the inrush current when SHDN goes
high.
LDO3 and LDO5 start up together at the current
limit of each LDO, causing large inrush currents
through the 4Ω series resistor at V+.
Soft-Shutdown Enable Delay
Soft-shutdown (10Ω discharge feature) is
enabled immediately when an output is
enabled, and is not dependent on the 22ms
(typ) startup undervoltage blanking timer.
Soft-shutdown (10Ω discharge feature) is
enabled only after the 22ms (typ) startup
undervoltage blanking time. This causes DL_ to
be driven high if the part is commanded to turn
off before the 22ms timer.
High-Output Impedance in UVLO
When LDO5 falls below its 4V (typ) UVLO
threshold, DH_ and DL_ are immediately
pulled low, and the outputs are high
impedance. The outputs are discharged by
the load.
When LDO5 falls below its 4V (typ) UVLO
threshold, DH_ is immediately pulled low and
DL_ forced high to clamp the output rails. This
causes the outputs to swing below ground.
______________________________________________________________________________________
31
MAX8732A/MAX8733A/MAX8734A
• Make all pin-strap control input connections (SKIP,
ILIM_, etc.) to GND or VCC of the device.
MAX8732A/MAX8733A/MAX8734A
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
Ordering Information (continued)
PART
PINTEMP RANGE
PACKAGE
MAX8734AEEI+ -40°C to +85°C 28 QSOP
MAX8734AEEI
-40°C to +85°C 28 QSOP
+Denotes lead free package.
5V/3V
SWITCHING
FREQUENCY
(kHz)
200/300 or
400/500
400kHz/500
Pin Configurations (continued)
TOP VIEW
CS3 1
28 BST3
PGOOD 2
27 LX3
ON3 3
26 DH3
ON5 4
25 LDO3
ILIM3 5
SHDN 6
24 DL3
MAX8732A
MAX8733A
23 GND
FB3 7
22 OUT3
REF 8
21 OUT5
FB5 9
20 V+
PRO 10
19 DL5
ILIM5 11
18 LDO5
SKIP 12
17 VCC
CS5 13
16 DH5
BST5 14
15 LX5
QSOP
Chip Information
TRANSISTOR COUNT: 8335
PROCESS: BiCMOS
32
______________________________________________________________________________________
High-Efficiency, Quad-Output, Main PowerSupply Controllers for Notebook Computers
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX8732A/MAX8733A/MAX8734A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)