PEREGRINE 3335-01

Product Specification
PE3335
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Product Description
Peregrine’s PE3335 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3335 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
The PE3335 features a 10/11 dual modulus prescaler,
counters, phase comparator and a charge pump as shown
in Figure 1. Counter values are programmable through
either a serial or parallel interface and can also be directly
hard wired.
The PE3335 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
Features
• 3000 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with
charge pump
• Serial, parallel or hardwired
programmable
• Ultra-low phase noise
• Available in 44-lead PLCC and
7x7 mm 48-lead QFN packages
Figure 1. Block Diagram
Fin
Fin
Prescaler
10/11
Main
Counter
fp
13
D(7:0)
8
Sdata
Pre_en
M(6:0)
A(3:0)
R(3:0)
Primary
20-bit
20
Latch
Secondary
20-bit
Latch
20
20
fr
Document No. 70-0049-02 │ www.psemi.com
Phase
Detector
20
16
6
PD_U
PD_D
Charge
Pump
CP
6
R Counter
fc
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3335
Product Specification
GND
GND
GND
fr
LD
Enh
VDD
R0
R1
R2
R3
1
GND
VDD
2
GND
R0
3
GND
R1
4
fr
R2
5
LD
R3
6
Enh
GND
Figure 2. Pin Configurations (Top View)
48 47 46 45 44 43 42 41 40 39 38 37
44 43 42 41 40
D 0, M0
7
39
D 1, M1
8
D 2, M2
9
fc
D0, M0
1
36
fc
38
VDD_f c
D1, M1
2
35
V DD_fc
37
NC
D2, M2
3
34
NC
D3, M3
4
33
NC
V DD
5
32
CP
V DD
6
D 3, M3
10
36
CP
V DD
11
35
VDD
31
GND
V DD
12
34
Cext
S_W R, D4, M4
7
30
VDD
S_W R, D 4, M4
13
33
VDD
Sdata, D5, M5
8
29
Cext
Sclk, D6, M6
9
28
VDD
FSELS, D7, Pre_en
10
27
Dout
GND
11
26
VDD_fp
FSELP, A0
12
25
fp
Sdata, D 5, M5
14
32
Dout
Sclk, D 6, M6
15
31
VDD_f p
FSELS, D7, Pre_en
16
30
fp
GND
17
29
GND
18 19 20 21 22 23 24 25 26 27 28
13 14 15 16 17 18 19 20 21 22 23 24
GND
Fin
Fin
Hop_WR
A_WR
M1_WR
V DD
V DD
Bmode
Smode, A3
M2_WR, A2
E_WR, A1
Fin
Fin
Hop_WR
A_WR
M1_WR
V DD
Bmode
Smode, A3
M2_WR, A 2
E_WR, A1
FSELP, A0
44-lead PLCC
48-lead QFN
Table 1. Pin Descriptions
Pin No.
Pin No.
(44-lead
PLCC)
(48-lead
QFN)
1
43
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
2
44
R0
Direct
Input
R Counter bit0 (LSB).
3
45
R1
Direct
Input
R Counter bit1.
4
46
R2
Direct
Input
R Counter bit2.
5
47
R3
Direct
Input
R Counter bit3.
6
48
GND
ALL
(Note 1)
Ground.
D0
Parallel
Input
Parallel data bus bit0 (LSB).
7
1
M0
Direct
Input
M Counter bit0 (LSB).
D1
Parallel
Input
Parallel data bus bit1.
M1
Direct
Input
M Counter bit1.
D2
Parallel
Input
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
D3
Parallel
Input
Parallel data bus bit3.
M3
Direct
Input
M Counter bit3.
8
9
10
Pin
Name
Interface
Mode
Type
Description
2
3
4
11
5
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
12
6
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
(44-lead
PLCC)
(48-lead
QFN)
13
14
15
16
17
18
Pin
Name
Interface
Mode
Type
S_WR
Serial
Input
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
M5
Direct
Input
M Counter bit5.
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
M6
Direct
Input
M Counter bit6.
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en
Direct
Input
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
GND
ALL
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A0
Direct
Input
A Counter bit0 (LSB).
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register
on the rising edge of E_WR.
A1
Direct
Input
A Counter bit1.
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
A2
Direct
Input
A Counter bit2.
Smode
Serial,
Parallel
Input
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface
Mode (Bmode=0, Smode=0).
A3
Direct
Input
A Counter bit3 (MSB).
Bmode
ALL
Input
Selects direct interface mode (Bmode=1).
VDD
ALL
(Note 1)
Same as pin 1 (MLP48 pin 43).
7
8
9
10
11
Ground.
12
E_WR
19
20
21
Description
13
14
15
22
16
23
17,18
24
19
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the
rising edge of M1_WR.
25
20
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
26
21
Hop_WR
Serial,
Parallel
Input
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
27
22
Fin
ALL
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
(44-lead
PLCC)
(48-lead
QFN)
28
23
Fin
ALL
29
24
GND
ALL
30
25
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
26
VDD-fp
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
32
27
Dout
Serial,
Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
33
28
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
34
29
Cext
ALL
Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
35
30
VDD
ALL
(Note 1)
Same as pin 1 (QFN48 pin 43).
36
32
CP
ALL
Output
Charge pump current is sourced when fc leads fp and sinked when fc lags fp.
37
33, 34
NC
ALL
38
35
VDD-fc
ALL
(Note 1)
VDD for fc can be left floating or connected to GND to disable the fc output.
39
36
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding VDD
pin 38.
40
31,37
GND
ALL
Ground.
41
38,39
GND
ALL
Ground.
42
40
fr
ALL
Input
Reference frequency input.
43
41
LD
ALL
Output
Lock detect and open drain logical inversion of Cext. When the loop is in lock,
LD is high impedance, otherwise LD is a logic low (“0”).
44
42
Enh
Serial,
Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Note 1:
Pin
Name
Interface
Mode
Type
Input
Description
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50 Ω resistor
directly to the ground plane.
Ground.
No connection.
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fc are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
Table 4. ESD Ratings
Parameter/Conditions
Min
Max
Units
Symbol
Supply voltage
-0.3
4.0
V
VESD
VI
Voltage on any input
-0.3
VDD +
0.3
V
II
DC into any input
-10
+10
mA
IO
DC into any output
-10
+10
mA
Electrostatic Discharge (ESD) Precautions
Storage temperature range
-65
150
°C
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
VDD
Tstg
Note 1:
Table 3. Operating Ratings
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Supply voltage
2.85
3.15
V
TA
Operating ambient
temperature range
-40
85
°C
Parameter/Conditions
ESD voltage (Human Body
Level
Units
1000
V
Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
IDD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
Conditions
Min
Digital Inputs: All except fr, R0, Fin, Fin
VIH
High level input voltage
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
High level input current
Low level input current
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
-1
Reference Divider input: fr
IIHR
High level input current
IILR
Low level input current
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
-100
R0 Input (Pull-up Resistor): R0
IIHRO
High level input current
IILRO
Low level input current
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
-5
Counter output Dout
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
IIH
IIL
Units
10
24
31
mA
mA
0.3 x VDD
V
V
+70
µA
µA
+100
µA
µA
+5
µA
µA
0.4
V
V
0.4
0.4
V
V
V
-1.4
2.6
mA
mA
15
µA
%
15
%
VDD - 0.4
Iout = 100 mA
Iout = -100 mA
Iout = 6 mA
ICP - Source
ICP – Sink
ICPL
ICP – Source
vs. ICP Sink
Drive current
Drive current
Leakage current
Sink vs. source mismatch
VCP = VDD / 2
VCP = VDD / 2
1.0 V < VCP < VDD – 1.0 V
VCP = VDD / 2,
TA = 25° C
Output current magnitude variation vs. voltage
V < VCP < VDD – 1.0 V
TA = 25° C
Document No. 70-0049-02 │ www.psemi.com
Max
0.7 x VDD
Lock detect outputs: Cext, LD
VOLC
Output voltage LOW, Cext
VOHC
Output voltage HIGH, Cext
VOLLD
Output voltage LOW, LD
Charge Pump output: CP
ICP vs. VCP
Typ
VDD = 2.85 to 3.15 V
VDD - 0.4
-2.6
1.4
-1
-2
2
1
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
PE3335
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
10
MHz
Control Interface and Latches (see Figures 3, 4, 5)
fClk
Serial data clock frequency
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tDSU
Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
10
ns
10
ns
30
ns
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
Sclk falling edge to E_WR transition
30
ns
30
ns
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
E_WR transition to Sclk rising edge
30
ns
30
ns
tDHLD
tPW
tCWR
tCE
tWRC
tEC
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8
ns
500
3000
MHz
-5
5
dBm
50
300
MHz
-5
5
dBm
(Note 2)
100
MHz
10
dBm
Main Divider (Including Prescaler)
Fin
Operating frequency
PFin
Input level range
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
PFin
Input level range
External AC coupling
Operating frequency
(Note 1)
Pfr
Reference input power
Single ended input
-2
Vfr
Input sensitivity
External AC coupling
0.5
Reference Divider
fr
VP-P
(Note 3)
Phase Detector
fc
Note 1:
Note 2:
Note 3:
Comparison frequency
(Note 1)
20
MHz
Parameter is guaranteed through characterization only and is not tested.
Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a lownoise amplifier to square up the edges is recommended at lower input frequencies.
CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 15
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Functional Description
The PE3335 consists of a prescaler, counters, a
phase detector, a charge pump and control logic.
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and “M”
divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in
the modulus select logic. The phase-frequency
detector generates up and down frequency control
signals. The control logic includes a selectable
chip interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 3. Functional Block Diagram
R Counter
(6-bit)
fr
D(7:0)
Sdata
Control
Pins
Control
Logic
fc
PD_U
R(5:0)
Phase
Detector
M(8:0)
PD_D
Charge
Pump
CP
A(3:0)
LD
Cext
2 kΩ
Modulus
Select
Fin
Fin
10/11
Prescaler
Document No. 70-0049-02 │ www.psemi.com
M Counter
(9-bit)
fp
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 15
PE3335
Product Specification
Main Counter Chain
Register Programming
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
Parallel Interface Mode
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
where A ≤ M + 1, 1 ≤ M ≤ 511
(1)
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
where A ≤ M + 1, 1 ≤ M ≤ 511
(2)
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
When the prescaler is bypassed, the equation
becomes:
Fin = (M + 1) x (fr / (R+1))
where 1 ≤ M ≤ 511
(3)
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
(4)
Note that programming R equal to “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”).
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 15
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three, 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 10. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 4. Data are
transferred to the counters as shown in Table 7
on page 10.
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 4. This data provides control bits as
shown in Table 8 on page 10 with bit
functionality enabled by asserting the Enh input
“low”.
Serial Interface Mode
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low.
fc = fr / (R + 1)
where 0 ≤ R ≤ 63
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR or Hop_WR
according to the timing diagram shown in
Figures 4-5. Data are transferred to the counters
as shown in Table 7 on page 10.
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
While the E_WR input is “high” and the S_WR
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Direct Interface Mode
input is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
functionality enabled by asserting the Enh input
“low”.
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
Table 7. Primary Register Programming
Interface
Mode
Enh
Bmode
Smode
Parallel
1
0
0
R5
R4
M8
M7
Pre_en
M6
M2_WR rising edge load
D3
D2
D1
D0
M5
M4
M3
M2
M1
M0
R3
R2
M1_WR rising edge load
D7
D6
D5
D4
D3
R1
R0
A3
A2
A1
A0
A_WR rising edge load
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
1
0
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
Direct
1
1
X
0
0
0
0
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Bmode
Smode
Parallel
0
X
0
Serial*
0
X
1
Reserved
Reserved
Reserved
D7
D6
D5
B0
B1
B2
Power
down
Counter
load
E_WR rising edge load
D4
D3
B3
B4
MSEL
output
Prescaler
output
fc, fp OE
D2
D1
D0
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
Document No. 70-0049-02 │ www.psemi.com
(last in) LSB
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 15
PE3335
Product Specification
Figure 4. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
D [7 : 0]
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
E_WR
tPW
Hop_WR
Figure 5. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 15
tClkH
tClkL
tCWR
tPW
tWRC
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0
Reserved**
Bit 1
Reserved**
Description
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the Bmode and
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Bit 7
fp, fc OE
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “low”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc.
The signals from the phase detector couple
directly to a charge pump. PD_U controls a
current source at pin CP with constant amplitude
and pulse duration approximately the same as
PD_U. PD_D similarly drives a current sink at pin
Document No. 70-0049-02 │ www.psemi.com
CP. The current pulses from pin CP are low pass
filtered externally and then connected to the VCO
tune voltage. PD_U pulses result in a current
source, which increases the VCO frequency;
PD_D pulses result in a current sink, which
decreases VCO frequency (for a positive Kv
VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
PE3335
Product Specification
Handling Requirements
All surface mount products which do not meet
Level 1 moisture sensitivity requirements are
processed through dry bake and pack procedure.
The necessary data is recorded on the caution
label of each shipment. Both packages for the
PE3335 are moisture sensitivity Level 3.
Level 3 Caution Label
The caution label should contain the following
information for Level 3 devices:
1. Calculated shelf life in sealed bag: 12 months
at <40 °C and <90% relative humidity (RH)
2. Peak package body temperature is 225 °C.
3. After bag is opened, devices that will be
subjected to reflow solder or other high
temperature process must
Level and Body temperature defined by:
IPC/JEDEC-J-STD-020
For Dry Bake Procedures, see:
IPC/JEDEC-J-STD-033
Operator must observe ESD precautions per
ESD Control Procedure and Parts Handling and
shipping Procedure.
a) Be mounted within 168 hours of factory
conditions <30 °C/60% RH, or
b) Be stored at <10% RH
4. Devices require bake, before mounting, if:
a) Humidity Indicator Card is > 10% when
read at 23 ± 5 °C
b) 3a or 3b are not met
5. If baking is required, devices may be baked for
48 hours at 125 +5/-0 °C
Note: If device containers cannot be subjected to
high temperature or shorter bake times are
desired, reference IPC/JEDEC-J-STD-033 for
bake procedure.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 15
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Figure 6. Package Drawing
48-lead QFN
7.00
-B-
3.50
7.00
3.50
INDEX AREA
3.50 X 3.50
0.25 C
0.80
-A-
0.10 C
2
0.08 C
SEATING
-CPLANE
0.30
0.50
5.00
5.25
2.50
2.63
13
24
25
5.00
5.25
0.23
7.00
5.50 TYP
0.23
2.50
2.63
2.75 TYP
12
0.18
0.20 REF
0.020
EXPOSED PAD &
TERMINAL PADS
0.18
1 48
36
37
EXPOSED PAD
DETAIL
A
2
0.50 TYP
0.23
0.10
C A B
1
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.
2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
AS THE TERMINALS.
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 15
PE3335
Product Specification
Figure 7. Package Drawing
44-lead PLCC
0.690±0.005
0.653±0.003
0.045 X 45°
0.010 X 45°
1*
0.020 MIN.
R0.025
0.653±0.003
PIN 1
SURFACE
MOUNT
POINT
0.050
0.690±0.005
4*
0.610 ±0.020
2*
0.050
3*
BOTTOM VIEW
DETAIL
AA
0.027 (WIDTH OF LEAD SLOT)
*EJECT PIN POSITION
Ø0.040
DIMENSIONS ARE IN INCHES
TOLERANCES ARE ± 0.004
50X 45°
0.070
0.180 MAX.
0.070
0.004
0.010
SEE DETAIL A
Table 10. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
3335-21
PE3335
PE3335-44PLCC-27A
44-lead PLCC
27 units / Tube
3335-22
PE3335
PE3335-44PLCC-500C
44-lead PLCC
500 units / T&R
3335-23
PE3335
PE3335-48QFN 7x7 mm-52A
48-lead QFN
52 units / Tube
3335-24
PE3335
PE3335-48QFN 7x7 mm-2000C
48-lead QFN
2000 units / T&R
3335-00
PE3335EK
PE3335-44PLCC-EVAL KIT
Evaluation Kit
1 / Box
3335-01
PE3335EK
PE3335-48QFN 7x7 mm-EK
Evaluation Kit
1 / Box
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 14 of 15
Document No. 70-0049-02 │ UltraCMOS™ RFIC Solutions
PE3335
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
Fax 858-731-9499
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
Peregrine Semiconductor Europe
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si,
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Fax: +82-31-728-4305
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Americas:
Tel: 505-881-0438
Fax: 505-881-0443
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
Document No. 70-0049-02 │ www.psemi.com
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 15