E2A0046-16-X1 ¡ Semiconductor ¡ Semiconductor This version: Jan. 1998 MSM7557 Previous version: Nov. 1996 MSM7557 Single Chip MSK Modem with Compandor for Cordless Telephone GENERAL DESCRIPTION The MSM7557 is a single chip MSK modem with base band voice processor for cordless telephone. The MSM7557 voice transmit block consists of high pass filter, compressor, pre-emphasis, limiter and splatter filter. Voice receive block consists of Band pass filter, De-emphasis and Expander. FEATURES • Available to transmit modem signal and also transmit base band voice signal through wireless transmission path (0.3 kHz to 3.4 kHz) • Built-in compandor circuit • Upper limit of voice band (3306 Hz/3400 Hz/3500 Hz) is selectable • Modem bit rate (2400/1200 bps) is selectable • Transmit function and receive function operate separately • Emphasis mode selectable • Built-in bit synchronous detector and frame synchronous detector • Built-in limiter level generator and external limit voltage input • Dynamic range selectable • Built-in crystal oscillator circuit • Wide range power supply voltage (2.7V ~ 5.5V) • Package : 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7557GS-2K) 1/25 LIM CMPI CC1 CC2 CC3N CC3P – + Compressor SD ST BR HPF1 PreEmphasis Splatter Filter Limiter MOD VR1 VR2 VR3 TAO CONT SEC DYN TVE ME EMP RCK1 RCK2 RCLPF BYP DEMOD VDD GND SG Flame Det SG Mix LPF X1 X2 RCLPF Mixer DEMBPF ¡ Semiconductor TVI BLOCK DIAGRAM TVIO RD RT FD FPS BIT FDE Shaper CSH RCLPF RVO OSC Voltage REF HPF2 Expander CE3P PDN DeEmphasis CE3N PDN RBPF + RAI CE1 CE2 – RAIO RVE MSM7557 2/25 ¡ Semiconductor MSM7557 43 NC 44 FPS 45 FD 46 RD 47 RT 48 RVE 49 VDD 50 PDN 51 NC 52 X1 53 X2 54 ME 55 TVE 56 SD PIN CONFIGURATION (TOP VIEW) VR3 8 35 SEC NC 9 34 CSH TVIO 10 33 RAI CMPI 11 32 NC TVI 12 31 RAIO CC1 13 30 CE3P CC2 14 29 NC 28 RCK1 NC 36 27 7 CE3N VR2 26 RCK2 CE2 37 25 6 CE1 VR1 24 BYP RVO 38 23 5 TAO NC 22 BR GND 39 21 4 (VDD) LIM 20 FDE NC 40 19 3 SG EMP 18 BIT DYN 41 17 2 CC3P ST 16 NC CC3N 42 15 1 NC NC Notes: The pin 49 should be used for VDD. The pin 21 should be connected to VDD or opened. NC : No connect pin 3/25 ¡ Semiconductor MSM7557 PIN DESCRIPTION Description Name Transmit data input. The data on SD pin are took into MSK modulator and the data are available on the positive edge of ST. ME SD input t MS SD ST Modulator input data In order to synchronize a receive modem, more than 18bits bit-synchronous signal should be transmitted before data transmission. If S/N ratio of the receive signal is always good, more than 11bits bit-synchronous signal synchronizes the receiver. ST Transmit data timing clock output. When digital "0" is put on ME pin, ST is fixed to digital "1" level. Emphasis path selection. EMP EMP 0 1 Transmit side Receive side Pre-emphasis circuit is bypassed to the De-emphasis circuit is bypassed to the path path Pre-emphasis circuit is connected to the De-emphasis circuit is connected to the path path Deviation limiter control. Voice signal maximum Rf modulation level is controlled by connecting external reference voltage to this pin. Input impedance of this pin is about 200 kW. When this pin is left open, internal reference voltage is used as the clamp level. LIM Internal clamp level is as follows. DYN Internal clamp level Limiter level 0 0.50 V –9 dBV 1 1.26 V –1 dBV This internal clamp level is made by internal reference voltage which is unrelated with VDD. Negative clamp level is made by internal operational amplifier and the voltage is reversed at VSG. 4/25 ¡ Semiconductor MSM7557 (Continued) Name Description Modulator output level control. Refer to the following figure. – + From modulator R1 ≥ 40 kW R2 ≥ 40 kW R1 ≥ R2 VR1 R1 VR1 VR2 VR2 – + To transmit filter VR3 R2 VR3 VTAO = 20 ¥ log (R2/R1) – 9 dBV (DYN = "0" ) VTAO = 20 ¥ log (R2/R1) – 1 dBV (DYN = "1" ) This level is made from internal voltage reference, so this level doesn't depend on power supply voltage. Transmit side RC active filter input (TVI) and output (TVIO). If over 50 kHz frequency element is in the input signal, folding noise is generated from internal SCF circuit, so second order RC-active filter is needed. (fc = 10 kHz) CMPI Compressor C19 C1 R3 R5 TVIO R5 ≥ 60 kW C1 and C19 are used for DC cut. C3 TVIO TVI TVI R4 C2 – + VTVI SG Example of fc = 10 kHz and 0 dB gain R3 = R4 = R5 = 68 kW C1 = 0.22 mF, C2 = 510 pF, C3 = 110 pF When digital "1" is applied to TVE pin, transmit voice signal comes out to TAO. CC1 Capacitor connection pins to remove for DC offset of the compressor. CC2 A 1 mF capacitor between SG pin and each pin should be connected. CC3N CC3P Capacitor connection pins for the compressor attack and recovery time. When DYN is digital "0" level, a 0.22 mF capacitor should be connected between CC3N and CC3P. And when DYN is digital "1" level, a 0.47 mF capacitor should be connected between them. 5/25 ¡ Semiconductor MSM7557 (Continued) Name CMPI Description Compressor circuit input. A 0.47 mF capacitor should be connected between CMPI and TVIO. Dynamic range control input. For an application of which VDD is always higher than 4.5 V (Base station), by setting DYN = "1", modem transmit carrier level, typical input signal level, limiter clamp level and compandor DYN standard input level are up about 8dB to improve S/N ratio. For an application of which VDD is lower than 4.5 V (Hand-set) DYN shall be digital "0". To make easier interface with the RF part, one solution is to put digital "0" on DYN pin for both Base station and Handset. Built-in analog signal ground. The DC voltage is half of VDD. SG To make this voltage source impedance lower and to ensure the device performance, it is necessary to put a bypass capacitor of more than 1mF between SG and VDD in close physical proximity to the device. GND Ground pin, (0V). Transmit analog signal output. According to control data on ME and TVE, TAO is set as follows. ME TAO TVE TAO 0 0 No signal output (potential = SG) 0 1 Voice signal output 1 X MSK modulator output X : Don't care Receive voice signal output. RVO pin state is defined by RVE control. RVO RVE RVO 0 Output disable (potential = SG) 1 Output enable CE1 Capacitor connection pins to remove DC offset of the expander. CE2 A 1 mF capacitor between SG pin and each pin should be connected. Capacitor connection pins for the expander attack time and recovery time. CE3N CE3P RAIO RAI CSH When DYN is digital "0" level, a 0.22 mF capacitor should be connected between CE3N and CE3P. And when DYN is digital "1" level, a 0.47 mF capacitor should be connected between them. Receive side amplifier input (RAI) and output (RAIO). Second order RC-active filter is needed like TVIO and TVI. Refer to TVIO and TVI pin description. Capacitor connection pin to remove DC offset of the modem shaper circuit. A 1 mF capacitor should be connected between GND pin and CSH. 6/25 ¡ Semiconductor MSM7557 (Continued) Name SEC Function Device test input. SEC shall be connected to GND. Voice band select. RCK1 RCK2 RCK1 RCK2 Upper Limit of Voice Band 0 1 3306 Hz X 0 3400 Hz 1 1 3500 Hz Compandor path selection. BYP BYP Transmit side Receive side 0 Compressor is connected to the path. Expander is connected to the path. 1 Compressor is bypassed to the path. Expander is bypassed to the path. Modem data signaling rate select pin. BR BR Date signaling rate 0 1200 bps 1 2400 bps 7/25 ¡ Semiconductor MSM7557 (Continued) Name Function Frame synchronous signal detector control. When digital "0" is applied to this pin, FD pin is fixed to "0" level. RT and RD always work. FDE When digital "1" is applied to this pin, frame synchronous detector works, and RT and RD pins are fixed to "1" level untill synchronous signal detector detects frame synchronous signal and FD becomes "1" level. Refer to Fig.3 (receive signal timing). Bit synchronous signal detector control. When BIT and FDE pins are digital "1" level and when bit synchronous signal and frame synchronous BIT signal are detected continously, FD becomes digital "1". When BIT pin is digital "0" level and FDE pin is digital "1" level and when 16-bit frame synchronous signal is detected, FD pin becomes digital "1" level. Refer to FPS pin detection. Frame synchronous pattern control. FPS BIT FPS Detect pattern Receiver 0 0 1001 0011 0011 0110 (=9336H) Handset side 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 (=C4D6H) Base station 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 (=A9336H) Handset side 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 (=AC4D6H) Base station (Note : This pattern is for Japanese Cordless Telephone.) Frame synchronous detector output. FD When receive data correspond to detection pattern, FD pin is held to digital "1" level. When FDE is applied to digital "0" level, FD pin is reset to digital "0" level. And at the full power down state (PDN = "1", RVE = "0" ), FD pin is reset to digital "0" level. Demodulator serial data output. RD The data are synchronized with the re-generated timing clock of RT. When FDE is digital "1" level and also FD is digital "0" level, RD is fixed to digital "1" level. Receive data timing clock output. This signal is re-generated by internal digital PLL. The falling edge of this clock output is coincident RT with the transitions of RD. The rising edge of RT can be used to latch the valid receive data. When FDE pin is applied to digital "1" level and also FD pin output digital "0" level, RT pin is fixed to digital "1" level. Refer to Fig.3. RVE Receive voice signal control. Refer to RVO pin description. Power supply. VDD This device is sensitive to power supply noises as switched capacitor tequniques are utilized. A bypass capacitor of more than 10 mF between VDD and GND pin should be connected to ensure the performance. 8/25 ¡ Semiconductor MSM7557 (Continued) Name Function Power down control. Power down state is controlled by PDN, ME, RVE, and TVE. PDN Voice control Transmit side Receive side path modem modem OFF OFF OFF X OFF OFF ON 0 OFF ON ON ON ON PDN ME RVE TVE Mode1 1 X 0 X Mode2 1 X 1 Mode3 0 1 0 Mode4 others ON X : Don't care At the mode 4, all functions are powered on. At the full power down mode(PDN = "1" and RVE = "0"), the demodulator circuit and FD pin are reset. When VDD is turned ON, the demodulator circuit and FD pin should be reset by setting Mode1. Crystal connection. X1 3.6864 MHz crystal shall be connected. X2 When an external master clock is applied, the clock should be supplied to X2 pin via a 200 pF capacitor for AC coupling and X1 should be opened. MSK moudulator output. ME When digital "1" is applied to this pin, MSK modulator is connected to the splatter filter. Refer to TAO pin description. TVE Transmit side voice signal contorol. Refer to TAO pin description. 9/25 ¡ Semiconductor MSM7557 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Analog Input Voltage *1 VIA Digital Input Voltage *2 VID Storage Temperature TSTG Rating Condition Unit –0.3 to +7.0 Ta = 25°C Refer to GND –0.3 to VDD + 0.3 — –55 to +150 V °C *1 : LIM, VR2, TVI, RAI, CMPI *2 : SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, X2, ME, TVE RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Crystal Oscillating Freq. Top fX'TAL Data Signaling Rate TS C4, C5, C11, C12, C15 C6, C13 Condition from Min. Typ. Max. DYN = "0" 2.7 3.6 5.5 GND level DYN= "1" 4.5 5.0 5.5 VDD = 2.7 V to 5.5 V –30 +25 +70 — 3.6860 3.6864 3.6868 BR = 0" — 1200 — BR = "1" — 2400 — — — — 1.0 — — DYN = "0" — 0.22 — — DYN = "1" — 0.47 — C7, C8 — — — 1.0 — C9, C10 — RL ≥ 40kW — 0.22 — C14 — — — 10 — C19 C20, C21 — — — — — — 0.47 20 — — Unit V °C MHz bit/sec mF pF 10/25 ¡ Semiconductor MSM7557 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Symbol IDD IDDS1 Power Supply Current *1 IDDS2 IDDS3 Input Leakage Current *2 Input Voltege *2 Output Voltege *3 Condition Normal 3.6 V mode 5.5 V (mode 4) Power down mode 1 5.5 V Power down mode 2 Power down Min. Typ. Max. — 9.0 18 — 14.0 24 — 1.0 20 — 3.8 7.0 IIL VIN = 0 V IIH VIN = VDD IIL IIH — VOL IOL = –20 mA VOH IOH= 20 mA mA mA mA 3.6 V mode 3 Unit — 4.6 9.0 –10 — +10 0 0.7VDD — — 0.2VDD VDD 0 0.8VDD — — 0.1VDD VDD mA V *1 Refer to PDN pin description *2 SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, ME, TVE *3 ST, FD, RD, RT 11/25 ¡ Semiconductor MSM7557 AC Characteristics Parameter DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Symbol fM1 Condition Transmit fS1 SD = "1" SD= "0" Carrier Frequency fM2 SD = "1" fS2 SD= "0" Transmit VOX Carrier Level Receive Carrier R1 = R2 Min. Typ. Max. BR = "0" 1199 1200 1201 ME= "1" 1799 1800 1801 BR = "1" 1199 1200 1201 ME= "1" 2399 2400 2401 DYN = "0" –11 –9 –7 DYN = "1" –3 –1 +1 –32 — –2 — 1 ¥ 10-3 — 10-5 — VIR Input Level 8 dB 1200 Defined at 10 dB — 5¥ RAIO 11 dB — 1 ¥ 10-3 — bps 13 dB — 5 ¥ 10-5 — — — 18 Number of PLL Lock-in Number of data bits required for the PLL to be locked in within the phase difference of 22.5° or less Number of data bits required for the PLL to be locked in within the phase difference of 90° or less — Bit Error Rate bps 2400 Data Bits *1 BER VIR Unit Hz dBV — bit — 11 *1 Receive MSK signal is bit synchronous signal (modulated signal of alternating "0", "1" pattern). 12/25 ¡ Semiconductor MSM7557 Voice Signal Interfaces Parameter RVO Maximum Output Signal Level Limiter Clamp Level DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Symbol VOUT VLIM Condition Min. Typ. Max. DYN = "0" — — –6 BYP = "0" *1 DYN = "1" — — +2 fIN = 1 kHz DYN = "0" –10 –9 –8 LIM = open DYN = "1" –2 –1 0 fIN = 1 kHz Transmit Output Distortion HDT fIN = 1 kHz, –12 dBV — –40 — Receive Output Distortion Transmit Gain HDR BYP = "0", EMP = "1" — –40 — GT fIN = 1 kHz, BYP = EMP = "1" –1.5 –0.2 +1 Receive Gain GR fIN = 1 kHz, BYP = EMP = "1" –1.5 –0.2 +1 Transmit Idle Noise HIT BYP = "0" — –51 — Receive Idle Noise RCV.ÆTran. Cross Talk Tran.ÆRCV. HIR EMP = "1" — –85 — CTT RAIO = –2 dBV — –75 –60 CTR TVIO = –2 dBV — –80 –60 FT1 Transmit Filter Response FT3 FT25 FT34 FT60 FR1 Receive Filter Response FR3 FR25 FR34 FR60 EMP = "1" BYP = "1" RCK2 = "0" Ref. = 1 kHz EMP = "1" BYP = "1" RCK2 = "0" Ref. = 1 kHz *2 100 Hz — –28 –23 300 Hz –12.5 –10.5 –8.5 2.5 kHz +6.5 +8.0 +9.5 3.4 kHz +8.5 +10.5 +12.5 6 kHz — –40 –30 100 Hz +1.5 +3.0 +4.5 300 Hz +8.0 +9.5 +11.0 2.5 kHz –9.5 –8.0 –6.5 3.4 kHz –12.5 –10.5 –8.5 — –40 –30 6 kHz Unit dBV dB dBV dB *1 S/D ≥ 20 dB *2 fIN = 1 kHz, BYP = EMP = "1" 13/25 ¡ Semiconductor MSM7557 (Continued) DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Parameter Standard Input Level Compressor Maximum Input Level Output Level *3 Attack Time Recovery Time Standard Input Level Expander Maximum Output Level Output Level Symbol Condition VICS fIN = 1 kHz VICM GC2 GC4 fIN = 1 kHz GC5 Min. Typ. Max. DYN = "0" –16.1 –13.7 –11.3 DYN = "1" –7.1 –5.5 –3.9 DYN = "0" — — –7 DYN = "1" — — +1.0 –20 dB –10.6 –9.9 –9.2 –40 dB –21.0 –19.8 –18.6 –60 dB — –29.5 — TAT1 DYN = "0", C6 = 0.22 mF — 3.4 — TAT2 DYN = "1", C6 = 0.47 mF — 3.5 — TRE1 DYN = "0", C6 = 0.22 mF — 17 — TRE2 DYN = "1", C6 = 0.47 mF VIES fIN = 1 kHz VIEM GE1 GE2 GE3 fIN = 1 kHz *3 — 16 — *4 –12.9 –10.8 –8.7 *5 –13.3 –11.2 –9.1 *6 –4.7 –3.1 –1.5 DYN = "0" — — –6 DYN = "1" — — +2 –10 dB –21.5 –20 –18.3 –20 dB –42.2 –40 –37.5 –30 dB — –59 — TAT3 DYN = "0", C13 = 0.22 mF — 3.4 — Time TAT4 DYN = "1", C13 = 0.47 mF — 3.5 — Recovery TRE3 DYN = "0", C13 = 0.22 mF — 17 — Time TRE4 DYN = "1", C13 = 0.47 mF — 16 — Attack Unit dBV dB ms dBV dB ms *3 0 dB is defined as the input level and the output level when the standard input level is input. *4 VDD = 3.6 V, DYN = "0" *5 VDD = 5.0 V, DYN = "0" *6 VDD = 5.0 V, DYN = "1" 14/25 ¡ Semiconductor MSM7557 Common Characteristics Parameter Input Resistance Output Resistance Output Load Resistance DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Symbol Condition Min. Typ. Max. Unit RIA TVI, RAI, VR2 — 10 — MW RIC LIM — 200 — kW ROX1 TAO — 1750 — ROX2 VR1, VR3, RVO — 600 — ROX3 TVIO, RAIO — 100 — *1 40 — — TVIO 60 — — SG VDD – 0.1 2 VDD VDD + 0.1 TAO, RVO VDD – 0.15 2 VDD RXL1 RXL2 S/D ≥ 20 dB VSG Output DC Voltage VAO 2 2 2 VDD + 0.15 W kW V 2 *1 VR1, VR3, TAO, RVO, RAIO Digital Timing Characteristics Parameter Transmit Data Set-up Time Transmit Data Hold Time Receive Data Output Delay Sync-signal Output Delay (MEÆST) Symbol DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = –30°C to 70°C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = –30°C to 70°C Condition tS Min. Typ. Max. 1 — — 1 — — Refer to Fig. 1 tH Unit ms tD Refer to Fig. 1 –300 — 300 ns tMS Refer to Fig. 1 0 — 834 ms 15/25 ¡ Semiconductor MSM7557 TIMING DIAGRAM ST 50% 50% SD tS tH Figure 1 Input Data Timing RT 50% FD,RD 50% tD Figure 2 Output Data Timing FDE RT Internal RD N-2 N-1 N D1 D2 D3 D1 D2 D3 FD RD N-2, N-1, N : Frame shnchronous signal Figure 3 Receive Signal Timing 16/25 ¡ Semiconductor MSM7557 OPERATION DESCRIPTION Limiter Circuit A R12 R11 + LIM R11 : 1 kW R12 : 200 kW – Reverse HPF1 or PRE – EMPHASIS DYN = "0" DYN = "1" Limiter Splatter filter : Clamp level = VSG ±0.50 V : Clamp level = VSG ±1.26 V 2. In case of using external voltage reference LIM pin shall be supplied over VSG voltage. Notes 1 ) R11 is protection resister from external extra voltage. 2 ) Resistor value of R11 and R12 changes 0.7 to 1.3 times from the typical value by lot variation and temperature variation. 17/25 ¡ Semiconductor MSM7557 Frame Detector Frame detection pattern is defined by BIT and FPS. BIT FPS Sync-pattern Receiver Note 0 0 9336H S.H. Frame synchronous 0 1 C4D6H M.T. Frame synchronous 1 0 A9336H S.H. Bit + Frame synchronous 1 1 AC4D6H M.T. Bit + Frame synchronous M.T. = Master telephone S.H. = Slave handset Fig 3 shows detection timing First, put digital "0" level to FDE pin more than 1 ms, then FD pin is reset to "0" level. Next, put digital "1" level to FDE pin, then RT and RD output digital "1" level until frame synchronous signal detected. When synchronous pattern is detected, FD pin is held to digital "1" level. At the full power down state (PDN = "1", RVE = "0"), FD pin becomes reset state. In order to detect frame synchronous signal certainly, receive side PLL should be locked in sufficiently. When a modem starts data transmittion, the bit-synchronous signal of more than 18 bits should be transmitted before frame pattern of the upper table. Frame detection signal Internal RT D Q CK Q FD FDE D Q CK Q RT Internal RD RD Full power down signal (Internal signal) 18/25 ¡ Semiconductor MSM7557 Application Circuit MSM7557GS-2K Transmit data SD Transmit data timing clock ST TVE Transmit voice output control ME C20 MSK modulator control X2 3.6864 MHz Emphasis path select EMP X1 Limiter circuit clamp voltage input LIM PDN VR1 VDD C21 R1 VR2 R2 C19 R5 Transmit voice input C1 Power down control Power supply C14 + – VR3 CMPI TVIO RVE Receive voice output control RT Receive timing clock TVI RD Receive data CC1 FD Frame synchronous detector output CC2 FPS Synchronous pattern select CC3N BIT Bit synchronus detector control C3 R3 C2 R4 C4 C5 C6 CC3P Dynamic range select C8 DYN FDE Frame synchronous detector control SG BR Modem data signaling rate select GND BYP Compandor path select TAO RCK1 RVO RCK2 CE1 SEC CE2 CSH CE3N RAI C7 VDD C9 Transmit signal output Voice band select C10 Receive voice output C11 C12 + – C15 C13 C16 CE3P R6 R8 C18 Receive signal input R7 RAIO C17 Note : An arrow mark of ( ) indicates connection to the SG pin. 19/25 ¡ Semiconductor MSM7557 MSM7557 Filter Characteristics MSM7557 has wide band filters (0.3 kHz to 3.4 kHz) as follows. Pre-Emphasis ........................................................................................................ Fig. 4 Splatter Filter ........................................................................................................ Fig. 5 RBPF ....................................................................................................................... Fig. 6 De-Emphasis ......................................................................................................... Fig. 7 Transmit Total (HPF1 + Pre-Emphasis + Splatter) ......................................... Fig. 8 Receive Total (RBPF + De-Emphasis) ............................................................... Fig. 9 Transmit and Receive Total ................................................................................ Fig. 10 Fig. 4 to Fig. 10 show the filter characteristics when RCK2 is digital "0". When RCK1 is digital "0" and RCK2 is digital "1", the filter characteristics change 0.972 times on the frequency axis. (pass-band becomes narrow) When RCK1 is digital "1" and RCK2 is digital "1", the filter characteristics change 1.029 times on the frequency axis. (pass-band becomes wide) 20/25 ¡ Semiconductor MSM7557 10 100 0 1k 10k FREQ [Hz] –20 LEVEL [dB] –10 –30 Figure 4 MSM7557 Pre–Emphasis 100 1k 10k 0 –10 Fcut(–0.2 dB) = 3.4 kHz FREQ [Hz] –20 –30 –40 –60 –70 LEVEL [dB] –50 –80 Figure 5 MSM7557 Splatter Filter 21/25 ¡ Semiconductor MSM7557 100 0 1k 10k FREQ [Hz] –10 Fcut(–0.2 dB) = 3.4 kHz –20 –30 –40 –60 –70 LEVEL [dB] –50 –80 Figure 6 MSM7557 RBPF 20 10 100 1k 10k 0 –10 LEVEL [dB] FREQ [Hz] –20 Figure 7 MSM7557 De–Emphasis 22/25 ¡ Semiconductor MSM7557 10 100 0 1k 10k FREQ [Hz] –10 –20 –30 –40 LEVEL [dB] –50 –60 –70 Figure 8 MSM7557 Transmit Total (HPF1 + Pre–Emphasis+Splatter) 10 100 1k 10k 0 FREQ [Hz] –10 –20 –30 –50 –60 LEVEL [dB] –40 –70 Figure 9 MSM7557 Receive Total (RBPF + De–Emphasis) 23/25 ¡ Semiconductor MSM7557 100 1k 10k 0 FREQ [Hz] –10 –20 –30 –40 –60 –70 LEVEL [dB] –50 –80 Figure 10 MSM7557 Transmit and Receive Total 24/25 ¡ Semiconductor MSM7557 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/25