MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 JFET Switching Transistors N−Channel http://onsemi.com Features 2 SOURCE • Pb−Free Packages are Available 3 GATE MAXIMUM RATINGS Rating Symbol Value Unit Drain−Source Voltage VDS 30 Vdc Drain−Gate Voltage VDG 30 Vdc Gate−Source Voltage VGS 30 Vdc Forward Gate Current IG(f) 50 mAdc 1 DRAIN 3 1 THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR− 5 Board (Note 1) TA = 25°C Derate above 25°C 2 Symbol Max Unit 225 1.8 mW mW/°C PD Thermal Resistance, Junction−to−Ambient RqJA 556 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C SOT−23 CASE 318 STYLE 10 MARKING DIAGRAM Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. FR−5 = 1.0 0.75 0.062 in. 6x M G G 1 6x M G = Specific Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or overbar may vary depending upon manufacturing location. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 2 of this data sheet. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 5 1 Publication Order Number: MMBF4391LT1/D MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)GSS 30 − Vdc − − 1.0 0.20 nAdc mAdc −4.0 −2.0 −0.5 −10 −5.0 −3.0 − − 1.0 1.0 50 25 5.0 150 75 30 − − − 0.4 0.4 0.4 − − − 30 60 100 OFF CHARACTERISTICS Gate−Source Breakdown Voltage (IG = 1.0 mAdc, VDS = 0) Gate Reverse Current (VGS = 15 Vdc, VDS = 0, TA = 25°C) (VGS = 15 Vdc, VDS = 0, TA = 100°C) IGSS Gate−Source Cutoff Voltage (VDS = 15 Vdc, ID = 10 nAdc) VGS(off) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Off−State Drain Current (VDS = 15 Vdc, VGS = −12 Vdc) (VDS = 15 Vdc, VGS = −12 Vdc, TA = 100°C) Vdc ID(off) nAdc mAdc ON CHARACTERISTICS Zero−Gate−Voltage Drain Current (VDS = 15 Vdc, VGS = 0) IDSS MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Drain−Source On−Voltage (ID = 12 mAdc, VGS = 0) (ID = 6.0 mAdc, VGS = 0) (ID = 3.0 mAdc, VGS = 0) mAdc VDS(on) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 Static Drain−Source On−Resistance (ID = 1.0 mAdc, VGS = 0) Vdc W rDS(on) MMBF4391LT1 MMBF4392LT1 MMBF4393LT1 SMALL− SIGNAL CHARACTERISTICS Input Capacitance (VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Ciss − 14 pF Reverse Transfer Capacitance (VDS = 0, VGS = 12 Vdc, f = 1.0 MHz) Crss − 3.5 pF ORDERING INFORMATION Device MMBF4391LT1 MMBF4391LT1G MMBF4392LT1 MMBF4392LT1G MMBF4393LT1 MMBF4393LT1G Marking Package 6J SOT−23 6J SOT−23 (Pb−Free) 6K SOT−23 6K SOT−23 (Pb−Free) 6G SOT−23 6G SOT−23 (Pb−Free) Shipping † 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 TYPICAL CHARACTERISTICS 1000 TJ = 25°C MMBF4391 MMBF4392 MMBF4393 RK = RD’ 200 100 500 VGS(off) = 12 V = 7.0 V = 5.0 V 50 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 TJ = 25°C RK = RD’ 200 t r , RISE TIME (ns) t d(on) , TURN−ON DELAY TIME (ns) 1000 500 50 20 10 5.0 RK = 0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 1. Turn−On Delay Time 1000 500 TJ = 25°C MMBF4391 MMBF4392 MMBF4393 200 100 VGS(off) = 12 V = 7.0 V = 5.0 V RK = RD’ 50 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 20 30 50 Figure 2. Rise Time t f , FALL TIME (ns) t d(off) , TURN−OFF DELAY TIME (ns) 1000 500 VGS(off) = 12 V = 7.0 V = 5.0 V 100 2.0 1.0 0.5 0.7 1.0 50 MMBF4391 MMBF4392 MMBF4393 30 200 100 TJ = 25°C MMBF4391 MMBF4392 MMBF4393 20 RK = 0 10 5.0 Figure 3. Turn−Off Delay Time 2.0 3.0 5.0 7.0 10 20 ID, DRAIN CURRENT (mA) Figure 4. Fall Time http://onsemi.com 3 VGS(off) = 12 V = 7.0 V = 5.0 V 50 2.0 1.0 0.5 0.7 1.0 50 RK = RD’ 30 50 MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 NOTE 1 VDD RD SET VDS(off) = 10 V INPUT RK RT OUTPUT RGEN 50 W RGG 50 W VGEN INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 ms DUTY CYCLE ≤ 2.0% VGG 50 W RGG > RK RD’ = RD(RT + 50) RD + RT + 50 V fs , FORWARD TRANSFER ADMITTANCE (mmhos) Figure 5. Switching Time Test Circuit The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) of Gate−Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn−on interval, Gate−Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R’D) and Drain−Source Resistance (rDS). During the turn−off, this charge flow is reversed. Predicting turn−on time is somewhat difficult as the channel resistance rDS is a function of the gate−source voltage. While Cgs discharges, VGS approaches zero and rDS decreases. Since Cgd discharges through rDS, turn−on time is non−linear. During turn−off, the situation is reversed with rDS increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD’ which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 15 20 MMBF4392 10 C, CAPACITANCE (pF) MMBF4391 10 MMBF4393 7.0 Tchannel = 25°C 5.0 VDS = 15 V 3.0 2.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 Cgs 7.0 Cgd 5.0 3.0 2.0 1.5 Tchannel = 25°C (Cds is negligible 1.0 0.03 0.05 0.1 50 ID, DRAIN CURRENT (mA) 50 mA 75 mA 100 mA 125 mA r DS(on), DRAIN−SOURCE ON−STATE RESISTANCE (NORMALIZED) r DS(on), DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) IDSS 25 mA = 10 160 mA 120 80 40 Tchannel = 25°C 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 VGS, GATE−SOURCE VOLTAGE (VOLTS) 30 Figure 7. Typical Capacitance Figure 6. Typical Forward Transfer Admittance 200 0.3 0.5 1.0 3.0 5.0 10 VR, REVERSE VOLTAGE (VOLTS) 8.0 2.0 1.8 ID = 1.0 mA VGS = 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 −70 −40 −10 20 50 80 110 140 170 Tchannel, CHANNEL TEMPERATURE (°C) Figure 8. Effect of Gate−Source Voltage on Drain−Source Resistance Figure 9. Effect of Temperature on Drain−Source On−State Resistance http://onsemi.com 4 MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 100 90 80 70 60 50 40 30 20 10 0 10 Tchannel = 25°C 9.0 8.0 7.0 rDS(on) @ VGS = 0 6.0 VGS(off) 5.0 4.0 3.0 2.0 1.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 V GS , GATE−SOURCE VOLTAGE (VOLTS) r DS(on) , DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) NOTE 2 IDSS, ZERO−GATE VOLTAGE DRAIN CURRENT (mA) Figure 10. Effect of IDSS on Drain−Source Resistance and Gate−Source Voltage The Zero−Gate−Voltage Drain Current (IDSS) is the principle determinant of other J−FET characteristics. Figure 10 shows the relationship of Gate−Source Off Voltage (VGS(off)) and Drain−Source On Resistance (rDS(on)) to IDSS. Most of the devices will be within ±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rDS(on) and VGS range for an MMBF4392 The electrical characteristics table indicates that an MMBF4392 has an IDSS range of 25 to 75 mA. Figure 10 shows rDS(on) = 52 W for IDSS = 25 mA and 30 W for IDSS = 75 mA. The corresponding VGS values are 2.2 V and 4.8 V. http://onsemi.com 5 MMBF4391LT1, MMBF4392LT1, MMBF4393LT1 PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. 318−01 THRU −07 AND −09 OBSOLETE, NEW STANDARD 318−08. D SEE VIEW C 3 HE E c 1 2 b DIM A A1 b c D E e L L1 HE 0.25 e q A L A1 L1 VIEW C MIN 0.89 0.01 0.37 0.09 2.80 1.20 1.78 0.10 0.35 2.10 MILLIMETERS NOM MAX 1.00 1.11 0.06 0.10 0.44 0.50 0.13 0.18 2.90 3.04 1.30 1.40 1.90 2.04 0.20 0.30 0.54 0.69 2.40 2.64 MIN 0.035 0.001 0.015 0.003 0.110 0.047 0.070 0.004 0.014 0.083 INCHES NOM 0.040 0.002 0.018 0.005 0.114 0.051 0.075 0.008 0.021 0.094 MAX 0.044 0.004 0.020 0.007 0.120 0.055 0.081 0.012 0.029 0.104 STYLE 10: PIN 1. DRAIN 2. SOURCE 3. GATE SOLDERING FOOTPRINT* 0.95 0.037 0.95 0.037 2.0 0.079 0.9 0.035 SCALE 10:1 0.8 0.031 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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