FAIRCHILD FAN2103

FAN2103 — TinyBuck™
3A, 24V Input Integrated Synchronous Buck Regulator
Features
Description
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Over 95% efficiency
The FAN2103 TinyBuck™ is an easy-to-use, cost- and
space-efficient, synchronous buck solution. It enables
designers to solve high-current requirements in a small
area with minimal external components.
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Integrated low-side Schottky diode
Internal power MOSFETs:
High-side RDS(ON) = 31mΩ
Low-side RDS(ON) = 23mΩ
Programmable frequency operation up to 750KHz
The summing current mode modulator uses lossless
current sensing for current feedback and over-current,
and includes voltage feedforward.
Power-good signal
Wide input range: 3.0V to 24V
Output voltage range: 0.8V to 90%VIN
Fairchild’s advanced BiCMOS power process,
combined with a thermally efficient MLP package,
provides low-RDS(ON), internal MOSFETs, and the ability
to dissipate high power in a small package.
Input under-voltage lockout (UVLO)
Programmable over-current protection
Under-voltage, over-voltage, and thermal protection
Selectable light-load power-saving mode
5x6mm, 25-pin, 3-pad MLP
External programming of clock frequency, current limit,
and loop response allows for optimization and flexibility
selecting output filter components and transient response.
Under-voltage, thermal shutdown, and power-good are
blanked at start-up, but protect the device from damage
during fault conditions.
Applications
Related Application Notes
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Thin and light Notebook PCs
AN-5067 – PCB land pattern design and surface
mount guidelines for MLP packages
Graphics cards
Battery-powered equipment
Set-top box
Point-of-load regulation
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing Method
FAN2103MPX
-10°C to 85°C
25-Pin Molded Leadless Package (MLP) 5x6mm
Tape and Reel
FAN2103EMPX
-40°C to 85°C
25-Pin Molded Leadless Package (MLP) 5x6mm
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
December 2007
P2
+5V
RRAMP
VCC
15
1
VIN
VIN
BOOT
CHF
CIN
Q1
C4
RILIM
RT
25
PGOOD
13
EN
14
ILIM
17
R(T)
18
P3
PGND
COMP
20
24
PWM#
19
FB
C2
C1
CBOOT
RAMP
AGND
Q2
P1
VOUT
SW
L
PWM
MODULATOR
COUT
16
R1
C3
RBIAS
R2
R3
Figure 1. Typical Application
Block Diagram
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Application Diagram
Figure 2. Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
2
Figure 3. MLP 5x6mm Pin Configuration (Bottom View)
Pin Definitions
Pin
Name
Description
P1, 6-12
SW
Switching Node.
P2, 2-5
VIN
Power Input Voltage. Connect to the main input power source.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes
an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when
SW is LOW.
13
PGOOD
Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range
of the reference when EN is HIGH. PGOOD does not assert HIGH until the fault latch is
enabled.
14
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
15
VCC
16
AGND
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the default setting.
18
R(T)
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
24
PWM#
Power Save Mode / Forced PWM. Connect to VCC to enable light-load, power-saving mode
of operation. Connect to GND or leave open for fixed-frequency PWM mode.
25
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp
amplitude and provides voltage feedforward functionality.
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Pin Configuration
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
VIN to PGND
VCC to AGND
AGND = PGND
SW to PGND
ESD
28
V
6
V
V
-0.3
6.0
V
-5
30
V
-0.3
VCC+0.3
V
Transient (t < 20ns, F < 600KHz)
All other pins
Unit
35
BOOT to PGND
BOOT to SW
Max.
Human Body Model, JESD22-A114
2.0
Charged Device Model, JESD22-C101
2.0
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
5.0
VCC
Bias Voltage
VCC to AGND
4.5
5.5
V
VIN
Supply Voltage
VIN to PGND
3
24
V
TA
Ambient Temperature
FAN2103M
-10
+85
°C
FAN2103EM
-40
TJ
Junction Temperature
+85
°C
+125
°C
Max.
Unit
Thermal Information
Symbol
TSTG
Parameter
Min.
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+300
°C
TVP
Vapor Phase, 60 Seconds
+215
°C
TI
Infrared, 15 Seconds
+220
°C
θJC
Thermal Resistance: Junction-to-Case
θJ-PCB
PD
Storage Temperature
Typ.
-65
P1 (Q2)
4
°C/W
P2 (Q1)
7
°C/W
P3
4
°C/W
Thermal Resistance: Junction-to-Mounting Surface
Power Dissipation, TA = 25°C
35
(1)
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
°C/W
2.8
(1)
W
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 26. Actual results
are dependent on mounting method and surface related to the design.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
4
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
8
12
mA
Power Supplies
SW = Open, FB = 0.7V, VCC = 5V,
FSW = 600KHz
VCC Current
Shutdown: EN = 0, VCC = 5V
Power Saving Mode, VCC = 5V, FMIN
Rising VCC
VCC UVLO Threshold
4.1
Hysteresis
7
10
µA
2.2
4.5
mA
4.3
4.5
V
300
mV
Power Output Section
N-Channel (Q1) RDS(ON)
VCC = 5V, 25°C
N-Channel (Q2) RDS(ON)
31
35
mΩ
23
25
mΩ
Oscillator
Frequency
Minimum On-Time
255
300
345
KHz
RT = 24KΩ
540
600
660
KHz
50
65
ns
(2)
16VIN, 1.8VOUT, RT = 30KΩ,
RRAMP = 200KΩ
Ramp Amplitude, pk–pk
Minimum Off-Time
RT = 50KΩ
0.53
(2)
V
100
150
ns
Reference
Reference Voltage (VFB)
FAN2103M, 25°C
794
800
806
mV
FAN2103EM, 25°C
795
800
805
mV
FAN2103M,
Temp. Coefficient (-10 to +85°C)
50
PPM
FAN2103EM
Temp. Coefficient (-40 to +85°C)
70
PPM
80
85
dB
12
15
Error Amplifier
DC Gain
(2)
Gain Bandwidth Product
(2)
VCC = 5V
Output Voltage (VCOMP)
0.4
Output Current, Sourcing
VCC = 5V, VCOMP = 2.2V
Output Current, Sinking
VCC = 5V, VCOMP = 1.2V
FB Bias Current
VFB = 0.8V, 25°C
1.5
MHz
3.2
2.2
V
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Electrical Specifications
mA
0.8
1.2
-850
-650
-450
mA
nA
3.8
5.0
7.0
A
10
11
µA
Protection and Shutdown
Current Limit
RILIM open
ILIM Current
25°C, VCC = 5V
Over-Temperature Shutdown
Over-Temperature Hysteresis
9
Internal Temperature
160
°C
30
°C
Over-Voltage Threshold
2 Consecutive Clock Cycles
110
115
120
%VOUT
Under-Voltage Shutdown
16 Consecutive Clock Cycles
68
73
78
%VOUT
Fault Discharge Threshold
Measured at FB Pin
250
mV
Fault Discharge Hysteresis
Measured at FB Pin (VFB ~500mV)
250
mV
Note:
2. Specifications guaranteed by design and characterization; not production tested.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
5
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Soft-Start
VOUT to Regulation (T0.8)
Fault Enable/SSOK (T1.0)
Frequency = 600KHz
5.3
ms
6.7
ms
Control Functions
EN Threshold, Rising
1.35
EN Hysteresis
250
mV
EN Pull-up Resistance
800
KΩ
1
µA
EN Discharge Current
Auto-restart Mode
V
800
Ω
FB < VREF
-14
-11
-8
%VFB
FB > VREF
107
110
113
%VFB
FB OK Drive Resistance
PGOOD Threshold
2.00
PGOOD Output Low
IOUT < 2mA
0.4
V
PGOOD Output High
VPGOOD = 5V
1
µA
0.6
0.8
V
1.0
1.2
µA
PWM# Threshold
PWM# Input Current
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
VPWM# = 0.4V
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Electrical Specifications (Continued)
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6
1.20
1.005
1.10
I FB
V FB
1.010
1.000
0.995
1.00
0.90
0.990
0.80
-50
0
50
100
150
-50
0
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
150
1.02
1200
1.01
Frequency
Frequency (KHz)
100
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
1500
900
600
600KHz
1.00
300KHz
0.99
300
0.98
0
0
20
40
60
80
100
120
-50
140
0
RT (KΩ)
50
100
150
o
Temperature ( C)
Figure 6. Frequency vs. RT
Figure 7.
Frequency vs. Temperature, Normalized
1.04
1.60
1.40
1.02
1.20
I ILIM
RDS
50
Temperature (oC)
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Characteristics
1.00
1.00
o
Q1 ~0.32 %/ C
0.80
0.98
o
Q2 ~0.35 %/ C
0.96
0.60
-50
0
50
100
150
-50
50
100
150
Temperature ( C)
Temperature ( C)
Figure 9.
Figure 8. RDS vs. Temperature, Normalized
(VCC = VGS = 5V)
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
0
o
o
ILIM Current (IILIM) vs. Temperature,
Normalized
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7
Figure 10. Application Circuit: 1.8 VOUT, 500KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=16V, VCC=5V, unless otherwise specified.
1.0
95
0.9
Loss8V (W)
90
0.8
Loss12V (W)
85
0.7
Loss_PSM (W)
80
0.6
Loss18V (W)
Loss (W)
Efficiency (%)
Power Loss
Efficiency
100
75
Effi8V (%)
70
60
0.2
Effi_PSM_12V(%)
Power Saving Mode, 12VIN
55
0.00
0.50
1.00
1.50
0.1
Effi18V (%)
2.00
2.50
0.4
0.3
Effi12V (%)
65
0.5
0.0
0.00
3.00
0.50
1.00
Load Current (A)
Figure 11.
2.00
2.50
3.00
Load Current (A)
1.8 VOUT Efficiency Over VIN vs. Load
Figure 12. 1.8 VOUT Dissipation Over VIN vs. Load
Regulation Characteristic
1.828
1.50
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Application Circuit
Efficiency
100
95
1.826
Efficiency (%)
Vo (V)
90
1.824
1.822
80
75
Vo8V (V)
1.820
85
Vo12V (V)
V IN =8V, 300KHz
70
Vo18V (V)
1.818
0.00
V IN =12V, 500Khz
65
0.50
1.00
1.50
2.00
Load Current (A)
2.50
0.00
3.00
1.00
1.50
2.00
2.50
3.00
Load Curr e nt (A)
Figure 13. 1.8 VOUT Regulation vs. Load
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
0.50
Figure 14. 3.3 VOUT Efficiency vs. Load
(Circuit Values Changed)
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8
Typical operating characteristics using the circuit shown in Figure 10. VIN=12V, VCC=5V, unless otherwise specified.
Figure 15. SW and VOUT Ripple, 3A Load
Figure 16. SW and VOUT Ripple, 0.5A Load
Figure 17. Transient Response, 1.5-3A Load
(Circuit Values Changed)
Figure 18. Transient Response, 0.3-3A Load
(Circuit Values Changed)
Figure 19.
Start-up, 3A Load
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
Figure 20.
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Shutdown, 3A Load
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9
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) can be calculated using:
Initialization
Once VCC exceeds the UVLO threshold and EN is
HIGH, the IC checks for an open or shorted FB pin
before releasing the internal soft-start ramp (SS).
ICC(mA ) = 4.58 + [(
If R1 is open, the error amplifier output (COMP) is forced
LOW and no pulses are generated. After the SS ramp
times out (T1.0), an under-voltage latched fault occurs.
VCC − 5
+ 0.013) • (F − 128 )]
227
(1)
where frequency (F) is expressed in KHz.
If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
Setting the Output Voltage
Soft-Start
The internal reference is 0.8V with 650nA, sourced from
the FB pin to ensure that if the pin is open, the regulator
does not start.
The output voltage of the regulator can be set from 0.8V
to ~90% of VIN by an external resistor divider (R1 and
RBIAS in Figure 1).
Once SS has charged to 0.8V (T0.8), the output voltage
is in regulation. Until SS reaches 1.0V (T1.0), the “Fault
Latch” and power-saving mode operations are inhibited.
The external resistor divider is calculated using:
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold.
− 0 .8 V
V
0 .8 V
= OUT
+ 650nA
RBIAS
R1
Soft-start time is a function of oscillator frequency.
(2)
Connect RBIAS between FB and AGND.
EN
To minimize noise on the FB node, the values of R1
and RBIAS should be selected to provide a minimum
parallel impedance of 1KΩ.
1.35V
2400 CLKs
0.8V
Setting the Frequency
FB
Oscillator frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND:
Fault
Latch
Enable
1.0V
0.8V
F(KHz ) =
SS
(3)
where RT is expressed in KΩ.
3200 CLKs
(10 6 / F) − 135
65
where frequency (F) is expressed in KHz.
T0.8
R T ( KΩ ) =
4000 CLKs
T1.0
Figure 21. Soft-Start Timing Diagram
(4)
The regulator does not start if RT is left open.
Calculating the Inductor Value
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until SS
reaches 95% of VREF (~0.76V). This helps the regulator
start against pre-biased outputs and ensures that
inductor current does not "ratchet" up during the softstart cycle.
Typically the inductor is set for a ripple current (ΔIL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the
high side of this range, while regulators that require very
low output ripple and/or use high-ESR capacitors
restrict allowable ripple current:
VCC UVLO or toggling the EN pin discharges the SS and
resets the IC.
ΔIL =
Bias Supply
The FAN2103 requires a 5V supply rail to bias the IC
and provide gate-drive energy and controller power.
Connect a >1.0µf X5R or X7R decoupling capacitor
between VCC and PGND. Whenever EN pin is pulled
up to VCC, the 5V supply connected to VCC should be
turned ON after VIN comes up. If the power supply is
turned ON using EN pin with an external control after
VCC and VIN come up, the VCC and VIN power
sequencing is not relevant.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
10 6
( 65 • R T ) + 135
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Circuit Description
VOUT • (1 - D)
L •F
(5)
where F is the oscillator frequency, and
L=
VOUT • (1 - D)
ΔIL • F
(6)
The selection of inductor influences the entry into
power-saving mode. Consider minimum and maximum
load conditions before inductor selection.
www.fairchildsemi.com
10
The internal ramp voltage excursion (ΔVRAMP) during tON
should be set to 0.6V. RRAMP is approximately:
RRAMP(KΩ ) =
( VIN − 1.8) • VOUT
−2
18 x10 − 6 • VIN • F
(7)
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which could make it difficult
to compensate the loop. For designs with low input
voltages (3V to 6.5V), it is recommended that separate
RRAMP and the compensation component values are
used as compared to designs with VIN between 6.5V
and 24V.
where frequency (F) is expressed in KHz.
Setting the Current Limit
There are two levels of current limit thresholds in
FAN2103. The first level of protection is through an
internal default limit set at the factory to limit output
current beyond normal usage levels. The second level
of protection is a flexible one to be set externally by the
user. Current limit protection is enabled whenever the
lower of the two thresholds is reached. The FAN2103
uses its internal low-side MOSFET as the currentsensing element. The current-limit threshold voltage
(VILIM) is compared to the voltage drop across the lowside MOSFET, sampled at the end of each PWM offtime/cycle. The internal default threshold (with ILIM open)
is temperature compensated.
Protection
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
and under-voltage conditions.
An internal “Fault Latch” is set for any fault intended to
shut down the IC. When the fault latch is set, the IC
discharges VOUT by enhancing the low-side MOSFET
until FB<0.25V. The MOSFET is not turned on again
unless FB>0.5V. This behavior discharges the output
without causing undershoot (negative output voltage).
The 10µA current sourced from the ILIM pin can be
used to establish a lower, temperature–dependent,
current-limit threshold by connecting an external
resistor (RILIM) to AGND:
RILIM(KΩ) = 10.4 • K T • (IOUT −
ΔIL
) + 142.5
2
0.25/0.5V
(8)
FAULT
PWM GATE
DRIVE
FB
where:
IOUT = desired current limit set point in Amps,
KT = the normalized temperature coefficient of the
low-side MOSFET (Q2) from Figure 8.
PWM LATCH
Figure 23. Latched Fault Response
Under-Voltage Shutdown
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to Auto-Restart section).
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
The over-current protection fault latch is active during
the soft-start cycle. Use a 1% resistor for RILIM.
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Because the FAN2103 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
Setting the Ramp Resistor Value
Over-Voltage Protection / Shutdown
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
Loop Compensation
The loop is compensated using a feedback network
around the error amplifier. Figure 22 shows a complete
Type-3 compensation network. Type-2 compensation
eliminates R3 and C3.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1µA to a 1.1V
threshold before the 800KΩ pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35V.
Depending on the external circuit, the FAN2103 can be
provisioned to remain latched-off or automatically
restart after a fault.
Figure 22. Compensation Network
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
11
EN pin
Controller / Restart State
Pull to GND
OFF (disabled)
VCC
No restart – latched OFF
Open
Immediate restart after fault
Cap to GND
New soft-start cycle after:
tDELAY (msec) = 3.9 • C(nf)
The IC is prevented from switching in the audible band.
If the FB pin has not dropped to VREF within 40µs of the
last pulse, the IC sinks current through the inductor to
initiate a new cycle.
Transition back to PWM mode is achieved when a load
transient causes the output voltage to drop 1.5% below
its regulation point.
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or drive it with a logic gate to keep the 1µA current
sink from discharging EN to 1.1V.
1.85
PSM to PWM
1.84
PWM to PSM
1.83
1.82
1.81
PSM to PWM
Transition
PWM to PSM
Transition
1.8
1.79
1.78
0
0.25
0.5
0.75
1
1.25
1.5
Figure 25. Power-Saving Mode Regulation
(Using Figure 10 Circuit)
Power-saving mode operation can be disabled by
connecting the PWM# pin to AGND, allowing only PWM
operation. The PWM# pin has a 1µA pull-down. If <0.6V
is detected, power-saving mode operation is disabled.
Figure 24.
Fault Latch with Delayed Auto-Restart
PCB Layout
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Power Good (PGOOD) Signal
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
During power-saving mode, the output is regulated to a
slightly higher value than its set point, since the current
pulse is triggered when FB crosses VREF.
Table 1. Fault / Restart Provisioning
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin (thresholds are specified in the Electrical
Specifications section). PGOOD does not assert HIGH
until the fault latch is enabled (T1.0).
Power-Saving Mode
Figure 26. Recommended PCB Layout
The FAN2103 maintains high efficiency at light load by
changing to a discontinuous, constant peak current,
power-saving mode (PSM).
The transition to power-saving mode occurs when the load
is <ΔIL/2 for eight consecutive clock cycles.
In power-saving mode, a constant-peak inductor current
(ΔILPSM) is generated each on-cycle. ΔILPSM is nominally
85% larger than PWM-mode inductor ripple (ΔIL).
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
12
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV2
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
Physical Dimensions
BOTTOM VIEW
Figure 27. 5x6mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
13
FAN2103 — TinyBuck™ 3A, 24V Input Integrated Synchronous Buck Regulator
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
14