FAN2110 — TinyBuck™, 3-24 V Input, 10 A, HighEfficiency, Integrated Synchronous Buck Regulator
Features
Description
Wide Input Voltage Range: 3 V-24 V
The FAN2110 TinyBuck™ is a highly efficient, small
footprint,
constant
frequency,
10 A
integrated
synchronous Buck regulator.
Fully Synchronous Operation with Integrated
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
Wide Output Voltage Range: 0.8 V to 80% VIN
10 A Output Current
1% Reference Accuracy Over Temperature
Over 93% Peak Efficiency
Programmable Frequency Operation: 200 KHz to
600 KHz
Internal Bootstrap Diode
Internal Soft-Start
Power-Good Signal
Starts up on Pre-Bias Outputs
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Programmable Current Limit
Under-Voltage, Over-Voltage, and Thermal
Shutdown Protections
5x6 mm, 25-Pin, 3-Pad MLP Package
Applications
The FAN2110 contains both synchronous MOSFETs
and a controller/driver with optimized interconnects in
one package, which enables designers to solve highcurrent requirements in a small area with minimal
external components. Integration helps to minimize
critical inductances making component layout simpler
and more efficient compared to discrete solutions.
The FAN2110 provides for external loop compensation,
programmable switching frequency, and current limit.
These features allow design flexibility and optimization.
High frequency operation allows for all ceramic solutions.
The summing current mode modulator uses lossless
current sensing for current feedback and over-current
protection. Voltage feedforward helps operation over a
wide input voltage range.
Fairchild’s advanced BiCMOS power process, combined
with low-RDS(ON) internal MOSFETs and a thermally
efficient MLP package, provide the ability to dissipate
high power in a small package.
Output over-voltage, under-voltage, and thermal
shutdown protections help protect the device from
damage during fault conditions. FAN2110 also prevents
pre-biased output discharge during startup in point-ofload applications.
Servers & Telecom
Graphics Cards & Displays
Related Application Notes
Computing Systems
TinyCalc™ Calculator Design Tool
Point-of-Load Regulation
AN-8022 — TinyCalc™ Calculator User Guide
Set-Top Boxes & Game Consoles
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing
Method
FAN2110MPX
FAN2110EMPX
-10°C to 85°C
-40°C to 85°C
Molded Leadless Package (MLP) 5x6 mm
Molded Leadless Package (MLP) 5x6 mm
Tape and Reel
Tape and Reel
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
November 2012
IN
P2
Boot
Diode
+5V
CHF
CIN
VCC
C4
15
1
Q1
RRAMP
RAMP
Power
Good
PGOOD
Enable
EN
RILIM
ILIM
RT
R(T)
COMP
CBOOT
25
13
14
17
Q2
P1
PWM
+
DRIVER
18
P3
POWER
MOSFETS
20
AGND
OUT
SW
L
COUT
19
16
PGND
24 NC
C2
C1
BOOT
R1
FB
C3
RBIAS
R2
R3
Figure 1. Typical Application Diagram
Block Diagram
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Application
Figure 2. Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
2
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pin Definitions
Pin #
Name
Description
P1, 6-12
SW
Switching Node. Junction of high-side and low-side MOSFETs.
P2, 2-5
VIN
Power Conversion Input Voltage. Connect to the main input power source.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes
an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when
SW is LOW.
13
PGOOD
14
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
15
VCC
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin. This
pin should be decoupled to AGND through a > 2.2 µF X5R / X7R capacitor.
16
AGND
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the internal default setting.
18
R(T)
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
24
NC
25
RAMP
Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits
specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
Compensation. Error amplifier output. Connect the external compensation network between
this pin and FB.
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Pin Configuration
No Connect. This pin is not used.
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp amplitude
and provides voltage feedforward functionality.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
Max.
VIN to PGND
VCC to AGND
AGND=PGND
BOOT to PGND
BOOT to SW
SW to PGND
Continuous
ESD
28
V
6
V
35
V
-0.5
6.0
V
-0.5
24.0
V
-5
30
V
-0.3
VCC+0.3
V
Transient (t < 20 ns, f < 600 KHz)
All other pins
Unit
Human Body Model, JEDEC JESD22-A114
2.0
Charged Device Model, JEDEC JESD22-C101
2.5
KV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
5.0
5.5
V
VCC
Bias Voltage
VCC to AGND
4.5
VIN
Supply Voltage
VIN to PGND
3
24
V
TA
Ambient Temperature
FAN2110MPX
-10
+85
°C
FAN2110EMPX
-40
TJ
Junction Temperature
fSW
Switching Frequency
200
+85
°C
+125
°C
600
kHz
Max.
Unit
+150
°C
Thermal Information
Symbol
TSTG
TL
θJC
θJ-PCB
PD
Parameter
Min.
Storage Temperature
Typ.
-65
Lead Soldering Temperature, 10 Seconds
+300
Thermal Resistance: Junction-to-Case
4
°C/W
P2 (Q1)
7
°C/W
P3
4
°C/W
(1)
Thermal Resistance: Junction-to-Mounting Surface
Power Dissipation, TA=25°C(1)
°C
P1 (Q2)
35
°C/W
2.8
W
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 35. Actual results
are dependent on mounting method and surface related to the design.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
www.fairchildsemi.com
4
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN=12 V, unless otherwise noted.
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
SW=Open, VFB=0.7 V, VCC=5 V,
fSW =600 KHz
8
12
mA
Shutdown: EN=0, VCC=5 V
7
10
µA
4.3
4.5
Power Supplies
ICC
VUVLO
VCC Current
4.1
Rising VCC
VCC UVLO Threshold
Hysteresis
300
V
mV
Oscillator
fSW
Frequency
RT=50 KΩ to GND
255
300
345
KHz
RT=24 KΩ to GND
540
600
660
KHz
50
65
ns
(2)
tONmin
Minimum On-Time
VRAMP
Ramp Amplitude, Peak-to-Peak
tOFFmin
Minimum Off-Time(2)
16 VIN, 1.8 VOUT, RT=30 KΩ,
RRAMP=200 KΩ
0.53
V
100
150
ns
Reference
VFB
Reference Voltage (see Figure 4 for
Temperature Coefficient)
FAN2110MPX, 25°C
794
800
806
mV
FAN2110EMPX, 25°C
795
800
805
mV
80
85
dB
12
15
MHz
Error Amplifier
G
GBW
VCOMP
ISINK
ISOURCE
IBIAS
DC Gain(2)
(2)
Gain Bandwidth Product
VCC=5 V
(2)
Output Voltage
0.4
3.2
V
Output Current, Sourcing
VCC=5 V, VCOMP=2.2 V
1.5
2.2
mA
Output Current, Sinking
VCC=5 V, VCOMP=1.2 V
0.8
1.2
mA
FB Bias Current
VFB=0.8 V, 25°C
-850
-650
-450
nA
RILIM=182 KΩ,, 25°C, fSW =500 KHz,
VOUT=1.5 V, RRAMP=243 KΩ,
16 Consecutive Clock Cycles(3)
12
14
16
A
VCC=5 V, 25°C
-11
-10
-9
µA
Protection and Shutdown
ILIM
Current Limit (see Circuit
Description)(2)
IILIM
ILIM Current
TTSD
THYS
Over-Temperature Shutdown
(2)
Over-Temperature Hysteresis
(2)
Internal IC Temperature
(3)
+155
°C
+30
°C
VOVP
Over-Voltage Threshold
2 Consecutive Clock Cycles
VUVSD
Under-Voltage Shutdown
16 Consecutive Clock Cycles(3)
110
115
121
%VOUT
68
73
78
%VOUT
VFLT
Fault Discharge Threshold
Measured at FB Pin
250
mV
VFLT_HYS
Fault Discharge Hysteresis
Measured at FB Pin (VFB ~500 mV)
250
mV
5.3
ms
6.7
ms
Soft-Start
tSS
tEN
VOUT to Regulation (T0.8)
(2)
Fault Enable/SSOK (T1.0)
fSW =500 KHz
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
5
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN=12 V, unless otherwise noted.
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
V
Control Functions
VEN
EN Threshold, Rising
VCC=5 V
1.35
EN Hysteresis
VCC=5 V
250
mV
REN
EN Pull-Up Resistance
VCC=5 V
800
KΩ
IEN_DISC
EN Discharge Current
Auto-Restart Mode, VCC=5 V
1
µA
VEN_HYS
RFBok
FB OK Drive Resistance
VPGTH_LO
PGOOD LOW Threshold
VPGTH_UP
800
FB < VREF, 2 Consecutive Clock
Cycles(3)
-14
FB > VREF, 2 Consecutive Clock
Cycles(3)
+7
VPG_LO
PGOOD Output Low
IOUT < 2 mA
IPG_LK
PGOOD Leakage Current
VPGOOD=5 V
Notes:
2. Specifications guaranteed by design and characterization; not production tested.
3. Delay times are not tested in production. Guaranteed by design.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
2.00
-11
Ω
-8
%VREF
+10
+13.5
0.4
V
0.2
1.0
µA
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications (Continued)
www.fairchildsemi.com
6
1.20
1.005
1.10
I FB
V FB
1.010
1.000
0.995
1.00
0.90
0.990
0.80
-50
0
50
100
150
-50
0
Temperature (oC)
Figure 4. Reference Voltage (VFB)
vs. Temperature, Normalized
150
1.02
1200
1.01
Frequency
Frequency (KHz)
100
Figure 5. Reference Bias Current (IFB)
vs. Temperature, Normalized
1500
900
600
600KHz
1.00
300KHz
0.99
300
0.98
0
0
20
40
60
80
100
120
-50
140
0
RT (KΩ)
100
150
Temperature ( C)
Figure 7.
1.04
1.2
1.02
I ILIM
1.4
Q1 ~0.32%/°C
1
50
o
Figure 6. Frequency vs. RT
RDS
50
Temperature (oC)
Frequency vs. Temperature, Normalized
1.00
Q2 ~0.35%/°C
0.98
0.8
0.96
0.6
-50
0
50
100
-50
150
50
100
150
o
Temperature ( C)
Temperature (°C)
Figure 9.
Figure 8. RDS vs. Temperature, Normalized
(VCC=VGS=5 V), Figure 1
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
0
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Characteristics
ILIM Current (IILIM) vs. Temperature,
Normalized
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7
FAN2110
VCC
+5V
2.2u
P2
15
VIN
10-20 VIN
10K
X5R
PGOOD
243K
13
3 x 10u
3.3n
VOUT
X5R
NC 24
2.49K
34
COMP
2.49K
5.6n
RAMP
25
20
120p
FB
1
19
BOOT
* Cooper Industries
HC8-1R2-R
5.6n
ILIM
0.1u
17
VOUT
EN
182K
14
P1
SW
1.2u *
R(T)
18
1.5
30.1K
2.80K
4 x 47u
AGND
P3 PGND
16
X5R
390p
3.3n
Figure 10. Application Circuit: 1.5 VOUT, 10 A, 500 KHz (10 V-20 VIN)
FAN2110
VCC
+5V
2.2u
100
P2
15
VIN
10K
X5R
3.3-5.5 VIN
1u
PGOOD
13
3.3n
10u
VOUT
X5R
NC 24
140K
4.99K
100
COMP
2.49K
3.3n
20
25 RAMP
19
1
330p
FB
BOOT
* Cooper Industries
HC8-R75-R
2.2n
ILIM
0.1u
17
VOUT
EN
182K
14
P1
SW
750n *
R(T)
18
1.5Ω
30.1K
2.80K
4 x 47u
AGND
P3 PGND
16
390p
470u
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Application Circuits
X5R
3.3n
Figure 11. Application Circuit: 1.5 VOUT, 10 A, 500 KHz (3.3 V-5.5 VIN)
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
8
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C, unless otherwise specified.
FAN2110_1.5V_500Khz
FAN2110_3.3V_500Khz
100
100
95
95
Efficiency (%)
Efficiency (%)
90
85
80
90
85
80
VIN = 10V
VIN = 10V
VIN = 12V
VIN = 12V
75
75
VIN = 16V
VIN = 16V
VIN = 20V
VIN = 20V
70
70
0
2
4
6
8
10
0
2
Load Current (Am ps)
Figure 12.
4
6
8
10
Load Current (Amps)
(4)
1.5 VOUT Efficiency, 500 KHz
Figure 13. 3.3 VOUT Efficiency, 500 KHz
FAN2110_1.5V_300Khz
FAN2110_3.3V_300Khz
100
100
95
95
Efficiency (%)
Efficiency (%)
90
85
80
90
85
80
VIN = 10V
VIN = 10V
VIN = 12V
75
VIN = 12V
75
VIN = 16V
VIN = 16V
VIN = 20V
VIN = 20V
70
70
0
2
4
6
8
0
10
2
6
8
10
Load Current (Amps)
Load Current (Am ps)
Figure 15. 3.3 VOUT Efficiency, 300 KHz(4)
Figure 14. 1.5 VOUT Efficiency, 300 KHz
FAN2110_2.5V_600Khz
FAN2110_1.5V_500K(3.3-5.5V)
95
100
90
Efficiency (%)
95
Efficiency (%)
4
90
85
80
VIN = 10V
VIN = 12V
75
85
80
VIN=3.5V
75
VIN = 16V
VIN=4.5V
VIN = 20V
70
VIN=5.5V
70
0
2
4
6
8
10
0
Load Current (Amps)
Figure 16. 2.5 VOUT Efficiency ,600 KHz(4)
2
4
6
Load Current (Amps)
8
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Performance Characteristics
10
Figure 17. 1.5 VOUT Efficiency, 500 KHz
(VIN=3.3 V to 5 V), Figure 11
Note:
4. Circuit values for this configuration change in Figure 10.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
9
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C unless otherwise specified.
Peak HS & LS Mosfet Tempr for 1.5V Output
(Measured on Demo Board)
Package Power Dissipation at various Vout(s)
Fsw = 500Khz
80
3
Power Dissipation (Watts)
Tem peratures(Deg C)
70
60
50
40
30
VIN=10V_HS
20
VIN=10V_LS
VIN=20V_HS
10
2.5
2
1.5
1
Vout = 1.5V
0.5
0
0
1
2
3
4
5
6
7
8
9
Vout = 1.8V
Vout = 3.3V
VIN=20V_LS
0
10
2
4
Load Current (A)
Figure 18. Peak MOSFET Temperatures, Figure 10
Figure 19.
10
Load Regulation
0.05
% Regulation (Compared to Voltage at
No load)
0.02
% Regulation (Compared to Voltage at
12V)
8
Device Dissipation Over VOUT vs. Load
Line Regulation Data
0.01
0
5
10
15
20
25
-0.01
-0.02
-0.03
No Load
1A Load
-0.04
0
0
2
4
6
8
10
-0.05
-0.1
-0.15
-0.2
VIN=10V
VIN=20V
-0.25
Input Voltage (Volts)
Load Current (Amps)
Figure 20. 1.5 VOUT Line Regulation
Figure 21.
Peak HS & LS Mosfet Tempr for 3.3V Output
(Measured on Demo Board)
1.5 VOUT Load Regulation
Safe Operating Area curves for 70 Deg Temperature rise
VIN = 20V, Natural Convection
100
12
10
L o ad Cu rren t (Amp s)
80
Temperatures(Deg C)
6
Load Current (Amps)
60
40
VIN=10V_HS
VIN=10V_LS
20
8
6
4
300K
2
500K
VIN=20V_HS
600K
VIN=20V_LS
0
0
1
2
3
4
5
6
7
Load Current (Amps)
8
9
0
10
2
4
6
8
10
12
14
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Output Voltage (Volts)
Figure 23.
Typical 20 VIN Safe Operation Area
Figure 22. Peak MOSFET Temperatures, 3.3 V Output(5) (SOA), 70°C Ambient Temperature, Natural Convection
Note:
5. Circuit values for this configuration change in Figure 10.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
www.fairchildsemi.com
10
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C unless otherwise specified.
VOUT
VOUT
VSW
EN
PGOOD
PGOOD
Figure 24. Startup, 10 A Load
Figure 25. Startup with 1.0 V Pre-Bias on VOUT
VOUT, 50mV/div
VOUT
VSW, 10V/Div
EN
PGOOD
Figure 26. Shutdown, 10 A Resistive Load
Figure 27.
VOUT Ripple and SW Voltage, 10 A Load
VOUT, 200mV/div
IOUT, 5A/Div
IOUT, 5A/Div
EN, 2V/Div
Figure 28. Transient Response, 0-8 A Load,
5 A / µs Slew Rate
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Figure 29. Restart on Short Circuit (Fault)
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11
PWM Generation
EN
Refer to Figure 2 for the PWM control mechanism.
FAN2110 uses the summing-mode method of control to
generate the PWM pulses. An amplified current-sense
signal is summed with an internally generated ramp and
the combined signal is compared with the output of the
error amplifier to generate the pulse width to drive the
high-side MOSFET. Sensed current from the previous
cycle is used to modulate the output of the summing
block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. RRAMP resistor helps set the charging current for
the internal ramp and provides input voltage feedforward function. The controller facilitates external
compensation for enhanced flexibility.
1.35V
2400 CLKs
0.8V
FB
Fault
Latch
Enable
1.0V
0.8V
SS
3200 CLKs
T0.8
4000 CLKs
Initialization
T1.0
Figure 31. Soft-Start Timing Diagram
Once VCC exceeds the UVLO threshold and EN is HIGH,
the IC checks for a shorted FB pin before releasing the
internal soft-start ramp (SS).
If the parallel combination of R1 and RBIAS is ≤ 1 KΩ, the
internal SS ramp is not released and the regulator does
not start.
VCC UVLO or toggling the EN pin discharges the internal
SS and resets the IC. In applications where external EN
signal is used, VIN and VCC should be established before
the EN signal comes up to prevent skipping the softstart function.
Enable
Startup on Pre-Bias
FAN2110 has an internal pull-up to the enable (EN) pin
so that the IC is enabled once VCC exceeds the UVLO
threshold. Connecting a small capacitor across EN and
AGND delays the rate of voltage rise on the EN pin. The
EN pin also serves for the restart whenever a fault
occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after VCC is established. For
applications where such sequencing is required,
FAN2110 can be enabled (after the VCC comes up) with
external control, as shown in Figure 30.
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76 V). This enables the regulator to startup
on a pre-biased output and ensures that pre-biased
outputs are not discharged during the soft-start cycle.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, undervoltage, and over-temperature conditions.
Under-Voltage Shutdown
If voltage on the FB pin remains below the under-voltage
threshold for 16 consecutive clock cycles, the fault latch
is set and the converter shuts down. This protection is
not active until the internal SS ramp reaches 1.0 V
during soft-start.
Figure 30. Enabling with External Control
Soft-Start
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Circuit Description
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), the fault latch is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold. Normal
sequence for powering up would be VINVCCEN.
Soft-start time is a function of oscillator frequency.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
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12
If voltage on the FB pin exceeds 115% of VREF for two
consecutive clock cycles, the fault latch is set and
shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV/UV fault protection circuits above are active all
the time, including during soft-start.
Over-Temperature Protection (OTP)
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 150°C is reached. The IC restarts when the die
temperature falls below 125°C.
Auto-Restart
Figure 32.
After a fault, EN pin is discharged by a 1 µA current sink
to a 1.1 V threshold before the internal 800 KΩ pull-up is
restored. A new soft-start cycle begins when EN
charges above 1.35 V.
Power-Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin.
Thresholds are specified in the Electrical Specifications
section. PGOOD does not assert HIGH until the fault
latch is enabled (T1.0) (see Figure 31).
Depending on the external circuit, the FAN2110 can be
configured to remain latched-off or to automatically
restart after a fault.
Table 1. Fault / Restart Configurations
EN Pin
Controller / Restart State
Pull to GND
OFF (Disabled)
No Restart – Latched OFF
Pull-up to VCC with 100K
(After VCC Comes Up)
Open
Immediate Restart After Fault
New Soft-Start Cycle After:
Cap. to GND
tDELAY (ms)=3.9 • C(nf)
When EN is left open, restart is immediate.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
Enable Control with Latch Option
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
If auto-restart is not desired, tie the EN pin to the VCC
pin or pull it HIGH after VCC comes up with a logic gate
to keep the 1 µA current sink from discharging EN to
1.1V. Figure 32 shows one method to pull up EN to VCC
for a latch configuration.
Over-Voltage Protection
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13
operate at a lower switching frequency. The inductor
value is calculated by the following formula:
Bias Supply
The FAN2110 requires a 5 V supply rail to bias the IC
and provide gate-drive energy. Connect a ≥ 2.2 µf
X5R or X7R decoupling capacitor between VCC and
AGND.
VO UT
)
Vin
ΔIL • f
where f is the oscillator frequency.
L=
Since VCC is used to drive the internal MOSFET
gates, supply current is frequency and voltage
dependent. Approximate VCC current (ICC) is
calculated by:
VCC − 5
+ 0.013 ) • (f − 128 )]
227
where frequency (f) is expressed in KHz.
ICC ( mA ) = 4.58 + [(
RRAMP resistor plays a critical role in the design by
providing charging current to the internal ramp
capacitor and also serving as a means to provide
input voltage feedforward.
(1)
RRAMP is calculated by the following formula:
R RAMP ( KΩ ) =
The output voltage of the regulator can be set from
0.8V to 80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1). For output voltages >3.3V,
output current rating may need to be de-rated
depending on the ambient temperature, power
dissipated in the package and the PCB layout. (Refer
to Thermal Information table on page 4, Figure 22,
and Figure 23.)
(4)
In all applications, current through the RRAMP pin must
be greater than 10 µA from the equation below for
proper operation:
VIN − 1.8
≥ 10 μA
RRAMP + 2
(1)
(5)
If the calculated RRAMP values in Equation (5) result in
a current less than 10 µA, use the RRAMP value that
satisfies Equation (6). In applications with large Input
ripple voltage, the RRAMP resistor should be
adequately decoupled from the input voltage to
minimize ripple on the ramp pin. For example, see
Figure 11.
If the parallel combination of R1 and RBIAS is ≤ 1KΩ,
the internal SS ramp is not released and the regulator
does not start.
Setting the Current Limit
Setting the Clock Frequency
The current limit system involves two comparators.
The MAX ILIMIT comparator is used with a VILIM fixedvoltage reference and represents the maximum
current limit allowable. This reference voltage is
temperature compensated to reflect the RDSON
variation of the low-side MOSFET. The ADJUST ILIMIT
comparator is used where the current limit needs to
be set lower than the VILIM fixed reference. The 10 µA
current source does not track the RDSON changes over
temperature, so change is added into the equations
for calculating the ADJUST ILIMIT comparator
reference voltage, as is shown below. Figure 33
shows a simplified schematic of the over-current
system.
Oscillator frequency is determined by an external
resistor, RT, connected between the RT pin and AGND.
Resistance is calculated by:
(2)
where RT is in KΩ and frequency (f) is in KHz.
The regulator cannot start if RT is left open.
Calculating the Inductor Value
Typically the inductor value is chosen based on ripple
current (ΔIL), which is chosen between 10 to 35% of
the maximum DC load. Regulator designs that require
fast transient response use a higher ripple-current
setting, while regulator designs that require higher
efficiency keep ripple current on the low side and
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
−2
For wide input operation, first calculate RRAMP for the
minimum and maximum input voltage conditions and
use larger of the two values calculated.
If R1 is open (see Figure 1), the output voltage is not
regulated and a latched fault occurs after the SS is
complete (T1.0).
(10 6 / f ) − 135
65
(VIN − 1.8 ) • VOUT
(31 − 2.05 • IOUT ) • VIN • f • 10 − 6
where frequency (f) is expressed in KHz.
The external resistor divider is calculated using:
RT (KΩ ) =
(3)
Setting the Ramp Resistor Value
Setting the Output Voltage
V
− 0.8V
0.8V
= OUT
+ 650nA
RBIAS
R1
Connect RBIAS between FB and AGND.
VOUT • (1 -
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Application Information
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14
VERR
+
_
the IC’s internal default current limit is fairly high. This
could lead to operation at high load currents, causing
overheating of the regulator. For a given RILIM and
RRAMP setting, the current limit point varies slightly in
an inverse relationship with respect to input voltage
(VIN).
PWM
COMP
PWM
VCC
VILIM
+
_
MAX
ILIMIT
Loop Compensation
10µA
+
_
ILIM
ADJUST
ILIMIT
The loop is compensated using a feedback network
around the error amplifier. Figure 34 shows a
complete type-3 compensation network. For type-2
compensation, eliminate R3 and C3.
ILIMTRIP
RILIM
Figure 33. Current-Limit System Schematic
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting
the reference voltage is:
VRILIM = 10µA*RILIM
(6)
To calculate RILIM:
RILIM = VRILIM/ 10µA
(7)
Figure 34. Compensation Network
The voltage VRILIM is made up of two components,
VBOT (which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
RILIM = (VBOT + VRMPEAK)/ 10µA
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW *0.03*RRAMP)}/10µA
Since the FAN2110 employs summing current-mode
architecture, type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, type-3 compensation may be required.
(8)
RRAMP also provides feedforward compensation for
changes in VIN. With a fixed RRAMP value, the
modulator gain increases as VIN is reduced, which
could make it difficult to compensate the loop. For
low-input-voltage-range designs (3 V to 8 V), RRAMP
and the compensation component values are different
compared to designs with VIN between 8 V and 24 V.
(9)
where:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW *0.03*RRAMP);
ILOAD = the desired maximum load current;
RDSON = the nominal RDSON of the low-side
MOSFET;
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
D = VOUT/VIN duty cycle;
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in kΩ.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
RAMP
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
Always use an external resistor RILIM to set the current
limit at the desired level. When RILIM is not connected,
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
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15
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Recommended PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with two-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect the AGND pin to PGND
at the output OR to the PGND plane.
SW
VIN
GND
GND
VOUT
Figure 35. Recommended PCB Layout
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
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16
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
OPTIONAL LEAD DESIGN
(LEADS# 1, 24 & 25 ONLY)
SCALE: 1.5X
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV3
BOTTOM VIEW
Figure 36. 5x6 mm Molded Leadless Package (MLP)
FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.4
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FAN2110 — TinyBuck™, 3-24 V Input, 10 A, High-Efficiency, Integrated Synchronous Buck Regulator
18
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© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.04