FAIRCHILD FAN2108_12

FAN2108 — TinyBuck™
3-24 V Input, 8 A, High-Efficiency, Integrated
Synchronous Buck Regulator
Features
Description
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Wide Input Voltage Range: 3 V-24 V
The FAN2108 TinyBuck™ is a highly efficient, small
footprint, 8 A, synchronous buck regulator.


Over 95% Peak Efficiency
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Internal Bootstrap diode
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Internal Soft-Start
Wide Output Voltage Range: 0.8 V to 80% VIN
8 A Output Current
Programmable Frequency Operation: 200 KHz to
600 KHz
Integrated Schottky Diode on Low-side MOSFET
Boosts Efficiency
Power-Good Signal
Pre-Bias Startup
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Input Under-Voltage Lockout
Programmable Current Limit
Under-Voltage, Over-Voltage, and Thermal
Shutdown Protections
5x6mm, 25-Pin, 3-Pad MLP Package
Applications
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The FAN2108 contains both synchronous MOSFETs
and a controller/driver with optimized interconnects in
one package, which enables designers to solve highcurrent requirements in a small area with minimal
external components.
External compensation, programmable switching
frequency, and current limit features allow design
optimization and flexibility.
The summing current mode modulator uses lossless
current sensing for current feedback and over-current
protection. Voltage feedforward helps operation over a
wide input voltage range.
Fairchild’s advanced BiCMOS power process, combined
with low-RDS(ON) internal MOSFETs and a thermally
efficient MLP package, provide the ability to dissipate
high power in a small package.
Output over-voltage, under-voltage, and thermal
shutdown protections help protect the device from
damage during fault conditions. FAN2108 prevents
pre-biased output discharge during startup in point-ofload applications.
Related Application Notes
Servers
AN-8022 — TinyCalc™ Calculator
Point-of-Load Regulation
High-End Computing Systems
Graphics Cards
Battery-Powered Equipment
Set-Top Boxes
Ordering Information
Part Number
Operating Temperature
Range
Package
Packing
Method
FAN2108MPX
FAN2108EMPX
-10°C to 85°C
-40°C to 85°C
Molded Leadless Package (MLP) 5x6 mm
Molded Leadless Package (MLP) 5x6 mm
Tape and Reel
Tape and Reel
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
November 2012
IN
P2
+5V
CHF
CIN
VCC
C4
15
1
BOOT
Q1
RRAMP
RAMP
Power
Good
PGOOD
Enable
EN
RILIM
ILIM
RT
R(T)
COMP
C2
C1
Boot
Diode
AGND
CBOOT
25
13
14
17
Q2
P1
PWM
+
DRIVER
18
L
COUT
POWER
MOSFETS
20
OUT
SW
P3
24 NC
19
16
PGND
R1
FB
C3
RBIAS
R2
R3
Figure 1. Typical Application Diagram
Block Diagram
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Application
Figure 2. Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
2
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pin Definitions
Pin #
Name
P1, 6-12
SW
Switching Node.
Description
P2, 2-5
VIN
Power Input Voltage. Connect to the main input power source.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes
an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when
SW is LOW.
13
PGOOD
Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range
of the reference. PGOOD does not assert HIGH until the fault latch is enabled.
14
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
15
VCC
16
AGND
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the default setting.
18
R(T)
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
24
NC
25
RAMP
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
Compensation. Error amplifier output. Connect the external compensation network between
this pin and FB.
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Pin Configuration
No Connect. This pin is not used.
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp amplitude
and provides voltage feedforward functionality.
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
VIN to PGND
VCC to AGND
AGND=PGND
SW to PGND
Continuous
ESD
28
V
6
V
V
-0.3
6.0
V
-0.5
24.0
V
-5
30
V
-0.3
VCC+0.3
V
Transient (t < 20 ns, f < 600 KHz)
All other pins
Unit
35
BOOT to PGND
BOOT to SW
Max.
Human Body Model, JEDEC JESD22-A114
2
Charged Device Model, JEDEC JESD22-C101
kV
2.5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
5.0
5.5
V
24
V
VCC
Bias Voltage
VCC to AGND
4.5
VIN
Supply Voltage
VIN to PGND
3
TA
Ambient Temperature
TJ
f
FAN2108MPX
-10
+85
°C
FAN2108EMPX
-40
+85
°C
Junction Temperature
+125
°C
Switching Frequency
600
kHz
Max.
Unit
+150
°C
+300
°C
Thermal Information
Symbol
TSTG
TL
TVP
TI
θJC
θJ-PCB
PD
Parameter
Min.
Storage Temperature
Typ.
-65
Lead Soldering Temperature, 10 Seconds
Vapor Phase, 60 Seconds
+215
°C
Infrared, 15 Seconds
+220
°C
Thermal Resistance: Junction-to-Case
P1 (Q2)
4
P2 (Q1)
7
°C/W
P3
4
°C/W
35
°C/W
Thermal Resistance: Junction-to-Mounting Surface(1)
(1)
Power Dissipation, TA=25°C
°C/W
2.8
W
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 25. Actual results
are dependent on mounting method and surface related to the design.
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical specifications are the result of using the circuit shown in Figure 1 unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
Power Supplies
ICC
VUVLO
VCC Current
SW=Open, FB=0.7 V, VCC=5 V,
fSW =600 KHz
8
12
mA
Shutdown: EN=0, VCC=5 V
7
10
µA
4.3
4.5
Rising VCC
VCC UVLO Threshold
4.1
Hysteresis
300
V
mV
Oscillator
f
tON
VRAMP
tOFF
Frequency
RT=50 KΩ
255
300
345
KHz
RT=24 KΩ
540
600
660
KHz
50
65
ns
(2)
Minimum On-Time
Ramp Amplitude, peak-to–peak
16 VIN, 1.8 VOUT, RT=30 KΩ,
RRAMP=200 KΩ
0.53
Minimum Off-Time(2)
100
V
150
ns
Reference
VFB
FAN2108MPX, 25°C
794
800
806
mV
FAN2108EMPX, 25°C
795
800
805
mV
80
85
dB
VCC=5 V
12
15
MHz
Output Current, Sourcing
VCC=5 V, VCOMP=2.2 V
1.5
Output Current, Sinking
VCC=5 V, VCOMP=1.2 V
FB Bias Current
VFB=0.8 V, 25°C
Reference Voltage (see Figure 4 for
Temperature Coefficient)
Error Amplifier
G
BW
VCOMP
ISINK
ISOURCE
IBIAS
DC Gain(2)
(2)
Gain Bandwidth Product
Output Voltage
0.4
3.2
2.2
V
mA
0.8
1.2
-850
-650
-450
mA
nA
12
15
18
A
-10
-9
µA
Protection and Shutdown
ILIM
Current Limit
IILIM
ILIM Current
TTSD
Over-Temperature Shutdown
RILIM Open at 25°C (see Circuit
Description)
-11
+155
Internal IC Temperature
°C
THYS
Over-Temperature Hysteresis
VOVP
Over-Voltage Threshold
Two Consecutive Clock Cycles
110
+30
115
121
%VOUT
°C
VUVLO
Under-Voltage Shutdown
16 Consecutive Clock Cycles
68
73
78
%VOUT
VFLT
Fault Discharge Threshold
Measured at FB Pin
250
mV
VFLT_HYS
Fault Discharge Hysteresis
Measured at FB Pin (VFB ~500 mV)
250
mV
5.3
ms
6.7
ms
Soft-Start
tSS
VOUT to Regulation (T0.8)
tEN
Fault Enable/SSOK (T1.0)
Frequency=600 KHz
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications
Note:
2. Specifications guaranteed by design and characterization; not production tested.
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
5
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
EN Threshold, Rising
1.35
V
EN Hysteresis
250
mV
800
KΩ
1
µA
Control Functions
VEN_R
VEN_HYS
REN
EN Pull-Up Resistance
IEN
EN Discharge Current
RFB
FB OK Drive Resistance
VPG
PGOOD Threshold
VPG_L
PGOOD Output Low
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
Auto-Restart Mode
2.00
800
FB < VREF
-14
-11
-8
FB > VREF
+7
+10
+13.5
IOUT < 2 mA
0.4
Ω
%VREF
V
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Electrical Specifications (Continued)
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6
1.20
1.005
1.10
I FB
V FB
1.010
1.000
0.995
1.00
0.90
0.990
0.80
-50
0
50
100
150
-50
0
Temperature (oC)
Figure 4. Reference Voltage (VFB)
vs. Temperature, Normalized
1200
1.01
Frequency
Frequency (KHz)
150
1.02
900
600
600KHz
1.00
300KHz
0.99
300
0.98
0
0
20
40
60
80
100
120
-50
140
0
100
150
Temperature ( C)
Figure 6. Frequency vs. RT
Figure 7.
1.04
1.2
1.02
I ILIM
1.4
Q1 ~0.32%/°C
1
50
o
RT (KΩ)
RDS
100
Figure 5. Reference Bias Current (IFB)
vs. Temperature, Normalized
1500
Q2 ~0.35%/°C
Frequency vs. Temperature, Normalized
1.00
0.98
0.8
0.6
-50
50
Temperature (oC)
0.96
0
50
100
150
-50
50
100
150
o
Temperature ( C)
Temperature (°C)
Figure 9.
Figure 8. RDS vs. Temperature, Normalized
(VCC=VGS=5V)
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
0
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical Characteristics
ILIM Current (IILIM) vs. Temperature,
Normalized
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7
VCC
+5V
1.0u
P2
15
VIN
8-20 VIN
10K
X5R
PGOOD
200K
13
VOUT
3.3n
3 x 4.7u
X7R
NC 24
2.49K
62
COMP
2.49K
4.7n
RAMP
25
20
56p
FB
1
19
* Inter-Technical
SC7232-2R2M
BOOT
4.7n
ILIM
EN
200K
R(T)
0.1u
17
14
P1
VOUT
SW
2.2u *
18
1.5
30.1K
2.00K
4 x 22u
AGND
3.3n
P3 PGND
16
X5R
390p
Figure 10. Application Circuit: 1.8 VOUT, 500 KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, VCC=5 V, unless otherwise specified.
0
Efficiency @ Vo=1.8V, fsw=500KHz, Ta=25 C
0
Efficiency @ Vo=3.3V, fsw=300KHz, Ta=25 C
100
95
95
Efficiency (%)
Efficiency (%)
90
85
Vin=8V
Vin=12V
80
Vin=16V
Vin=20V
75
90
80
Vin=12V
4
6
Vin=20V
70
8
0
Load Current (A)
Figure 11.
Vin=10V
Vin=14V
70
2
Vin=5V
75
Vin=24V
0
85
1.8 VOUT Efficiency Over VIN vs. Load
2
4
Load Current (A)
6
8
Figure 12. 3.3 VOUT Efficiency Over VIN vs. Load
[email protected] Vin=12V, Vo=1.8V
Load Regulation @ Vo=0.8V, 500kHz, 25°C
0.8012
Vin=8V
0.801
90
Output Voltage (V)
Efficiency (%)
95
85
80
300KHz
500KHz
75
600KHz
Vin=12V
0.8008
Vin=16V
0.8006
Vin=20V
0.8004
Vin=24V
0.8002
0.8
0.7998
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Application Circuit
0.7996
70
0.7994
0
1
2
3
4
5
6
7
0.7992
8
0
Load Current (A)
1
2
3
4
5
6
7
8
Load Current (A)
Figure 13. 1.8 VOUT Efficiency Over Frequency
vs. Load
Figure 14. 0.8 VOUT Load Regulation Over VIN
vs. Load
Typical Performance Characteristics (Continued)
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
8
VOUT
VOUT
SW
PGOOD
EN
EN
Figure 15. Startup, 3 A Load
Figure 16. Startup with 1 V Pre-Bias on Vout
SW
VOUT
PGOOD
EN
EN
Figure 17. Shutdown, 1 A Load
Figure 18.
Restart on Fault
HS and LS MOSFET Temperature
90
VOUT
[email protected] 20Vin
T e mp e ra tu re ( °C)
80
IOUT
[email protected] 12Vin
[email protected] 20Vin
70
[email protected] 12Vin
60
50
40
30
20
0
2
4
6
8
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, VCC=5 V, unless otherwise specified.
Load Current (A)
Figure 20. MOSFET Temperature – Still Air at Room
Temperature
Figure 19. Transient Response, 2-8 A Load
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
9
Initialization
Soft-Start
Once VCC exceeds the UVLO threshold and EN is HIGH,
the IC checks for an open or shorted FB pin before
releasing the internal soft-start ramp (SS).
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), the fault latch is inhibited.
If R1 is open (Figure 1), the error amplifier output
(COMP) is forced LOW and no pulses are generated.
After the SS ramp times out (T1.0), an under-voltage
latched fault occurs.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold.
Soft-start time is a function of oscillator frequency.
If the parallel combination of R1 and RBIAS is ≤ 1 KΩ, the
internal SS ramp is not released and the regulator does
not start.
EN
2400 CLKs
Bias Supply
The FAN2108 requires a 5 V supply rail to bias the IC
and provide gate-drive energy. Connect a ≥ 1.0 µf X5R
or X7R decoupling capacitor between VCC and PGND.
VCC − 5
+ 0.013 ) • (f − 128 )]
227
where frequency (f) is expressed in KHz.
0.8V
FB
Fault
Latch
Enable
1.0V
0.8V
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) is calculated by:
ICC ( mA ) = 4.58 + [(
1.35V
SS
(1)
3200 CLKs
T0.8
4000 CLKs
Enable
T1.0
Figure 21. Soft-Start Timing Diagram
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until
internal SS ramp reaches 95% of VREF (~0.76 V). This
helps the regulator to start on a pre-biased output and
ensures that inductor current does not "ratchet" up
during the soft-start cycle.
FAN2108 has an internal pull-up to enable pin so that
the IC is enabled once VCC is applied. Connecting a
small capacitor across EN and AGND delays the rate of
voltage rise on the EN pin. EN pin also serves for the
restart whenever a fault occurs (refer to the Auto-Restart
section). For applications where sequencing is required,
FAN2108 can be enabled (after the VCC comes up) with
external control, as shown in Figure 20.
VCC UVLO or toggling the EN pin discharges the SS and
resets the IC.
Setting the Output Voltage
The output voltage of the regulator can be set from
0.8 V to 80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1).
The internal reference is 0.8 V with 650 nA, sourced
from the FB pin to ensure that, if the pin is open, the
regulator does not start.
Figure 20. Enabling with External Control
Setting the Frequency
The external resistor divider is calculated using:
Oscillator frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND.
Resistance is calculated by:
V
− 0.8V
0.8V
= OUT
+ 650nA
RBIAS
R1
Connect RBIAS between FB and AGND.
(10 6 / f ) − 135
65
where RT is in KΩ and frequency (f) is in KHz.
RT (KΩ ) =
(3)
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Circuit Description
(2)
The regulator cannot start if RT is left open.
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
10
Typically the inductor is set for a ripple current (ΔIL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the high
side of this range; while regulators that require very low
output ripple and/or use high-ESR capacitors restrict
allowable ripple current.
V
VOUT • (1 - OUT )
VIN
L=
ΔIL • f
(4)
RILIM = (VBOT + VRMPEAK)/ 10µA
(8)
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW *0.03*RRAMP)}/10µA
(9)
where f is the oscillator frequency.
where:
Setting the Ramp Resistor Value
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW *0.03*RRAMP);
The internal ramp voltage excursion (∆VRAMP) during tON
should be set to 0.6 V at nominal operating point. RRAMP
is approximately:
RRAMP (KΩ ) =
(VIN − 1.8) • VOUT
18 x10 − 6 • VIN • f
(7)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
ILOAD = the desired maximum load current;
RDSON = the nominal RDSON of the low-side MOSFET;
−2
(5)
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
where frequency (f) is expressed in KHz.
D = VOUT/VIN duty cycle;
Setting the Current Limit
fSW = Clock frequency in kHz; and
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the lowside MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 22 shows a simplified schematic of the overcurrent system.
RRAMP = chosen ramp resistor value in kΩ.
RAMP
VERR
+
_
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
Loop Compensation
The loop is compensated using a feedback network
around the error amplifier. Figure 23 shows a complete
type-3 compensation network. For type-2 compensation,
eliminate R3 and C3.
PWM
COMP
PWM
VCC
VILIM
+
_
MAX
ILIMIT
10µA
+
_
ILIM
ADJUST
ILIMIT
ILIMTRIP
RILIM
Figure 23. Compensation Network
Figure 22. Current-Limit System Schematic
Since the FAN2108 employs summing current-mode
architecture, type-2 compensation can be used for many
applications. For applications that require wide loop
bandwidth and/or use very low-ESR output capacitors,
type-3 compensation may be required.
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
VRILIM = 10µA*RILIM
(6)
Protection
To calculate RILIM:
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
RILIM = VRILIM/ 10µA
Calculating the Inductor Value
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11
An internal fault latch is set for any fault intended to shut
down the IC. When the fault latch is set, the IC
discharges VOUT by enhancing the low-side MOSFET
until FB<0.25 V. The MOSFET is not turned on again
unless FB>0.5 V. This behavior discharges the output
without causing undershoot (negative output voltage).
15 VCC
100K
Under-Voltage Shutdown
FAN2108
14 EN
If voltage on the FB pin remains below the under-voltage
threshold for 16 consecutive clock cycles, the fault latch
is set and the converter shuts down. This protection is
not active until the internal SS ramp reaches 1.0 V
during soft-start.
3.3n
Figure 24.
Over-Voltage Protection / Shutdown
If voltage on the FB pin exceeds the over-voltage
threshold for two consecutive clock cycles, the fault latch
is set and shutdown occurs.
Enable Control with Latch Option
Over-Temperature Protection (OTP)
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 150°C is reached. The IC restarts when the die
temperature falls below 125°C.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
Power-Good (PGOOD) Signal
The two fault protection circuits above are active all the
time, including during soft-start.
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin.
Thresholds are specified in the Electrical Specifications
section. PGOOD does not assert HIGH until the fault
latch is enabled (T1.0).
Auto-Restart
After a fault, EN pin is discharged by a 1 µA current sink
to a 1.1 V threshold before the internal 800 KΩ pull-up is
restored. A new soft-start cycle begins when EN
charges above 1.35 V.
PCB Layout
Depending on the external circuit, the FAN2108 can be
configured to remain latched-off or to automatically
restart after a fault.
Table 1. Fault / Restart Configurations
EN Pin
Controller / Restart State
Pull to GND
Pull-up to VCC with
100K
Open
OFF (Disabled)
No Restart – Latched OFF(After
VCC Comes Up)
Immediate Restart After Fault
New Soft-Start Cycle After:
tDELAY (ms)=3.9 • C(nf)
Cap. to GND
With EN is left open, restart is immediate.
Figure 25. Recommended PCB Layout
If auto-restart is not desired, tie the EN pin to the VCC
pin or pull it HIGH after VCC comes up with a logic gate
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
to keep the 1 µA current sink from discharging EN to
1.1 V. Figure 24 shows one method to pull up EN to VCC
for a latch configuration.
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, undervoltage, and over-temperature conditions.
www.fairchildsemi.com
12
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
OPTIONAL LEAD DESIGN
(LEADS# 1, 24 & 25 ONLY)
SCALE: 1.5X
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV3
BOTTOM VIEW
Figure 26. 5x6 mm Molded Leadless Package (MLP)
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2
www.fairchildsemi.com
13
FAN2108 — TinyBuck™, 3-24 V Input, 8 A, High-Efficiency, Integrated Synchronous Buck Regulator
14
www.fairchildsemi.com
© 2008 Fairchild Semiconductor Corporation
FAN2108 • Rev. 1.0.2